JPH09120998A - Flash eeprom cell, its preparation, program method and read method - Google Patents

Flash eeprom cell, its preparation, program method and read method

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Publication number
JPH09120998A
JPH09120998A JP8118037A JP11803796A JPH09120998A JP H09120998 A JPH09120998 A JP H09120998A JP 8118037 A JP8118037 A JP 8118037A JP 11803796 A JP11803796 A JP 11803796A JP H09120998 A JPH09120998 A JP H09120998A
Authority
JP
Japan
Prior art keywords
flash eeprom
eeprom cell
drain
floating gates
control gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8118037A
Other languages
Japanese (ja)
Other versions
JP2828951B2 (en
Inventor
Fukudan So
福男 宋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hyundai Electronics Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Industries Co Ltd filed Critical Hyundai Electronics Industries Co Ltd
Publication of JPH09120998A publication Critical patent/JPH09120998A/en
Application granted granted Critical
Publication of JP2828951B2 publication Critical patent/JP2828951B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
    • G11C16/0458—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates comprising two or more independent floating gates which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7887—Programmable transistors with more than two possible different levels of programmation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/561—Multilevel memory cell aspects
    • G11C2211/5612—Multilevel memory cell with more than one floating gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

PROBLEM TO BE SOLVED: To store and output quaternary information in accordance with the program and erasure of two floating gates by forming the floating gates above a channel area. SOLUTION: After a tunnel oxide film 2 is grown on a silicon substrate 1, a first polysilicon layer 3 is formed on the film 2 and first and second floating gates 3A and 3B are formed horizontally adjacently to each other by patterning the polysilicon layer 3. A source 5 and drain 6 are formed by injecting the ion of an impurity into the substrate 1 and a dielectric film 7 and a second polysilicon layer 8 are formed on the entire surface. After the layer 8 is formed, the dielectric film 7 and a control gate 8A are laminated on the floating gates 3A and 3B by successively etching the layer 8 and film 7. Therefore, quaternary information can be programmed and read out through the gates 3A and 3B.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、フラッシュＥＥＰ
ＲＯＭ（ｆｌａｓｈ ＥＥＰＲＯＭ）セル、その製造方
法、プログラム及び読出方法に関わり、特にチャネル
（ｃｈａｎｎｅｌ）領域の上部に２個のフローティング
ゲート（ｆｌｏａｔｉｎｇ ｇａｔｅ）を形成し、この
２個のフロテイングゲート各々のプログラム及び消去の
如何に従い、４進情報の出力を得られるようにしたフラ
ッシュＥＥＰＲＯＭセル、その製造方法、プログラム
（書込）及び読出方法に関するものである。The present invention relates to a flash EEP.
The present invention relates to a flash (EEPROM) cell, a method of manufacturing, a method of programming, and a method of reading. In particular, two floating gates are formed above a channel region, and each of the two floating gates is programmed. The present invention relates to a flash EEPROM cell capable of obtaining an output of quaternary information in accordance with the method of erasing and erasing, a method of manufacturing the same, and a method of programming (writing) and reading.

【０００２】[0002]

【従来の技術】一般的に、電気的プログラム（ｐｒｏｇ
ｒａｍ）及び消去（ｅｒａｓｅ）が可能な機能を合わせ
持つ、フラシュＥＥＰＲＯＭ（Ｅｌｅｃｔｒｉｃａｌｌ
ｙ Ｅｒａｓａｂｌｅ Ｐｒｏｇｒａｍａｂｌｅ Ｒｅ
ａｄ Ｏｎｌｙ Ｍｅｍｏｒｙ；ＥＥＰＲＯＭ）素子
は、その固有の長所により需要が次第に増大する実情で
ある。このようなフラッシュＥＥＰＲＯＭ素子は、一個
のセルに２進情報、即ち、”０”又は”１”だけをプロ
グラム或いは読出するので一バイト（ｂｙｔｅ；８個の
セル）で表示が可能な情報量は２５６（＝２8 ）個であ
る。更に、一個のセルが４進情報、即ち、”０”、”
１”、”２”及び”３”を持つとすれば、一バイトの情
報量は６５５３６（＝４8 ）個になるので、２進セルが
持つ情報量より２５６倍多くの情報量を持つことができ
る。即ち、一ギガ（ｇｉｇａ）以上の容量を持つメモリ
素子の具現が可能となる。2. Description of the Related Art Generally, an electrical program is used.
flash EEPROM (Electrical), which has a function capable of performing erasing (erasing) and erasing (erasing).
y Erasable Programmable Re
The ad-only memory (EEPROM) element is a situation in which demand is gradually increased due to its inherent advantages. In such a flash EEPROM device, since only binary information, that is, "0" or "1" is programmed or read in one cell, the amount of information that can be displayed in one byte (eight cells) is limited. There are 256 (= 2 8 ) pieces. Further, one cell contains quaternary information, that is, “0”, “0”.
If it has 1 "," 2 "and" 3 ", the information amount of one byte is 65536 (= 4 8 ). Therefore, the information amount of the binary cell is 256 times larger than that of the binary cell. That is, a memory device having a capacity of 1 giga or more can be realized.

【０００３】[0003]

【発明が解決しようとする課題】従って、本発明は、チ
ャネル領域の上部に、２個のフローティングゲートを形
成し、その２個のフローティングゲート各々のプログラ
ム及び消去の如何に従い、４進情報の記憶及び出力を得
ることができるようにするフラッシュＥＥＰＲＯＭ素子
を具現することにより、上記の短所を解消することがで
きるフラッシュＥＥＰＲＯＭセル、その製造方法、プロ
グラム及び読出方法を提供することにその目的がある。Accordingly, the present invention forms two floating gates above a channel region and stores quaternary information according to the programming and erasing of each of the two floating gates. It is another object of the present invention to provide a flash EEPROM cell capable of solving the above-mentioned disadvantages by implementing a flash EEPROM element capable of obtaining an output, a method of manufacturing the same, a program and a reading method.

【０００４】[0004]

【課題を解決するための手段】上記の目的を達成するた
めの本発明によるフラッシュＥＥＰＲＯＭセルは、水平
に隣接し、トンネル酸化膜により下部のシリコン基板と
電気的に分離される第１及び第２フローティングゲート
と、上記第１及び第２フローティングゲートを含む上部
面に形成される、誘電体膜と、上記誘電体膜の上部に形
成され、上記誘電体膜により上記第１及び第２フローテ
ィングゲートと電気的に分離されるコントロールゲート
と、上記シリコン基板に形成され、上記第１及び第２フ
ローティングゲート各々の外側部と一部重なり形成され
るソース及びドレーンとからなることを特徴とする。SUMMARY OF THE INVENTION In order to achieve the above object, a flash EEPROM cell according to the present invention comprises first and second horizontally adjacent cells electrically separated from a lower silicon substrate by a tunnel oxide film. A floating gate; a dielectric film formed on an upper surface including the first and second floating gates; and a first dielectric film formed on the dielectric film, and the first and second floating gates formed by the dielectric film. An electrical isolation control gate, and a source and a drain formed on the silicon substrate and partially overlapping the outer portions of the first and second floating gates.

【０００５】上記フラッシュＥＥＰＲＯＭセルの第１実
施例の製造方法は、シリコン基板上にトンネル酸化膜及
び第１ポリシリコン層を順次に形成する段階と、上記段
階から、上記第１ポリシリコン層をパターニングして第
１及び第２フローティングゲートを各々形成する段階
と、上記段階から、上記第１及び第２フローティングゲ
ート間のシリコン基板を除外した全体領域に、不純物イ
オンを注入してソース及びドレーンを形成する段階と、
上記段階から、全体上部面に誘電体膜及び第２ポリシリ
コン層を順次に形成する段階と、上記段階から、上記第
２ポリシリコン層及び誘電体膜を順次にパターニングし
て、コントロールゲートを形成する段階でなることを特
徴とする。The method of manufacturing the flash EEPROM cell according to the first embodiment includes the steps of sequentially forming a tunnel oxide film and a first polysilicon layer on a silicon substrate, and patterning the first polysilicon layer from the above steps. Forming first and second floating gates, respectively, and implanting impurity ions into the entire region excluding the silicon substrate between the first and second floating gates from the above step to form a source and a drain. To do,
From the above step, a dielectric film and a second polysilicon layer are sequentially formed on the entire upper surface, and from the above step, the second polysilicon layer and the dielectric film are sequentially patterned to form a control gate. It is characterized in that it is a stage to do.

【０００６】第２実施例の製造方法は、シリコン基板上
にトンネル酸化膜及び第１ポリシリコン層を順次に形成
する段階と、上記段階から、第１フローティングゲート
及び第２フローティングゲートの間に上記第１ポリシリ
コン層をパターニングする段階と、上記段階から、上部
面全体に誘電体膜及び第２ポリシリコン層を順次に形成
する段階と、上記段階から、コントロールゲート電極用
マスクを利用した写真及びエッチング工程により、上記
第２ポリシリコン層、上記誘電体膜、及び上記第１及び
第２フローティングゲートを順次にパターニングする段
階と、上記段階から、シリコン基板に不純物イオンを注
入してソース及びドレーンを形成する段階とからなるこ
とを特徴とする。The manufacturing method according to the second embodiment includes the steps of sequentially forming a tunnel oxide film and a first polysilicon layer on a silicon substrate, and, from the above step, the step of forming a tunnel oxide film and a first polysilicon layer between the first floating gate and the second floating gate. Patterning the first polysilicon layer, forming a dielectric film and a second polysilicon layer sequentially on the entire upper surface from the above step, and photographing using a control gate electrode mask from the above step. Patterning the second polysilicon layer, the dielectric film, and the first and second floating gates sequentially by an etching process; and implanting impurity ions into the silicon substrate to form a source and a drain from the step. And forming.

【０００７】本発明による、フラッシュＥＥＰＲＯＭセ
ルのプログラム方法は、第１及び第２フローティングゲ
ートに、ホットエレクトロンが注入されるように、コン
トロールゲート、ソース及びドレーンにバイアス電圧を
印加した後、上記コントロールゲート、ソース及びドレ
ーンに印加されるバイアス電圧の条件に従い、上記第１
及び第２フローティングゲートに注入されるホットエレ
クトロンを選択的に消去して４進情報がプログラムされ
るようにすることを特徴とする。The method of programming a flash EEPROM cell according to the present invention includes the steps of applying a bias voltage to a control gate, a source, and a drain so that hot electrons are injected into the first and second floating gates. , According to the conditions of the bias voltage applied to the source and the drain.
And selectively erasing hot electrons injected into the second floating gate to program quaternary information.

【０００８】上記フラッシュＥＥＰＲＯＭセルの読出方
法は、第１及び第２フローティングゲートに、選択的に
注入されるホットエレクトロンにより、プログラムされ
た４進情報を読出するため、順方向読出及び逆方向読出
を各々実施した後、ドレーン及びソース電流の有無によ
り貯蔵された情報が読出されることを特徴とする。In the above-mentioned method of reading a flash EEPROM cell, the quaternary information programmed by the hot electrons selectively injected into the first and second floating gates is read. After each operation, the stored information is read according to the presence or absence of the drain and source currents.

【０００９】[0009]

【発明の実施の形態】以下、添付された図面を参照して
本発明を詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the attached drawings.

【００１０】図１Ａ乃至図１Ｅは、本発明による、フラ
ッシュＥＥＰＲＯＭセルの第１実施例の製造方法を説明
するための素子の断面図である。FIGS. 1A to 1E are cross-sectional views of a device for explaining a method of manufacturing a flash EEPROM cell according to a first embodiment of the present invention.

【００１１】図１Ａは、シリコン基板（１）上にトンネ
ル酸化膜（ｔｕｎｎｅｌ ｏｘｉｄｅ；２）を８０乃至
１２０Åの厚さに成長させた後、第１ポリシリコン層
（３）を形成した状態の断面図である。FIG. 1A is a cross-sectional view showing a state in which a tunnel oxide film (2) is grown on a silicon substrate (1) to a thickness of 80 to 120 ° and a first polysilicon layer (3) is formed. FIG.

【００１２】図１Ｂは、フローティングゲート電極用マ
スク（図示されていない）を利用した、写真及びエッチ
ング工程により上記第１ポリシリコン層（３）をパター
ニングして、水平に隣接する第１及び第２フローティン
グゲート（３Ａ及び３Ｂ）を各々形成した状態の断面図
である。FIG. 1B illustrates a first and second horizontally adjacent first and second polysilicon layers 3 patterned by a photo and etching process using a floating gate electrode mask (not shown). It is sectional drawing in the state where each of the floating gates (3A and 3B) was formed.

【００１３】図１Ｃは、全体面に感光膜（４）を塗布し
た後、上記第１及び第２フローティングゲート（３Ａ及
び３Ｂ）の上部及び間にだけ感光膜（４）が残留される
ようにパターニングし、露出されたシリコン基板（１）
に不純物イオンを注入して、ソース及びドレーン（５乃
至６）を形成した状態の断面図である。FIG. 1C shows that after the photosensitive film 4 is coated on the entire surface, the photosensitive film 4 remains only above and between the first and second floating gates 3A and 3B. Patterned and exposed silicon substrate (1)
FIG. 6 is a cross-sectional view showing a state in which a source and a drain (5 and 6) are formed by implanting impurity ions into the substrate.

【００１４】図１Ｄは、全体上部面に、誘電体膜（７）
及び第２ポリシリコン層（８）を順次に形成した状態の
断面図であり、又、誘電体膜（７）は酸化膜−窒化膜−
酸化膜の順に形成されたＯＮＯ構造である。FIG. 1D shows a dielectric film (7) on the entire upper surface.
FIG. 4 is a cross-sectional view showing a state in which a second polysilicon layer (8) and a second polysilicon layer (8) are sequentially formed, and a dielectric film (7) is an oxide film-nitride film-
An ONO structure is formed in the order of the oxide films.

【００１５】図１Ｅは、コントロールゲート電極用マス
ク（図示されていない）を利用した写真及びエッチング
工程により、上記第２ポリシリコン層（８）及び誘電体
膜（７）を順次にエッチングして上記第１及び第２フロ
ーティングゲート（３Ａ及び３Ｂ）上部に誘電体膜
（７）及びコントロールゲート（８Ａ）が積層されたＥ
ＥＰＲＯＭセルを形成した状態の断面図である。In FIG. 1E, the second polysilicon layer 8 and the dielectric film 7 are sequentially etched by a photo and etching process using a control gate electrode mask (not shown). The dielectric film 7 and the control gate 8A are stacked on the first and second floating gates 3A and 3B.
FIG. 3 is a cross-sectional view showing a state where an EPROM cell is formed.

【００１６】図２Ａ乃至図２Ｄは、本発明によるフラッ
シュＥＥＰＲＯＭセルの第２実施例の製造方法を説明す
るための素子の断面図である。2A to 2D are cross-sectional views of a device for explaining a method of manufacturing a flash EEPROM cell according to a second embodiment of the present invention.

【００１７】図２Ａは、シリコン基板（１）上にトンネ
ル酸化膜（２）を８０乃至１２０Åの厚さに成長させた
後、第１ポリシリコン層（３）を形成した状態の断面図
である。FIG. 2A is a sectional view showing a state in which a tunnel oxide film (2) is grown on a silicon substrate (1) to a thickness of 80 to 120 ° and a first polysilicon layer (3) is formed. .

【００１８】図２Ｂは、写真及びエッチング工程によ
り、第１及び第２フローティングゲート（３Ａ及び３
Ｂ）の間の上記第１ポリシリコン層（３）をパターニン
グした状態の断面図である。FIG. 2B shows the first and second floating gates (3A and 3A) formed by photo and etching processes.
It is sectional drawing of the state which patterned the said 1st polysilicon layer (3) during B).

【００１９】図２Ｃは、全体上部面に誘電体膜（７）及
び第２ポリシリコン層（８）を順次に形成した状態の断
面図であり、又、上記誘電体膜（７）は酸化膜−窒化膜
−酸化膜の順に形成されたＯＮＯ構造である。FIG. 2C is a sectional view showing a state in which a dielectric film (7) and a second polysilicon layer (8) are sequentially formed on the entire upper surface, and the dielectric film (7) is an oxide film. An ONO structure formed in the order of a nitride film and an oxide film.

【００２０】図２Ｄは、コントロールゲート電極用マス
ク（図示されていない）を利用した写真及びエッチング
工程により、上記第２ポリシリコン層（８）、誘電体膜
（７）と上記第１及び第２フローティングゲート（３Ａ
及び３Ｂ）を順次にエッチングし、シリコン基板（１）
に不純物イオンを注入してソース及びドレーン（５及び
６）を形成することにより、上記第１及び第２フローテ
ィングゲート（３Ａ及び３Ｂ）上部に誘電体膜（７）及
びコントロールゲート（８Ａ）が積層されたＥＥＰＲＯ
Ｍセルを形成した状態の断面図である。FIG. 2D shows a photograph and an etching process using a control gate electrode mask (not shown), and the second polysilicon layer 8 and the dielectric film 7 and the first and second polysilicon layers 8. Floating gate (3A
And 3B) are sequentially etched to form a silicon substrate (1).
The source and drain (5 and 6) are formed by implanting impurity ions into the dielectric layer (7) and the control gate (8A) are stacked on the first and second floating gates (3A and 3B). EEPRO
It is sectional drawing of the state which formed the M cell.

【００２１】上記の如く、トンネリング（ｔｕｎｎｅｌ
ｉｎｇ）が可能になるように薄く形成されたトンネル酸
化膜（２）上に、２個のフローティングゲート（３Ａ及
び３Ｂ）が水平に隣接されるように形成し、この２個の
フローティングゲート）３Ａ乃至３Ｂ）各々の外側部と
充分に重なるように、シリコン基板（１）上にソース及
びドレーン（５及び６）を形成することにより、トンネ
リング時に必要な面積を効果的に確保して、短い有効チ
ャネルの長さ（ｅｆｆｅｃｔｉｖｅ ｃｈａｎｎｅｌ
ｌｅｎｇｔｈ）による読出の時、電流の流れが容易にな
る。As described above, tunneling (tunnel)
In this case, two floating gates (3A and 3B) are formed so as to be horizontally adjacent to each other on the tunnel oxide film (2) formed so as to be thin so that the floating gates 3A and 3A can be formed. 3B) By forming the source and drain (5 and 6) on the silicon substrate (1) so as to sufficiently overlap with the respective outer portions, the area required for tunneling can be effectively secured and the short effective area can be obtained. Channel length (effective channel)
When reading by length, the flow of current is facilitated.

【００２２】次に、かような技術的原理を利用して、４
進情報（”０”、”１”、”２”及び”３”）をプログ
ラム及び読出しするため、上記の如く製造したフラッシ
ュＥＥＰＲＯＭセルの動作を説明することにする。Next, utilizing such a technical principle, 4
The operation of a flash EEPROM cell manufactured as described above to program and read binary information ("0", "1", "2" and "3") will now be described.

【００２３】図３Ａ乃至図３Ｄは、本発明によるフラッ
シュＥＥＰＲＯＭセルのプログラム動作を説明するため
の動作状態図であり、図４Ａ乃至図４Ｄを参照して下記
の如く説明する。FIGS. 3A to 3D are operation state diagrams for explaining a program operation of a flash EEPROM cell according to the present invention, and will be described below with reference to FIGS. 4A to 4D.

【００２４】先ず、セルに”０”と言う情報をプログラ
ム即ち、すべてのフローティングゲートに電荷を貯蔵
（ｃｈａｒｇｅ）するためには、図３Ａの如く、コント
ロールゲート（８Ａ）に１２Ｖの高電圧を印加し、ドレ
ーン（６）に５Ｖ、ソース（５）には接地電位をそれぞ
れ印加する。上記コントロールゲート（８Ａ）に印加さ
れた高い電位により、第１及び第２フローティングゲー
ト（３Ａ及び３Ｂ）下部のシリコン基板（１）にはチャ
ネルが形成され、上記ドレーン（６）に印加された電圧
により、上記第１及び第２フローティングゲート（３Ａ
及び３Ｂ）間のシリコン基板（１）には高電界領域が形
成される。このとき、電流が上記の高電界領域を通過す
るとホットエレクトロン（ｈｏｔ ｅｌｅｃｔｒｏｎ；
９）が発生され、このホットエレクトロン（９）の一部
が上記コントロールゲート（８Ａ）に印加された高電位
により形成される垂直方向の電界により、上記第１及び
第２フローティングゲート（３Ａ及び３Ｂ）に注入（ｉ
ｎｊｅｃｔｉｏｎ）される。従って、このようなホット
エレクトロンの注入により上記ドレーン及びソース（６
及び５）側の限界電圧（ｔｈｒｅｓｈｏｌｄ ｖｏｌｔ
ａｇｅ）はそれぞれ、例を挙げると、６Ｖ程度に上昇す
るため図４Ａと同様に”０”という情報がプログラムさ
れた状態になる。First, a high voltage of 12 V is applied to the control gate (8A) as shown in FIG. 3A in order to program the information "0" in the cell, that is, to charge the floating gates. Then, 5 V is applied to the drain (6) and the ground potential is applied to the source (5). Due to the high potential applied to the control gate (8A), a channel is formed in the silicon substrate (1) below the first and second floating gates (3A and 3B), and a voltage applied to the drain (6). As a result, the first and second floating gates (3A
And 3B), a high electric field region is formed in the silicon substrate (1). At this time, when the current passes through the high electric field region, hot electrons (hot electrons;
9) is generated, and a part of the hot electrons (9) is generated by the vertical electric field formed by the high potential applied to the control gate (8A), and the first and second floating gates (3A and 3B) are generated. ) Is injected (i
njection). Therefore, the drain and source (6
And 5) side threshold voltage (threshold voltage)
Age), for example, rises to about 6 V, so that information "0" is programmed as in FIG. 4A.

【００２５】セルに”１”という情報をプログラムする
ためには、上記図４Ａの状態で図３Ｂと同様に、コント
ロールゲート（８Ａ）に接地電位、ドレーン（６）に１
２Ｖをそれぞれ印加し、ソース（５）をフロート（ｆｌ
ｏａｔ）させると、第２フローティングゲート（３Ｂ）
内に貯蔵されたエレクトロン（９）がトンネリングによ
り、上記ドレーン（６）を通じて放電（ｄｉｓｃｈａｒ
ｇｅ）されることにより、ドレーン（６）側の限界電圧
が、例えば、２Ｖ程度に低くなるので、図４Ｂの如く”
１”という情報がプログラムされた状態になる。In order to program the information "1" into the cell, the ground potential is applied to the control gate (8A) and 1 is applied to the drain (6) as in FIG. 3B in the state of FIG. 4A.
2V is applied, and the source (5) is floated (fl)
oat), the second floating gate (3B)
The electrons (9) stored in the discharge (dischar) through the drain (6) by tunneling.
g), the limit voltage on the drain (6) side is reduced to, for example, about 2 V, and as shown in FIG.
The information "1" is in a programmed state.

【００２６】セルに”２”という情報をプログラムする
ためには、上記図４Ａの状態で図３Ｃと同様に、コント
ロールゲート（８Ａ）に接地電位、ソース（５）に１２
Ｖをそれぞれ印加し、ドレーン（６）をフロートさせる
と、第１フローティングゲート（３Ａ）内に貯蔵された
エレクトロン（９）がトンネリングにより上記ソース
（５）を通じて放電されることにより、ソース（５）側
の限界電圧が、例えば、２Ｖ程度に低くなるので、図４
Ｃの如く”２”という情報がプログラムされた状態にな
る。In order to program the information "2" in the cell, the ground potential is applied to the control gate (8A) and 12 to the source (5) as in FIG. 3C in the state of FIG. 4A.
When V is applied and the drain (6) is floated, the electrons (9) stored in the first floating gate (3A) are discharged through the source (5) by tunneling, so that the source (5) is discharged. 4 becomes lower, for example, to about 2V.
The information "2" is programmed as shown in C.

【００２７】セルに”３”という情報をプログラムする
ためには、上記図４Ａの状態で図３Ｄと同様に、コント
ロールゲート（８Ａ）に接地電位を、ソース及びドレー
ン（５及び６）にそれぞれ１２Ｖを印加すると、第１及
び第２フローティングゲート（３Ａ及び３Ｂ）内に貯蔵
されたエレクトロン（９）がトンネリングにより上記ソ
ース及びドレーン（５及び６）を通じて放電されること
により、ソース及びドレーン側の限界電圧が、例えば、
２Ｖ程度に低くなるので、図４Ｄの如く”３”という情
報がプログラムされた状態になる。In order to program the information "3" into the cell, the ground potential is applied to the control gate (8A) and the source and drain (5 and 6) are each set to 12 V in the state of FIG. 4A, as in FIG. 3D. Is applied, the electrons (9) stored in the first and second floating gates (3A and 3B) are discharged through the source and drain (5 and 6) by tunneling, thereby limiting the source and drain side. If the voltage is, for example,
Since the voltage is reduced to about 2 V, the information "3" is programmed as shown in FIG. 4D.

【００２８】このように、コントロールゲート（８
Ａ）、ソース及びドレーン（５及び６）に印加するバイ
アス電圧（ｂｉａｓ ｖｏｌｔａｇｅ）の条件を変更し
て４進情報を一個のセルにプログラムすることが出来る
が、一つの情報をプログラムするときは２個のフローテ
ィングゲート相互の作用を防止するため、先ず情報”
０”をプログラムし、次に情報”１”、”２”又は”
３”をプログラムしなければならない。As described above, the control gate (8
A), quaternary information can be programmed into one cell by changing the condition of bias voltage (bias voltage) applied to the source and drain (5 and 6). In order to prevent interaction between floating gates,
0 ”and then the information“ 1 ”,“ 2 ”or“
3 "must be programmed.

【００２９】次に、上記の如くセルにプログラムされた
４進情報を判読するための読出（ｒｅａｄ）動作を、図
５Ａ及び図５Ｂを参照して説明する。Next, a read operation for reading the quaternary information programmed in the cell as described above will be described with reference to FIGS. 5A and 5B.

【００３０】上記の如く、４進情報が一つのセルにプロ
グラムされるので、これを読出するためには基本的に２
回の読出動作を、即ち、順方向読出（ｆｏｒｗａｒｄ
ｒｅａｄ）及び逆方向読出（ｒｅｖｅｒｓｅ ｒｅａ
ｄ）を、それぞれ実施することになる。ここでは、上記
図４Ｃと同様に情報”２”がプログラムされた状態での
読出動作を、例を挙げて、説明することにする。As described above, since the quaternary information is programmed in one cell, basically, two bits are required to read it.
Times of reading operation, that is, forward reading (forward)
read) and reverse read (reverse read)
d) will be performed respectively. Here, a read operation in a state where the information “2” is programmed in the same manner as in FIG. 4C will be described with an example.

【００３１】上記図４Ｃの如く、第２フローティングゲ
ート（３Ｂ）にだけエレクトロン（９）が貯蔵された状
態で、順方向読出を実施しようとする場合は、図５Ａの
如く、コントロールゲート（８Ａ）に４Ｖ、ドレーン
（６）に３Ｖ及びソース（５）には接地電位をそれぞれ
印加する。これにより、エレクトロン（９）が注入され
るソース（５）側の第１フローティングゲート（３Ａ）
下部のシリコン基板（１）上にチャネルが形成されるた
めドレーン電流（ＩD ）が存在する。As shown in FIG. 4C, when forward reading is to be performed in a state where electrons 9 are stored only in the second floating gate 3B, as shown in FIG. 5A, the control gate 8A is used. 4V, 3V to the drain (6) and the ground potential to the source (5), respectively. Thereby, the first floating gate (3A) on the side of the source (5) into which the electrons (9) are injected.
Since a channel is formed on the lower silicon substrate (1), a drain current ( ID ) exists.

【００３２】尚、上記図４Ｃと同様に、第２フローティ
ングゲート（３Ｂ）にだけエレクトロン（９）が貯蔵さ
れた状態で、逆方向読出を実施しようとする場合は、図
５Ｂの如くコントロールゲート（８Ａ）に４Ｖ、ソース
（５）に３Ｖ、及びドレーンにには接地電位をそれぞれ
印加する。これにより、エレクトロン（９）が注入され
るドレーン（６）側の第２フローティングゲート（３
Ｂ）下部のシリコン基板（１）にチャネルが形成されな
いためソース電流（ＩS ）は存在しなくなる。As in the case of FIG. 4C, when the backward reading is to be performed with the electrons (9) stored only in the second floating gate (3B), as shown in FIG. 4A is applied to 8A), 3V is applied to the source (5), and the ground potential is applied to the drain. As a result, the second floating gate (3) on the drain (6) side into which electrons (9) are injected.
B) Since no channel is formed in the lower silicon substrate (1), there is no source current (I S ).

【００３３】このような方法により、２回の読出動作を
実施した後、上記ドレーン及びソース電流（ＩD 及びＩ
S ）の有無に従い貯蔵された情報が読み出されるが、参
考に上記情報”０”、”１”、”２”及び”３”の読出
時のドレーン及びソース電流のフロー状態を下記の＜表
＞に表した。After performing the read operation twice by this method, the drain and source currents (I D and I
The stored information is read according to the presence or absence of S ). For reference, the flow states of the drain and source currents when reading the above information "0", "1", "2" and "3" are shown in the following table. It was expressed in.

【００３４】[0034]

【表１】 [Table 1]

【００３５】[0035]

【発明の効果】上述した如く、本発明によれば、チャネ
ル領域の上部に、２個のフローティングゲートを形成す
ることにより、この２個のフローティングゲートそれぞ
れのプログラム及び消去如何により、４進情報をプログ
ラムすることができ、且つ、正確に読出するのが可能な
ため大容量を持つフラッシュイイプロムセルを具現する
のに利用されることができる。更に、フローティングゲ
ートに情報が貯蔵されるため永久的に情報を貯蔵するこ
とができる卓越した効果がある。As described above, according to the present invention, by forming two floating gates on the channel region, the quaternary information can be written according to whether each of the two floating gates is programmed or erased. Since it can be programmed and can be read accurately, it can be used to implement a flash iprom cell having a large capacity. Further, since the information is stored in the floating gate, there is an excellent effect that the information can be stored permanently.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明によるフラッシュイイプロムセルの第１
実施例の製造方法を説明するための素子の断面図であ
る。FIG. 1 shows a first embodiment of a flash iprom cell according to the present invention.
It is sectional drawing of the element for demonstrating the manufacturing method of an Example.

【図２】本発明によるフラッシュイイプロムセルの第２
実施例の製造方法を説明するための素子の断面図であ
る。FIG. 2 shows a second embodiment of a flash iprom cell according to the invention.
It is sectional drawing of the element for demonstrating the manufacturing method of an Example.

【図３】本発明によるフラッシュイイプロムセルのプロ
グラム動作を説明するための動作状態図である。FIG. 3 is an operation state diagram for explaining a programming operation of the flash iprom cell according to the present invention.

【図４】図３を説明するための概念図である。FIG. 4 is a conceptual diagram for explaining FIG. 3;

【図５】本発明によるフラッシュイイプロムセルの読出
動作を説明するための動作状態図である。FIG. 5 is an operation state diagram for explaining a read operation of a flash iprom cell according to the present invention;

【符号の説明】[Explanation of symbols]

１ シリコン基板 ２ トンネ
ル酸化膜 ３ 第１ポリシリコン層 ３Ａ及び３Ｂ 第１及び第２フローティングゲート ４ 感光膜 ５及び６ ソー
ス及びドレーン ７ 誘電体膜 ８ 第２ポ
リシリコン層 ８Ａ コントロールゲート ９ ホット
エレクトロン1 Silicon Substrate 2 Tunnel Oxide Film 3 First Polysilicon Layer 3A and 3B First and Second Floating Gate 4 Photosensitive Film 5 and 6 Source and Drain 7 Dielectric Film 8 Second Polysilicon Layer 8A Control Gate 9 Hot Electron

Claims (18)

【特許請求の範囲】[Claims] 【請求項１】フラッシュＥＥＰＲＯＭセルにおいて、 互いに水平隣接し、トンネル酸化膜により下部のシリコ
ン基板と電気的に分離される第１及び第２フローティン
グゲートと、 上記第１及び第２フローティングゲートを含む上部面に
形成される誘電体膜と、 上記誘電体膜上部に形成され、上記誘電体膜により、上
記第１及び第２フローティングゲートと電気的に分離さ
れるコントロールゲートと、 上記シリコン基板に形成され、上記第１及び第２フロー
ティングゲート各々の外側部と一部重なるように形成さ
れるソース及びドレーンとからなることを特徴とするフ
ラッシュＥＥＰＲＯＭセル。1. In a flash EEPROM cell, first and second floating gates that are horizontally adjacent to each other and are electrically separated from a lower silicon substrate by a tunnel oxide film, and an upper portion including the first and second floating gates. A dielectric film formed on the surface, a control gate formed on the dielectric film and electrically separated from the first and second floating gates by the dielectric film, and formed on the silicon substrate. A flash EEPROM cell comprising a source and a drain formed so as to partially overlap the outer portions of the first and second floating gates. 【請求項２】第１項において、 上記誘電体膜は、酸化膜−窒化膜−酸化膜でなることを
特徴とするフラッシュＥＥＰＲＯＭセル。2. The flash EEPROM cell according to claim 1, wherein the dielectric film comprises an oxide film-a nitride film-an oxide film. 【請求項３】フラッシュＥＥＰＲＯＭセル製造方法にお
いて、 シリコン基板上に、トンネル酸化膜及び第１ポリシリコ
ン層を順次に形成する段階と、 上記段階から、上記第１ポリシリコン層をパターニング
して第１及び第２フローティングゲートを各々形成する
段階と、 上記段階から、上記第１及び第２フローティングゲート
間のシリコン基板を除外した全体領域に、不純物イオン
を注入してソース及びドレーンを形成する段階と、 上記段階から、上部面全体に、誘電体膜及び第２ポリシ
リコン層を順次に形成する段階と、 上記段階から、上記第２ポリシリコン層及び誘電体膜を
順次にパターニングしてコントロールゲートを形成する
段階とからなることを特徴とするフラッシュＥＥＰＲＯ
Ｍセルの製造方法。3. A method of manufacturing a flash EEPROM cell, comprising the steps of sequentially forming a tunnel oxide film and a first polysilicon layer on a silicon substrate, and from the step, patterning the first polysilicon layer to form a first polysilicon layer. And forming a second floating gate, and implanting impurity ions into the entire region excluding the silicon substrate between the first and second floating gates to form a source and a drain. From the above step, a dielectric film and a second polysilicon layer are sequentially formed on the entire upper surface, and from the above step, the second polysilicon layer and the dielectric film are sequentially patterned to form a control gate. Flash EEPRO, characterized in that
Manufacturing method of M cell. 【請求項４】第３項において、 上記トンネル酸化膜は、８０ないし１２０Åの厚さで形
成されることを特徴とするフラッシュＥＥＰＲＯＭセル
の製造方法。4. The method of manufacturing a flash EEPROM cell according to claim 3, wherein the tunnel oxide film is formed to a thickness of 80 to 120Å. 【請求項５】第３項において、 上記第１及び第２フローティングゲートは、水平に隣接
して形成されることを特徴とするフラッシュＥＥＰＲＯ
Ｍセルの製造方法。5. The flash EEPRO according to claim 3, wherein the first and second floating gates are horizontally adjacent to each other.
Manufacturing method of M cell. 【請求項６】第３項において、 上記誘電体膜は、酸化膜−窒化膜−酸化膜の順に形成さ
れることを特徴とするフラッシュＥＥＰＲＯＭセルの製
造方法。6. The method of manufacturing a flash EEPROM cell according to claim 3, wherein the dielectric film is formed in the order of oxide film-nitride film-oxide film. 【請求項７】フラッシュＥＥＰＲＯＭセルの製造方法に
おいて、 シリコン基板上に、トンネル酸化膜及び第１ポリシリコ
ン層を順次に形成する段階と、 第１フローティングゲートと第２フローティングゲート
間の上記第１ポリシリコン層をパターニングする段階
と、 上部面全体に、誘電体膜及び第２ポリシリコン層を順次
に形成する段階と、 コントロールゲート用マスクを利用し写真及びエッチン
グ工程で上記第２シリコン層、上記誘電体膜、及び上記
第１及び第２フローティングゲートを順次にパターニン
グする段階と、 シリコン基板に、不純物イオンを注入してソース及びド
レーンを形成する段階とからなることを特徴とするフラ
ッシュＥＥＰＲＯＭセルの製造方法。7. A method of manufacturing a flash EEPROM cell, wherein a tunnel oxide film and a first polysilicon layer are sequentially formed on a silicon substrate, and the first polysilicon between the first floating gate and the second floating gate is formed. Patterning a silicon layer, sequentially forming a dielectric film and a second polysilicon layer on the entire upper surface, and using a mask for a control gate to photograph and etch the second silicon layer and the dielectric layer. Manufacturing a flash EEPROM cell, which comprises sequentially patterning a body film and the first and second floating gates, and implanting impurity ions into a silicon substrate to form a source and a drain. Method. 【請求項８】第７項において、 上記トンネル酸化膜は、８０乃至１２０Åの厚さで形成
されることを特徴とするフラッシュＥＥＰＲＯＭセルの
製造方法。8. The method of manufacturing a flash EEPROM cell according to claim 7, wherein the tunnel oxide film is formed to a thickness of 80 to 120Å. 【請求項９】第７項において、 上記第１及び第２フローティングゲートは、水平に隣接
して形成されることを特徴とするフラッシュＥＥＰＲＯ
Ｍセルの製造方法。9. The flash EEPRO according to claim 7, wherein the first and second floating gates are horizontally adjacent to each other.
Manufacturing method of M cell. 【請求項１０】第７項において、 上記誘電体膜は、酸化膜−窒化膜−酸化膜の順に形成さ
れることを特徴とするフラッシュＥＥＰＲＯＭセルの製
造方法。10. The method of manufacturing a flash EEPROM cell according to claim 7, wherein the dielectric film is formed in the order of oxide film-nitride film-oxide film. 【請求項１１】第１及び第２フローティングゲートにホ
ットエレクトロンが注入されるようにコントロールゲー
ト、ソース及びドレーンにバイアス電圧を印加した後、
上記コントロールゲート、ソース及びドレーンに印加さ
れるバイアス電圧の条件に従い、上記第１及び第２フロ
ーティングゲートに注入されたホットエレクトロンを選
択的に消去して、４進情報がプログラムされるようにす
ることを特徴とするフラッシュＥＥＰＲＯＭセルのプロ
グラム方法。11. A bias voltage is applied to a control gate, a source and a drain so that hot electrons are injected into the first and second floating gates,
Selectively erasing hot electrons injected into the first and second floating gates to program quaternary information according to a condition of a bias voltage applied to the control gate, the source and the drain. And a method for programming a flash EEPROM cell. 【請求項１２】第１１項において、 上記第１及び第２フローティングゲートにホットエレク
トロンを注入させるため、上記コントロールゲートに印
加する電圧は、ドレーンに印加される電圧より高くし、
ソースには接地電位が印加されるようにしたことを特徴
とするフラッシュＥＥＰＲＯＭセルのプログラム方法。12. The voltage applied to the control gate is set higher than the voltage applied to the drain in order to inject hot electrons into the first and second floating gates.
A method for programming a flash EEPROM cell, wherein a ground potential is applied to the source. 【請求項１３】第１１項において、 上記第２フローティングゲートに注入されたホットエレ
クトロンを放電させるため、上記コントロールゲートを
接地電位になるようにし、ソースはフロートさせる一
方、ドレーンには、上記コントロールゲートに印加され
る電圧より高い電圧が印加されるようにしたことを特徴
とするフラッシュＥＥＰＲＯＭセルのプログラム方法。13. The hot gate according to claim 11, wherein the control gate is set to a ground potential and the source is floated while the hot electrons injected into the second floating gate are discharged, while the drain is the control gate. A method for programming a flash EEPROM cell, characterized in that a voltage higher than that applied to the flash EEPROM cell is applied. 【請求項１４】第１１項において、 上記第１フローティングゲートに注入されたホットエテ
クトロンを放電させるため、上記コントロールゲートは
接地電位になるようにし、ドレーンをフロートさせる一
方、ソースには上記コントロールゲートに印加される電
圧より高い電圧が印加されるようにしたことを特徴とす
るフラッシュＥＥＰＲＯＭセルのプログラム方法。14. The discharge control device according to claim 11, wherein the control gate is set to the ground potential to discharge the hot ectron injected into the first floating gate, and the drain is floated while the source is the control gate. A method for programming a flash EEPROM cell, characterized in that a voltage higher than that applied to the flash EEPROM cell is applied. 【請求項１５】第１１項において、 上記第１及び第２フローティングゲートに注入されたホ
ットエレクトロンを放電させるため、上記コントロール
ゲートが接地電位になるようにし、ソース及びドレーン
には、上記コントロールゲートに印加される電圧より高
いが、同一の大きさの電圧が印加されるようにしたこと
を特徴とするフッラッシュＥＥＰＲＯＭセルのプログラ
ム方法。15. The discharge control method according to claim 11, wherein the control gate is set to a ground potential to discharge the hot electrons injected into the first and second floating gates, and the source and drain are connected to the control gate. A method for programming a flash EEPROM cell, characterized in that a voltage having a higher magnitude than the applied voltage is applied. 【請求項１６】第１及び第２フローティングゲートに、
選択的に注入されたホットエレクトロンにより、プログ
ラムされた４進情報を読出するため、順方向読出及び逆
方向読出を各々実施した後、ドレーン及びソース電流の
有無に従い、貯蔵された情報が読出されるようにしたこ
とを特徴とするフラッシュＥＥＰＲＯＭセルの読出方
法。16. The first and second floating gates,
Since the programmed quaternary information is read by the selectively injected hot electrons, the stored information is read according to the presence / absence of drain and source currents after performing forward read and reverse read, respectively. A method of reading a flash EEPROM cell, characterized in that. 【請求項１７】第１６項において、 上記、順方向読出の際、ソースが接地電位になるように
し、コントロールゲートには、ドレーンに印加される電
圧より高い電圧が印加されるようにしたことを特徴とす
るフラッシュＥＥＰＲＯＭセルの読出方法。17. The method according to claim 16, wherein the source is set to a ground potential and a voltage higher than a voltage applied to the drain is applied to the control gate during the forward reading. A method of reading a characteristic flash EEPROM cell. 【請求項１８】第１６項において、 上記、逆方向読出の際、ドレーンが接地電位になるよう
にし、コントロールゲートにはソースに印加される電圧
より高い電圧が印加されるようにしたことを特徴とする
フラッシュＥＥＰＲＯＭセルの読出方法。18. The method according to claim 16, wherein the drain is set to the ground potential and the control gate is applied with a voltage higher than the voltage applied to the source during the reverse reading. And a method for reading a flash EEPROM cell.
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