CN103426885A - Non-self-alignment and fixed hydrocarbon storage structure - Google Patents
Non-self-alignment and fixed hydrocarbon storage structure Download PDFInfo
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- CN103426885A CN103426885A CN2012101611643A CN201210161164A CN103426885A CN 103426885 A CN103426885 A CN 103426885A CN 2012101611643 A CN2012101611643 A CN 2012101611643A CN 201210161164 A CN201210161164 A CN 201210161164A CN 103426885 A CN103426885 A CN 103426885A
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Abstract
The invention provides a non-self-alignment and fixed hydrocarbon storage structure. The non-self-alignment and fixed hydrocarbon storage structure mainly comprises a semiconductor substrate, a left floating grid storage unit cell, a right floating grid storage unit cell, a control grid and a grid insulating layer which is located between the two floating grid storage unit cells and the control grid. The drain electrode of the left floating grid storage unit cell and the drain electrode of the right floating grid storage unit cell are connected to different voltage quasi stations respectively. The control grid is located on the two floating grid storage unit cells and covers floating grids of the two floating grid storage unit cells to control the two floating grids at the same time. The demand for aligning grid lines does not need to be met according to the fixed hydrocarbon storage structure, and accordingly the complexity of the technology, the number of layers of needed photomasks and manufacturing cost are reduced.
Description
Technical field
The invention relates to a kind of structure of memory, particularly the non-volatile memory structure of the non-self-aligned of a kind of low cost.
Background technology
Along with the progress of electronics and information industry, the various electronic products that are applied to daily life are constantly weeded out the old and bring forth the new, and in these electronic products, are provided with memory for storage data.Nowadays, the memory the most often adopted is non-volatility memorizer (Non-volatile memory, NVM), and for example: flash memory, it is for being used in a large number the non-volatility memorizer in the electronic products such as mobile phone or digital camera.
Specifically, complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) manufacture method commonly used that technology is Application Specific Integrated Circuit (application specific integrated circuit, ASIC).In today of computerized information product prosperity, but electronic type clear program read-only memory (Electrically Erasable Programmable Read Only Memory, EEPROM) owing to possessing to have, electrically write and the non-volatility memorizer function of the data of erasing, and data can not lost after power supply is turned off, so be widely used on electronic product.
Generally speaking, non-volatility memorizer is programmable, and it is to store electric charge to change the transistorized grid voltage of memory, or does not store electric charge to stay the transistorized grid voltage of former memory.Erase operation for use is that all electric charges that are stored in non-volatility memorizer are removed, and makes all non-volatility memorizers get back to the transistorized grid voltage of former memory.
The non-volatility memorizer that prior art proposes has two kinds of different silicon material structures, and the one, silicon oxide nitride oxide silicon (SONOS) structure, floating grid (Floating Gate) structure that is current main flow.Research according to each flash memory factory of family, floating grid has its technical restriction, as: NOR wafer need be below 45 nanometers, the NAND wafer need be below 32 nanometers, and the grid of non-volatility memorizer is two wide control grids (Control gate) and floating grid (Floating gate) usually.Therefore, non-volatility memorizer, when the thermal process through follow-up, needs to use extra San Zhi tetra-road light shields more, to meet the specification demands of grid Line To Line (line to line), in this, will significantly increase operation, complexity and the cost of manufacture of technique.
In view of this, the present invention, then for the disappearance of above-mentioned prior art, proposes the non-volatile memory structure of the non-self-aligned of a kind of low cost, effectively to overcome these above-mentioned problems.
Summary of the invention
Main purpose of the present invention is that a kind of non-volatile memory structure of non-self-aligned is being provided, its be by one the control lock above floating grid contain two memory cells, to control the floating grid of two non-self-aligneds simultaneously.
Another object of the present invention is that a kind of non-volatile memory structure of non-self-aligned is being provided, it is the structure that contains two memory cells of the control lock above floating grid by, and form the gate stack structure need not control the non-self-aligned that grid aims at the grid Line To Line of floating grid, solve existing non-volatile memory structure and must accomplish the problem that grid Line To Line (line to line) is aimed at, significantly reduce thus the complexity of technique and the light shield number of plies of the required use of technique, and then reduce production costs.
In order to achieve the above object, the invention provides a kind of non-volatile memory structure of non-self-aligned, it consists predominantly of semiconductor substrate, a left floating gate memory structure cell and a right floating gate memory structure cell, one and controls grid, and a gate insulator.
Left floating gate memory structure cell and right floating gate memory structure cell are to be formed on semiconductor base, and the drain electrode of two floating gate memories is received respectively different voltage quasi positions, the purpose of using to reach independence.
Controlling grid is to be positioned on the two floating gate memory structure cells of left and right, and controls the floating grid that grid is contained two floating gate memory structure cells, to control two floating grids simultaneously.
Gate insulator is at left floating gate memory structure cell, right floating gate memory structure cell and controls between grid.
During enforcement, the border, left and right of part that this control grid is non-is positioned at the floating grid top of the floating grid of this left floating gate memory structure cell and this right floating gate memory structure cell is the outer boundaries that respectively is more than or equal to the floating grid of the floating grid of this left floating gate memory structure cell and this right floating gate memory structure cell.
During enforcement, the material of this gate insulator is the tetraethoxysilane oxide layer.
During enforcement, the material of this control grid is polysilicon.
During enforcement, more comprise the Yi Jingxing district in this semiconductor substrate, and this left floating gate memory structure cell and this right floating gate memory structure cell are to be positioned at the Gai Jingxing district.
During enforcement, this left floating gate memory structure cell and this right floating gate memory structure cell respectively include:
One floating grid insulating barrier, it is to be positioned on this semiconductor substrate;
One floating grid, it is to be positioned on this floating grid insulating barrier; And
One the drain electrode and one source pole, it is to be arranged in this semiconductor substrate, and lays respectively at two sides of this floating grid insulating barrier, and with this floating grid insulating barrier adjacency.
During enforcement, the source electrode of this right floating gate memory structure cell and this left floating gate memory structure cell shares.
Under by specific embodiment, illustrate in detail, when the effect that is easier to understand purpose of the present invention, technology contents, characteristics and reaches.
The accompanying drawing explanation
The cutaway view of one embodiment of the non-volatile memory structure that Fig. 1 is non-self-aligned of the present invention;
The vertical view that Fig. 2 is Fig. 1;
Fig. 3 is the cutaway view of another embodiment of the non-volatile memory structure of non-self-aligned of the present invention;
Fig. 4 is the cutaway view of another embodiment of the non-volatile memory structure of non-self-aligned of the present invention;
Fig. 5 is the cutaway view of another embodiment of the non-volatile memory structure of non-self-aligned of the present invention;
Fig. 6 is the vertical view of another embodiment of the non-volatile memory structure of non-self-aligned of the present invention.
Description of reference numerals: the non-volatility memorizer of the non-self-aligned of 10-; 12,12 '-semiconductor base; The left floating gate memory structure cell of 14-; The right floating gate memory structure cell of 16-; 18-controls grid; The 20-gate insulator; 22,22 '-drain electrode; 24,24 '-drain electrode; The 26-floating grid; The 28-floating grid; The left floating grid insulating barrier of 30-; The 32-source electrode; The right floating grid insulating barrier of 34-; 36,36 '-Jing Xingqu; 38-controls grid.
Embodiment
Please in the lump with reference to figure 1 and Fig. 2, it is respectively cutaway view and the vertical view of an embodiment of the non-volatile memory structure of non-self-aligned of the present invention.
As shown in the figure, the non-volatility memorizer 10 of non-self-aligned of the present invention consists predominantly of: the left floating gate memory structure cell 14 of semiconductor substrate 12, one and a right floating gate memory structure cell 16, are controlled grid 18, and a gate insulator 20.
Left floating gate memory structure cell 14 is to be formed on semiconductor base 12 with right floating gate memory structure cell 16, and the drain electrode 22 of left floating gate memory structure cell 14 is received respectively different voltage quasi positions from the drain electrode 24 of right floating gate memory structure cell 16, to reach the independent purpose of using.
Controlling grid 18 is to be positioned on left floating gate memory structure cell 14 and right floating gate memory structure cell 16, and control grid 18 and contain the floating grid 26 of left floating gate memory structure cell 14 and the floating grid 28 of right floating gate memory structure cell 16, the floating grid 28 with the floating grid 26 of controlling left floating gate memory structure cell 14 simultaneously with right floating gate memory structure cell 16.
The material of above-mentioned control grid 18 can be polysilicon, and the material of gate insulator 20 can be tetraethoxysilane oxide layer (tetraethyl-ortho-silicate, TEOS).
Left floating gate memory structure cell 14 can include a floating grid insulating barrier 30 be positioned on semiconductor substrate 12; One is positioned at the floating grid 26 on floating grid insulating barrier 30; And one the drain electrode 22 with one source pole 32.Drain electrode 22 is to be arranged in semiconductor substrate 12 with source electrode 32, and lays respectively at two sides of floating grid insulating barrier 30, and with floating grid insulating barrier 30 adjacency.
Right floating gate memory structure cell 16 can include a floating grid insulating barrier 34 be positioned on semiconductor substrate 12 equally; One is positioned at the floating grid 28 on floating grid insulating barrier 34; And one the drain electrode 24 with one source pole 32.Drain electrode 24 is to be arranged in semiconductor substrate 12 with source electrode 32, and lays respectively at two sides of floating grid insulating barrier 34, and with floating grid insulating barrier 34 adjacency.
Moreover as shown in the figure, left floating gate memory structure cell 14 of the present invention shares with the source electrode 32 of right floating gate memory structure cell 16.
In addition, source electrode is contrary with the conductivity of drain electrode and the conductivity of semiconductor substrate, and for instance, as shown in Figure 1, when semiconductor substrate 12 is P type semiconductor substrate (P-substrate), source electrode 32 is the N-type doping with drain electrode 22,24.Perhaps as shown in Figure 3, when semiconductor substrate 12 ' is N type semiconductor substrate (N-substrate), source electrode 32 ' is the doping of P type with drain electrode 22 ', 24 '.Because Fig. 3 only has source electrode, drain electrode contrary with the conductivity of semiconductor substrate compared to Fig. 1, therefore other structure division system is no longer repeated.
Left floating grid insulating barrier 30 can be silicon dioxide (SiO with the material of right floating grid insulating barrier 34
2).Moreover the more left floating grid insulating barrier 30 of thickness system of gate insulator 20 comes slightly thickly with the thickness of right floating grid insulating barrier 34.
Refer to Fig. 4, it is the cutaway view of another embodiment of the non-volatile memory structure of non-self-aligned of the present invention.As shown in the figure, more comprise Yi Jingxing district 36 in semiconductor substrate 12, and left floating gate memory structure cell 14 is to be positioned at Jing Xing district 36 with right floating gate memory structure cell 16.
Source electrode is contrary with the conductivity in the conductivity Yu Jingxing district of drain electrode.For instance, when ，Jing Xing district 36 is the P type as shown in Figure 4, source electrode 32 is the N-type doping with drain electrode 22,24.When perhaps ，Jing Xing district 36 is N-type as shown in Figure 5, source electrode 32 is the doping of P type with drain electrode 22,24.Because Fig. 5 only has the conductivity in source electrode, drain electrode Yu Jingxing district contrary compared to the 4th figure, therefore other structure division system is no longer repeated.
Refer to Fig. 6, the vertical view of another embodiment of its non-volatile memory structure that is non-self-aligned of the present invention.It is rectangles that the difference of this embodiment and Fig. 2 is in the control grid 18 overall appearance profiles of Fig. 2, and the control grid 38 overall appearance profiles of Fig. 6 are zigzags.That is to say that the non-floating grid 26 that is positioned at left floating gate memory structure cell 14 of the control grid 38 of Fig. 6 is the outer boundaries that respectively are greater than or equal to floating grid 26 with the floating grid 28 of right floating gate memory structure cell 16 of left floating gate memory structure cell 14 with the border, left and right of the part of floating grid 28 tops of right floating gate memory structure cell 16, and present outside outstanding.
In sum, the non-volatile memory structure of disclosed non-self-aligned be utilize one and the control lock of position above floating grid contain two floating gate memory structure cells, control the floating grid of two non-self-aligneds simultaneously, wherein the drain voltage of left and right floating gate memory structure cell is received respectively different voltage quasi positions, reaches thus the independent purpose of using.The present invention forms non-self-aligned (non-self aligned) structure by control grid and the floating grid that makes non-volatility memorizer, must accomplish by solving existing non-volatile memory structure the problem that grid Line To Line (line to line) is aimed at, significantly reduce thus the complexity of technique and the light shield number of plies of the required use of technique, and then reduce the production cost of non-volatile memory structure.
As described above, be only preferred embodiment of the present invention, not is used for limiting scope of the invention process.Therefore be that all equalizations of doing according to the described feature of the present patent application scope and spirit change or modify, all should be included in claim of the present invention.
Claims (7)
1. the non-volatile memory structure of a non-self-aligned, is characterized in that, it includes:
The semiconductor substrate;
One left floating gate memory structure cell and a right floating gate memory structure cell, it is formed on this semiconductor base, and the drain electrode of this left floating gate memory structure cell is received respectively different voltage quasi positions from the drain electrode of this right floating gate memory structure cell;
One controls grid, it is positioned on this left floating gate memory structure cell and this right floating gate memory structure cell, and this control grid is contained the floating grid of this left floating gate memory structure cell and the floating grid of this right floating gate memory structure cell, with the floating grid of controlling this left floating gate memory structure cell and the floating grid of this right floating gate memory structure cell simultaneously; And
One gate insulator, it is between this left floating gate memory structure cell, this right floating gate memory structure cell and this control grid.
2. the non-volatile memory structure of non-self-aligned according to claim 1, it is characterized in that, the border, left and right of part that this control grid is non-is positioned at the floating grid top of the floating grid of this left floating gate memory structure cell and this right floating gate memory structure cell is the outer boundaries that respectively is more than or equal to the floating grid of the floating grid of this left floating gate memory structure cell and this right floating gate memory structure cell.
3. the non-volatile memory structure of non-self-aligned according to claim 1, is characterized in that, the material of this gate insulator is the tetraethoxysilane oxide layer.
4. the non-volatile memory structure of non-self-aligned according to claim 1, is characterized in that, the material of this control grid is polysilicon.
5. the non-volatile memory structure of non-self-aligned according to claim 1, is characterized in that, more comprises the Yi Jingxing district in this semiconductor substrate, and this left floating gate memory structure cell and this right floating gate memory structure cell are to be positioned at the Gai Jingxing district.
6. the non-volatile memory structure of non-self-aligned according to claim 1, is characterized in that, this left floating gate memory structure cell and this right floating gate memory structure cell respectively include:
One floating grid insulating barrier, it is to be positioned on this semiconductor substrate;
One floating grid, it is to be positioned on this floating grid insulating barrier; And
One the drain electrode and one source pole, it is to be arranged in this semiconductor substrate, and lays respectively at two sides of this floating grid insulating barrier, and with this floating grid insulating barrier adjacency.
7. according to the non-volatile memory structure of claim 1 or 6 described non-self-aligned, it is characterized in that, the source electrode of this right floating gate memory structure cell and this left floating gate memory structure cell shares.
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| CN2012101611643A CN103426885A (en) | 2012-05-22 | 2012-05-22 | Non-self-alignment and fixed hydrocarbon storage structure |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1159059A (en) * | 1995-05-16 | 1997-09-10 | 现代电子产业株式会社 | Flash EEPROM cell, method of manufacturing the same, method of programming and method of reading the same |
| CN1607669A (en) * | 2003-08-07 | 2005-04-20 | 三星电子株式会社 | Nonvolatile semiconductor memory device having double floating gate structure and method of manufacturing the same |
| US20070253257A1 (en) * | 2006-04-26 | 2007-11-01 | Chih-Hsin Wang | Electrically alterable non-volatile memory cells and arrays |
| US20080084750A1 (en) * | 2004-12-08 | 2008-04-10 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and a method of word lines thereof |
| US8004032B1 (en) * | 2006-05-19 | 2011-08-23 | National Semiconductor Corporation | System and method for providing low voltage high density multi-bit storage flash memory |
-
2012
- 2012-05-22 CN CN2012101611643A patent/CN103426885A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1159059A (en) * | 1995-05-16 | 1997-09-10 | 现代电子产业株式会社 | Flash EEPROM cell, method of manufacturing the same, method of programming and method of reading the same |
| CN1607669A (en) * | 2003-08-07 | 2005-04-20 | 三星电子株式会社 | Nonvolatile semiconductor memory device having double floating gate structure and method of manufacturing the same |
| US20080084750A1 (en) * | 2004-12-08 | 2008-04-10 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and a method of word lines thereof |
| US20070253257A1 (en) * | 2006-04-26 | 2007-11-01 | Chih-Hsin Wang | Electrically alterable non-volatile memory cells and arrays |
| US8004032B1 (en) * | 2006-05-19 | 2011-08-23 | National Semiconductor Corporation | System and method for providing low voltage high density multi-bit storage flash memory |
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Application publication date: 20131204 |