TW201349393A - Non-self-aligned, non-volatile memory structure - Google Patents

Abstract

The present invention provides a non-self-aligned, non-volatile memory structure, which mainly comprises a semiconductor base, a left floating gate memory unit cell and a right floating gate memory unit cell, a control gate, and a gate insulation layer located in-between the two memory unit cells and the control gate. The drains of the two floating gate memory unit cells are separately connected to different voltage levels. The control gate is located on two floating gate memory unit cells and covers the floating gates of the two floating gate memory unit cells, so as to synchronously control the two floating gates. The non-volatile memory structure of the present invention does not require alignment from the gate line, so as to reduce the complexity of the manufacturing process, the number of the photo-mask layer necessarily used, and manufacturing cost.

Description

Non-self-aligned non-volatile memory structure

The present invention relates to the structure of a memory, and more particularly to a low cost non-self-aligned non-volatile memory structure.

With the advancement of the electronic information industry, various electronic products used in daily life are constantly being introduced, and memories are stored in these electronic products for storing materials. Today, the most commonly used memory system is non-volatile memory (NVM), such as flash memory, which is a non-volatile memory used in a large number of electronic products such as mobile phones or digital cameras. .

In detail, Complementary Metal Oxide Semiconductor (CMOS) process technology is a common manufacturing method for application specific integrated circuits (ASICs). In today's computer information products, Electronically Erasable Programmable Read Only Memory (EEPROM) has a non-volatile memory function that electrically writes and erases data, and is powered off. After the data is lost, it is widely used in electronic products.

In general, a non-volatile memory system is programmable, which is used to store charge to change the gate voltage of the transistor of the memory, or to store the gate voltage of the transistor of the original memory without storing the charge. . The erase operation removes all of the charge stored in the non-volatile memory, causing all of the non-volatile memory to return to the gate voltage of the transistor of the original memory.

The non-volatile memory proposed by the prior art has two different germanium material structures, one is a neodymium oxynitride (SONOS) structure, and the other is a current floating gate structure. According to the research of various flash memory factories, the floating gate has its technical limitations, such as: NOR The wafer needs to be below 45 nm, the NAND wafer needs to be below 32 nm, and the gate of the non-volatile memory is usually two equal width control gates and floating gates. . Therefore, non-volatile memory needs to use an additional three to four masks in the subsequent thermal process to meet the line to line specification requirements, which will greatly increase the process. Process, complexity and production costs.

In view of the above, the present invention proposes a low-cost non-self-aligned non-volatile memory structure in response to the above-mentioned shortcomings of the prior art to effectively overcome the above problems.

The main object of the present invention is to provide a non-self-aligned non-volatile memory structure that covers two memory cells by a control gate above the floating gate to simultaneously control two non-self-self Align the floating gate.

Another object of the present invention is to provide a non-self-aligned non-volatile memory structure that is formed by a structure that covers two memory cells by a control gate above the floating gate. Non-self-aligned gate stack structure with gate-to-line gate alignment of the gate and floating gate, to solve the conventional non-volatile memory structure, it is necessary to achieve gate to line alignment The problem is to greatly reduce the complexity of the process and the number of reticle layers required for the process, thereby reducing production costs.

To achieve the above object, the present invention provides a non-self-aligned non-volatile memory structure, which mainly comprises a semiconductor substrate, a left floating gate memory cell and a right floating gate memory cell, Control the gate and a gate insulation.

The left floating gate memory cell and the right floating gate memory cell are formed on the semiconductor substrate, and the drains of the two floating gate memories are respectively connected to different voltage levels for independent use. the goal of.

The control gate is located on the left and right floating gate memory cells, and the control gate covers the floating gates of the two floating gate memory cells to simultaneously control the two floating gates.

The gate insulating layer is located between the left floating gate memory cell, the right floating gate memory cell and the control gate.

The purpose, technical content, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments.

Please refer to FIG. 1 and FIG. 2 together, which are cross-sectional and plan views of one embodiment of the non-self-aligned non-volatile memory structure of the present invention.

As shown, the non-self-aligned non-volatile memory 10 of the present invention mainly comprises: a semiconductor substrate 12, a left floating gate memory cell 14 and a right floating gate memory cell 16, A control gate 18 and a gate insulating layer 20.

The left floating gate memory cell 14 and the right floating gate memory cell 16 are formed on the semiconductor substrate 12, and the left floating gate memory cell 14 has a drain 22 and a right floating gate memory cell. The 16 poles of the 16 are respectively connected to different voltage levels for the purpose of independent use.

The control gate 18 is located on the left floating gate memory cell 14 and the right floating gate memory cell 16, and the control gate 18 covers the floating gate 26 and the right floating of the left floating gate memory cell 14. The floating gate 28 of the gate memory cell 16 simultaneously controls the floating gate 26 of the left floating gate memory cell 14 and the floating gate 28 of the right floating gate memory cell 16.

The gate insulating layer 20 is located between the left floating gate memory cell 14, the right floating gate memory cell 16 and the control gate 18 for insulation.

The material of the control gate 18 may be polysilicon, and the material of the gate insulating layer 20 may be tetraethyl-ortho-silicate (TEOS).

The left floating gate memory cell 14 may include a floating gate insulating layer 30 on the semiconductor substrate 12; a floating gate 26 on the floating gate insulating layer 30; and a drain 22 and a source 32. . The drain 22 and the source 32 are located in the semiconductor substrate 12 and are respectively located on two sides of the floating gate insulating layer 30 and are adjacent to the floating gate insulating layer 30.

The right floating gate memory cell 16 can also include a floating gate insulating layer 34 on the semiconductor substrate 12; a floating gate 28 on the floating gate insulating layer 34; and a drain 24 and a source 32. The drain 24 and the source 32 are located in the semiconductor substrate 12 and are respectively located on two sides of the floating gate insulating layer 34 and are adjacent to the floating gate insulating layer 34.

Furthermore, as shown, the left floating gate memory cell 14 of the present invention is shared with the source 32 of the right floating gate memory cell 16.

Further, the conductivity type of the source and the drain is opposite to the conductivity type of the semiconductor substrate. For example, as shown in FIG. 1, when the semiconductor substrate 12 is a P-type semiconductor substrate (P-substrate), the source 32 and the drain 22, 24 are N-type doped. Alternatively, as shown in Fig. 3, when the semiconductor substrate 12' is an N-type semiconductor substrate (N-substrate), the source 32' and the drain electrodes 22' and 24' are P-type doped. Since FIG. 3 has only the source and drain electrodes opposite to the conductivity type of the semiconductor substrate in FIG. 1, the other structural portions will not be described again.

The material of the left floating gate insulating layer 30 and the right floating gate insulating layer 34 may be cerium oxide (SiO ₂ ). Moreover, the thickness of the gate insulating layer 20 is slightly thicker than the thickness of the left floating gate insulating layer 30 and the right floating gate insulating layer 34.

Please refer to FIG. 4, which is another non-self-aligned non-volatile memory structure of the present invention. A cross-sectional view of an embodiment. As shown, the semiconductor substrate 12 further includes a well pattern region 36, and the left floating gate memory cell 14 and the right floating gate memory cell 16 are located within the well region 36.

The conductivity pattern of the source and the drain is opposite to the conductivity of the well region. For example, as shown in FIG. 4, when the well region 36 is a P-type, the source 32 and the drains 22, 24 are N-type doped. Alternatively, as shown in Fig. 5, when the well region 36 is of the N-type, the source 32 and the drains 22, 24 are P-type doped. Since Fig. 5 has only the opposite conductivity types of the source, drain and well regions compared to Fig. 4, the other structural portions will not be described again.

Please refer to FIG. 6, which is a top plan view of another embodiment of the non-self-aligned non-volatile memory structure of the present invention. The difference between this embodiment and FIG. 2 is that the overall outline of the control gate 18 of FIG. 2 is a rectangle, and the overall outline of the control gate 38 of FIG. 6 is a sawtooth shape. That is to say, the control gate 38 of FIG. 6 is not located at the left and right boundaries of the floating gate 26 of the left floating gate memory cell 14 and the floating gate 28 of the right floating gate memory cell 16 Greater than or equal to the outer boundary of the floating gate 26 of the left floating gate memory cell 14 and the floating gate 28 of the right floating gate memory cell 16, exhibiting an outward protrusion.

In summary, the non-self-aligned non-volatile memory structure disclosed by the present invention covers two floating gate memory cells by using a control gate above the floating gate, and simultaneously controls two Non-self-aligned floating gates, in which the drain voltages of the left and right floating gate memory cells are respectively connected to different voltage levels, thereby achieving the purpose of independent use. The present invention forms a non-self aligned structure by making the control gate of the non-volatile memory and the floating gate, and the gate pair must be solved by solving the conventional non-volatile memory structure. The problem of line to line alignment, thereby greatly reducing the complexity of the process and the number of mask layers required for the process, thereby reducing the production cost of the non-volatile memory structure.

The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention. Therefore, any changes or modifications of the features and spirits of the present invention should be included in the scope of the present invention.

10‧‧‧ Non-self-aligned non-volatile memory

12, 12'‧‧‧ Semiconductor substrate

14‧‧‧ Left floating gate memory cell

16‧‧‧Right floating gate memory cell

18‧‧‧Control gate

20‧‧‧ gate insulation

22, 22’‧‧‧汲

24, 24’‧‧‧汲

26‧‧‧Floating gate

28‧‧‧Floating gate

30‧‧‧Left floating gate insulation

32‧‧‧ source

34‧‧‧Right floating gate insulation

36, 36’‧‧‧ Well pattern area

38‧‧‧Control gate

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing one embodiment of a non-self-aligned non-volatile memory structure of the present invention.

Fig. 2 is a plan view of Fig. 1.

Figure 3 is a cross-sectional view of another embodiment of a non-self-aligned non-volatile memory structure of the present invention.

Figure 4 is a cross-sectional view of another embodiment of a non-self-aligned non-volatile memory structure of the present invention.

Figure 5 is a cross-sectional view of another embodiment of a non-self-aligned non-volatile memory structure of the present invention.

Figure 6 is a top plan view of another embodiment of a non-self-aligned non-volatile memory structure of the present invention.

10‧‧‧ Non-self-aligned non-volatile memory

12‧‧‧Semiconductor substrate

14‧‧‧ Left floating gate memory cell

16‧‧‧Right floating gate memory cell

18‧‧‧Control gate

20‧‧‧ gate insulation

22‧‧‧汲polar

24‧‧‧汲polar

26‧‧‧Floating gate

28‧‧‧Floating gate

30‧‧‧Left floating gate insulation

32‧‧‧ source

34‧‧‧Right floating gate insulation

Claims (7)

A non-self-aligned non-volatile memory structure comprising: a semiconductor substrate; a left floating gate memory cell and a right floating gate memory cell formed on the semiconductor substrate, The drain of the left floating gate memory cell and the drain of the right floating gate memory cell are respectively connected to different voltage levels; a control gate is located at the left floating gate memory cell and the gate a right floating gate memory cell, and the control gate covers a floating gate of the left floating gate memory cell and a floating gate of the right floating gate memory cell to simultaneously control the left floating a floating gate of the gate memory cell and a floating gate of the right floating gate memory cell; and a gate insulating layer located in the left floating gate memory cell, the right floating gate Between the memory cell and the control gate. The non-self-aligned non-volatile memory structure according to claim 1, wherein the control gate is not located in a floating gate of the left floating gate memory cell and a floating of the right floating gate memory cell The left and right boundaries of the portion above the gate are outer boundaries of floating gates greater than or equal to the left floating gate memory cell and the floating gate of the right floating gate memory cell. The non-self-aligned non-volatile memory structure of claim 1, wherein the gate insulating layer is made of tetraethyl-ortho-silicate (TEOS). The non-self-aligned non-volatile memory structure of claim 1, wherein the control gate is made of polysilicon. The non-self-aligned non-volatile memory structure of claim 1, wherein the semiconductor substrate further comprises a well type region, and the left floating gate memory cell and the right floating gate memory The body cell system is located in the well type region. The non-self-aligned non-volatile memory structure of claim 1, wherein the left floating gate memory cell and the right floating gate memory cell each comprise: a floating gate insulating layer, Is located on the semiconductor substrate; a floating gate is disposed on the floating gate insulating layer; and a drain and a source are located in the semiconductor substrate and are respectively located in the floating gate insulating layer The second side is adjacent to the floating gate insulating layer. The non-self-aligned non-volatile memory structure of claim 1 or 6, wherein the right floating gate memory cell is shared with a source of the left floating gate memory cell.