TWI690061B - Single gate multiple writing to non-volatile memory and operation method thereof - Google Patents

Abstract

A single gate is written to non-volatile memory multiple times and its operation method. The non-volatile memory is a single floating gate, which is provided with a transistor and a capacitor structure on the semiconductor substrate, the transistor is on the conductive gate The semiconductor substrate on both sides has two ion doped regions as the source and the drain, wherein the width of the source and the drain is designed to be different, and the edge of the drain can be used as a capacitor to control the floating gate; The minimum control voltage type and the minimum number of components can be used at the time of input, which can greatly shorten the length of the control circuit, achieve the effect of reducing the overall area, and reduce the production cost of non-volatile memory.

Description

Single gate multiple writing to non-volatile memory and operation method thereof

The invention relates to a single-gate multiple write non-volatile memory (Non-Volatile Memory), in particular to a single-gate multiple write non-volatile using a drain edge as a capacitor to control a floating gate Sexual memory and its operation method.

According to this, the complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) process technology has become a common manufacturing method for application specific integrated circuits (ASIC). Today, with the development of computer information products, electronically erasable programmable read only memory (Electrically Erasable Programmable Read Only Memory, EEPROM) has the function of electrically writing and erasing nonvolatile memory, and the power is off The data will not disappear after being dropped, so it is widely used in electronic products.

The non-volatile memory system is programmable, which is used to store charge to change the gate voltage of the transistor of the memory, or not to store charge to leave the gate voltage of the transistor of the original memory. The erase operation is to remove all charges stored in the non-volatile memory, so that all the non-volatile memory returns to the gate voltage of the transistor of the original memory. In the structure of the conventional single-gate non-volatile memory, there are many types of control voltages and many memory elements, so the area of the non-volatile memory is large, resulting in an increase in cost.

In view of this, the present invention specifically proposes a single gate multiple write to non-volatile memory and its operation method in order to greatly reduce the area of single gate non-volatile memory and enhance the single Product value of gate non-volatile memory.

The main object of the present invention is to provide a single gate multiple writing non-volatile memory and operation method thereof, the source and the drain in the non-volatile memory are designed to have different widths, so as to use the edge of the drain as a capacitor To control the floating gate, the minimum voltage type and the minimum number of components can be controlled during writing to achieve the effect of reducing the overall area. Compared with the general non-volatile memory that can be written to a single gate, the cost is increased due to the complicated control. Because of the simple operation and the minimum number of components, the invention greatly reduces the control circuit, which can greatly reduce the cost of the non-volatile memory.

Therefore, in order to achieve the above purpose, a single gate multiple write nonvolatile memory disclosed by the present invention includes a P-type semiconductor substrate, transistors and capacitor structures ; Among them, the transistor and the capacitor structure are arranged on the P-type semiconductor substrate, the transistor is stacked by the first conductive gate on the surface of the first dielectric layer, the first dielectric layer is located on the P-type semiconductor substrate, and there are two highly conductive The ion-doped region is located in the P-type semiconductor substrate on both sides of the first conductive gate and the first dielectric layer to form the source and the drain, and the source and the drain have different widths; the capacitor structure uses the drain The edge is used as a capacitor to control the floating gate, and a lightly doped region is included between the drain and the floating gate. The lightly doped region and the ion doped region have the same type of ions, and form a single floating connection of non-volatile memory Gate.

In the present invention, the semiconductor substrate is a P-type semiconductor substrate or a semiconductor substrate with a P-type well, the transistor structure is an N-type transistor, and the lightly doped region and the ion-doped region are N-type ion-doped regions.

In addition, the operation method of the single gate multiple writing non-volatile memory disclosed in the present invention can write the non-volatile multiple times for the single gate composed of the above P-type semiconductor substrate, transistor and capacitor structure The memory performs the writing or erasing process by applying the substrate voltage V _sub , the source voltage V _s , and the drain voltage V _d to the P-type semiconductor substrate, the source, and the drain, respectively. Among them, when writing, satisfy V _sub is ground (= 0), V _d = V _s = high voltage (HV); or V _d = high voltage (HV), and V _s = medium voltage (MV) or low voltage (LV) ); or V _d = medium voltage (MV), V _s = low voltage (LV) or ground (0). When erasing, satisfy V _sub is ground (0), V _d = high voltage (HV), V _s = floating; or V _d = high voltage (HV), V _s is ground (= 0); or V _s = High voltage (HV) with V _d = ground (0); or V _s = high voltage (HV) with V _d = floating.

The following detailed description will be made with specific embodiments and accompanying drawings to make it easier to understand the purpose, technical content, features, and effects of the present invention.

Please refer to FIG. 1, which is a cross-sectional view of a single gate multiple write non-volatile memory structure according to an embodiment of the present invention.

The single gate multiple write non-volatile memory 100 includes a P-type semiconductor substrate 130, or a semiconductor substrate with a P-type well. Here, the P-type semiconductor substrate 130 is taken as an example, and the NMOS transistor (NMOSFET) 110 The N-type capacitor structure 120 is disposed in the P-type semiconductor substrate 130; the NMOS transistor 110 includes a first dielectric layer 111 on the surface of the P-type semiconductor substrate 130, and the first conductive gate 112 is stacked on the first dielectric layer 111 Above, and the two-ion doped region is located in the P-type semiconductor substrate 130, respectively as its source 113 and drain 114, a channel 115 is formed between the source 113 and the drain 114, and the source 113 and the drain 114 have different Width; The N-type capacitor structure 120 uses the edge of the drain 114 as a capacitor to control a floating gate, and forms a single floating gate of the non-volatile memory 100 (floating gate). Specifically, the edge of the drain 114 is in the middle of the floating gate. Among them, the light-doped region 116 is included between the drain 114 and the floating gate, and the ion-doped region and the light-doped region are N-type ion-doped regions.

In the present invention, the widths of the source electrode 113 and the drain electrode 114 refer to their side lengths along a horizontal axis direction (that is, the parallel direction from the source electrode 113 to the drain electrode 114), as shown in FIG. 1, In the embodiment, the width W _d of the drain 114 is greater than the width W _{s of the} source 113. In addition, the lengths of the source 113 and the drain 114 may also be different. As shown in FIG. 2, one aspect of this embodiment is to design the length L _d of the ion-doped region of the drain 114 to be greater than the source 113 ion doping zone length L _s; Further, as shown in FIG. 3, another aspect of the present embodiment is the length of the ion doping of the drain region 114 of L _d designed to be larger in ion-doped source 113 The length of the miscellaneous area L _s , and its two opposite sides present an angle.

The single gate multiple writing non-volatile memory 100 is provided with three terminals. The schematic diagram is shown in FIG. 4. The three terminals are the source, the drain, and the substrate connection structure, and are in P-type. A substrate voltage V _sub , a source voltage V _s and a drain voltage V _{d are} applied to the semiconductor substrate 130, the source 113 and the drain 114, respectively. The operating voltage of the single gate multiple times writing to the non-volatile memory 100 is as follows: When writing: a. V _sub = ground (0). b. V _d = V _s = high voltage (HV); or V _d = high voltage (HV), and V _s = medium voltage (MV) or low voltage (LV); or V _d = medium voltage (MV), and V _s = Low voltage (LV) or ground (0). When erasing: a. V _sub = ground (0). b. V _d = high voltage (HV) and V _s = ground (0); or V _d = high voltage (HV) and V _s = floating; or V _s = high voltage (HV) and V _d = ground ( 0); or V _s = high voltage (HV), and V _d = floating.

Further, the ranges of "high voltage", "medium voltage" and "low voltage" proposed in the above bias conditions are specifically described, where "high voltage" refers to the breakdown voltage of the drain to the source-the critical voltage of the transistor V _t ; "Medium voltage" refers to the breakdown voltage of the drain to the source *1/2; and "Low voltage" refers to the breakdown voltage of the drain to the source *1/4.

The structure in Figure 1 above is manufactured on a P-type silicon wafer. After the basic isolation structure is completed by the standard isolation module process, a channel of an NMOS transistor is formed by ion implantation. After a dielectric layer of a conductive gate, then, polysilicon is deposited and patterned by lithography to form the polysilicon into a single floating gate; then, ion implantation is performed to form the drain and source of the NMOS transistor Extreme electrode. After metallization, many single gates are written to the non-volatile memory structure.

To sum up, according to the disclosed single-gate multiple writing non-volatile memory and its operation method, compared with the general non-volatile memory that can be written to single gate, its control is complicated and costly Higher, the invention can minimize the control voltage and the least components during writing, which can greatly reduce the area of the non-volatile memory, and can shorten the length of the control circuit, so as to achieve the purpose of greatly reducing production costs.

The above describes the characteristics of the present invention through embodiments, and its purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly, rather than limiting the patent scope of the present invention. The equivalent modification or modification completed by the disclosed spirit should still be included in the scope of the patent application described below.

100: Single gate writes to non-volatile memory multiple times

110: NMOS transistor

111: first dielectric layer

112: the first conductive gate

113: source

114: Jiji

115: channel

116: Lightly doped region

120: N-type capacitor structure

130: P-type semiconductor substrate

L _d : length

L _s : length

V _d : drain voltage

V _s : source voltage

V _sub : base voltage

W _d : width

W _s : width

FIG. 1 is a cross-sectional view of a single gate multiple write non-volatile memory structure according to an embodiment of the invention. FIG. 2 is a layout structure of source and drain having different widths in an embodiment of the present invention. FIG. 3 is another layout structure of the source and the drain having different widths according to an embodiment of the present invention. FIG. 4 is a schematic diagram of a structure with three endpoints according to an embodiment of the invention.

100: Single gate writes to nonvolatile memory multiple times

110: NMOS transistor

111: first dielectric layer

112: the first conductive gate

113: source

114: Jiji

115: channel

116: Lightly doped region

120: N-type capacitor structure

130: P-type semiconductor substrate

W _d : width

W _s : width

Claims (2)

A single gate multiple writing non-volatile memory includes: a P-type semiconductor substrate; an transistor, the transistor is disposed on the P-type semiconductor substrate, the transistor includes a first dielectric layer, a first A conductive gate and a plurality of ion-doped regions, the first dielectric layer is located on the surface of the P-type semiconductor substrate, the first conductive gate is stacked on the first dielectric layer, and the ion-doped regions are located on The semiconductor substrate is located on both sides of the first conductive gate, forming a source and a drain, respectively, the source and the drain have different widths; and a capacitor structure, the capacitor structure is disposed on the P-type semiconductor substrate The capacitor structure uses the edge of the drain as a capacitor to control a floating gate, and a lightly doped region is included between the drain and the floating gate. The lightly doped region and the ion doped regions have Ions of the same type form a single floating gate of the non-volatile memory. An operation method for single gate multiple writing into non-volatile memory, the non-volatile memory includes a P-type semiconductor substrate, a transistor and a capacitor structure, the transistor is disposed on the P-type semiconductor substrate, the electric The crystal includes a first dielectric layer, a first conductive gate and a plurality of ion doped regions, the first dielectric layer is located on the surface of the P-type semiconductor substrate, and the first conductive gate is stacked on the first dielectric On the layer, the ion-doped regions are disposed in the semiconductor substrate and are located on both sides of the first conductive gate, forming a source and a drain, respectively, and the source and the drain have different widths, and the capacitor structure The edge of the drain is used as a capacitor to control a floating gate, and a lightly doped region is included between the drain and the floating gate. The lightly doped region and the ion doped regions have the same type of ions. A single floating gate of the non-volatile memory is formed. The operation method is characterized in that: a substrate voltage V _sub and a source voltage V _s are respectively applied on the P-type semiconductor substrate, the source electrode and the drain electrode And a drain voltage V _d and satisfy the following conditions: when writing: a. V _sub = ground (0); and b. V _d = V _s = high voltage (HV); or V _d = high voltage (HV), And V _s = medium voltage (MV) or low voltage (LV); or V _d = medium voltage (MV), and V _s = low voltage (LV) or ground (0); when erasing: a. V _sub = ground ( 0); and b. V _d = high voltage (HV), and V _s = ground (0); or V _d = high voltage (HV), and V _s = floating; or V _s = high voltage (HV), and V _d = ground (0); or V _s = high voltage (HV), and V _d = floating.

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