TWI635496B - Method for erasing single-gate non-volatile memory - Google Patents

Abstract

A single gate non-volatile memory erasing method, the non-volatile memory has a single floating gate structure, when performing an erase operation, a voltage is applied to the drain, and the gate is not applied with a voltage, The bucker voltage is used to generate and control the anti-layer, thereby reducing the erase voltage and elevating the erase speed, and preventing over-wiping.

Description

Method for erasing single-gate non-volatile memory

The present invention relates to a non-volatile memory (Non-Volatile Memory), and more particularly to a single-gate non-volatile memory that can be used for erasing memory elements with an oxide layer thickness greater than 100 angstroms (Å) for high-pressure processes. Method of erasing memory.

According to CMOS, Complementary Metal Oxide Semiconductor (CMOS) process technology has become a common manufacturing method for application specific integrated circuits (ASICs). Today, with the development of computer information products, electronically erasable programmable read only memory (EEPROM) has a nonvolatile memory function for electrically writing and erasing data. The data will not disappear after being dropped, so it is widely used in electronic products.

The non-volatile memory system is programmable, which is used to store the charge to change the gate voltage of the transistor of the memory, or not to store the charge to leave the gate voltage of the transistor of the original memory. The erase operation is to remove all the charges stored in the non-volatile memory, so that all the non-volatile memory returns to the gate voltage of the transistor of the original memory. Therefore, in the structure of the conventional non-volatile memory, in addition to the gate layer of the transistor, an additional conductive layer needs to be added to store the charge, thereby forming a double-layer structure. More thin film deposition, etching, and exposure and development steps than ordinary CMOS processes, which increase the cost, make the process complicated, reduce the component yield, and increase the working hours, especially when used in embedded EEPROM products.

In the conventional method of erasing EEPROM elements, the stored charge is moved from the floating gate to the electric power under the tunneling effect of the Fowler-Nordheim tunneling (referred to as FN tunneling) technology. To remove the crystal, the voltage often needs to be greater than 10V. Because the structure of the single-gate EEMPROM memory is a transistor substrate-floating gate-capacitor substrate, the stored charge can be released to any direction according to the direction of the electric field application. ; Causes the problem of excessive erasure of single-gate EEPROM components becomes more serious.

In view of the above problems, the main object of the present invention is to provide a method for erasing a single-gate non-volatile memory, which uses a single floating gate structure and has an oxide layer with a thickness greater than 100 Angstroms (Å) in a high-pressure process. Single-gate non-volatile memory for memory element erasing; when erasing, voltage is applied to the drain, and no voltage is applied to the gate to generate and control the reverse layer by the drain voltage, thereby improving erasing The efficiency is stopped when the drain voltage is reduced or the source voltage is increased when erasing is completed, which can prevent excessive erasing and solve the deficiency of the prior art.

Therefore, in order to achieve the above object, the method for erasing the single-gate non-volatile memory disclosed in the present invention is applied to the single-gate non-volatile memory. The single-gate non-volatile memory includes a P-type semiconductor substrate. Transistor and capacitor structure, wherein the transistor and capacitor structure are disposed on a P-type semiconductor substrate, the transistor is stacked on the surface of the first dielectric layer by a first conductive gate, and the first dielectric layer is located on the semiconductor substrate, and There are two highly conductive first ion-doped regions on the two sides of the first conductive gate and the first dielectric layer to form a source and a drain; the capacitor structure, like a transistor, also forms a sandwich structure, including a second ion doping The miscellaneous region, the second dielectric layer and the second conductive gate, and the second conductive gate of the capacitor structure and the first conductive gate of the transistor are isolated and electrically connected to form a single floating non-volatile memory. Connect the gate. The erasing method of the single-gate non-volatile memory includes applying a voltage to the drain, and the gate does not apply a voltage, so as to generate and control the reverse layer by the drain voltage to reduce the erase voltage and increase Erase effect.

The first ion-doped region and the second ion-doped region are N-type doped regions, and the capacitor structure may be an N-type capacitor or an N-well capacitor. It is within the scope of the present invention to use the method of the present invention to erase the non-volatile memory with different structural changes.

Specifically, the method for erasing a single-gate non-volatile memory disclosed in the present invention can perform an erasing process on a non-volatile memory composed of a P-type semiconductor substrate, a transistor, and a capacitor structure. The substrate voltage, source voltage, and drain voltage are applied to the P-type semiconductor substrate, the source, and the drain, respectively, and no voltage is applied to the second ion-doped region, and the drain voltage is greater than the source voltage. The voltage is greater than or equal to the substrate voltage, which is grounded.

In the following, detailed descriptions will be made through specific embodiments in conjunction with the accompanying drawings to make it easier to understand the purpose, technical content, features and effects of the present invention.

FIG. 1A is a cross-sectional view of a single-gate non-volatile memory structure according to a first embodiment of the present invention. The single-gate non-volatile memory structure 30 includes an NMOS transistor (NMOSFET) 32 and an N-well (N -well) capacitor 34 in P-type silicon substrate 36; NMOS transistor 32 includes a first dielectric layer 320 on the surface of P-type silicon substrate 36, and a first conductive gate 322 is stacked on top of the first dielectric layer 320 And two N ⁺ ion doped regions are located in the P-type silicon substrate 36, and serve as its source 324 and drain 324 ', respectively, forming a channel 326 between the source 324 and the drain 324'; the N-well capacitor 34 includes a first A two-ion doped region is located in the P-type silicon substrate 36 as its N-well 340, the second dielectric layer 342 is located on the surface of the N-well 340, and the second conductive gate 344 is stacked on the second dielectric layer 342, The capacitor structure is formed to form a top plate, a dielectric layer, and a bottom plate. The first conductive gate 322 of the NMOS transistor 32 and the second conductive gate 344 on top of the N-well capacitor 34 are electrically connected and isolated by an isolation structure 38 to form a single floating gate 40. structure.

The single-gate non-volatile memory structure 30 is provided with a structure of four terminals. As shown in FIG. 2A, the four terminals are a source, a drain, a control gate, and a substrate. A base voltage V _sub , a source voltage V _s , and a drain voltage V _d are applied to the source and the drain, respectively, and the control gate voltage V _c is applied to the second ion-doped region; FIG. 2C is an equivalent circuit thereof. . The conditions of the erasing process of the single-gate non-volatile memory structure 30 are as follows: a. V _sub is grounded (= 0); and b. V _s ≧ V _sub = 0, and V _s <V _d .

Therefore, V _d > V _s ≧ V _sub = 0, and V _c means that no voltage is applied.

Next, FIG. 1B is a cross-sectional view of a single-gate non-volatile memory structure according to a second embodiment of the present invention. The single-gate non-volatile memory structure 50 includes an NMOS transistor (NMOSFET) 52 and an N-type The capacitor 54 is in a P-type silicon substrate 56; the NMOS transistor 52 includes a first dielectric layer 520 on the surface of the P-type silicon substrate 56, a first conductive gate 522 is stacked on the first dielectric layer 520, and two The N ⁺ ion doped region is located in the P-type silicon substrate 56 and serves as its source 524 and drain 524 ', respectively. A channel 526 is formed between the source 524 and the drain 524'; the N-type capacitor 54 includes a second ion dopant. The impurity region is in the P-type silicon substrate 56, the second dielectric layer 542 is located on the surface of the P-type silicon substrate 56, and the second conductive gate 544 is stacked on the second dielectric layer 542 to form a top plate-dielectric layer. -Capacitive structure of the bottom plate. The first conductive gate 522 of the NMOS transistor 52 and the second conductive gate 544 on top of the N-type capacitor 54 are electrically connected and isolated by an isolation structure 58 to form a single floating gate 60. structure.

The single-gate non-volatile memory structure 50 is provided with a structure of four endpoints. As shown in FIG. 2B, the four endpoints are a source, a drain, a control gate, and a substrate. A base voltage V _sub , a source voltage V _s , and a drain voltage V _d are applied to the source and the drain, respectively, and the control gate voltage V _c is applied to the second ion-doped region; FIG. 2C is an equivalent circuit thereof. . The conditions for the erasing process of the single-gate non-volatile memory structure 50 are as follows: a. V _sub is grounded (= 0); and b. V _s ≧ V _sub = 0, and V _s <V _d . Therefore, V _d > V _s ≧ V _sub = 0, and V _c is the voltage not applied.

The structure of FIG. 1A is manufactured on a P-type silicon wafer. The isolation structure 38 is completed by a standard isolation module process. After the basic isolation structure 38 is formed, the N-well 340 and the NMOS transistor 32 The channel 326 is formed by ion implantation. After the dielectric layers of the first conductive gate 322 and the second conductive gate 344 are grown, polycrystalline silicon is deposited and patterned by lithographic etching to form polycrystalline silicon. The gate 40 is connected; then ion implantation is performed to form electrodes such as the source 324, the drain 324 'and the control gate of the NMOS transistor 32. After metallization, the fabrication of many single-gate non-volatile memory structures 30 is completed.

Using the same process, the single-gate non-volatile memory structure 50 shown in FIG. 1B above is manufactured on a P-type silicon wafer, and the isolation structure 58 is completed by a standard isolation module process; After the basic isolation structure 58, the channel 526 of the N-type capacitor 54 and the NMOS transistor 52 is formed by ion implantation; after the dielectric layers of the first conductive gate 522 and the second conductive gate 523 are grown, then Polycrystalline silicon is deposited and patterned by lithographic etching to form single floating gate 60; then, ion implantation is performed to form electrodes such as source 524, drain 524 ', and control gate of NMOS transistor 52. . After the metallization, the fabrication of the single-gate non-volatile memory structure 50 is completed.

In the present invention, the above process refers to a general CMOS manufacturing process.

In summary, the present invention proposes a method for erasing a single-gate non-volatile memory, which applies a voltage to the drain of the single-gate non-volatile memory structure, and does not apply a voltage to the gate to thereby The drain layer is used to generate and control the inversion layer, which can reduce the erase voltage and increase the erase speed. When the erase is completed, the drain voltage will decrease due to the channel opening or the source voltage will increase, and the erase will stop. Reduce the erasing voltage and solve the problem of over-erase.

The above is the description of the features of the present invention through the examples. The purpose is to enable those skilled in the art to understand the contents of the present invention and implement them accordingly, rather than to limit the patent scope of the present invention. Equivalent modifications or modifications made by the disclosed spirit should still be included in the scope of patent application described below.

30‧‧‧Single-gate non-volatile memory structure

32‧‧‧NMOS transistor

320‧‧‧ first dielectric layer

322‧‧‧First conductive gate

324‧‧‧Source

324’‧‧‧ Drain

326‧‧‧channel

34‧‧‧N Well Capacitance

Well 340‧‧‧N

342‧‧‧Second dielectric layer

344‧‧‧Second conductive gate

36‧‧‧P-type silicon substrate

38‧‧‧Isolation structure

40‧‧‧Single floating gate

50‧‧‧Single-gate non-volatile memory structure

52‧‧‧NMOS Transistor

520‧‧‧First dielectric layer

522‧‧‧The first conductive gate

524‧‧‧Source

524’‧‧‧ Drain

526‧‧‧channel

54‧‧‧N type capacitor

542‧‧‧Second dielectric layer

544‧‧‧Second conductive gate

56‧‧‧P-type silicon substrate

58‧‧‧Isolation structure

60‧‧‧Single floating gate

FIG. 1A is a cross-sectional view of a single-gate non-volatile memory structure according to a first embodiment of the present invention.

FIG. 1B is a cross-sectional view of a single-gate non-volatile memory structure according to a second embodiment of the present invention.

FIG. 2A is a schematic diagram of a structure provided with four endpoints according to the first embodiment of the present invention.

FIG. 2B is a schematic structural diagram of a second embodiment of the present invention provided with four endpoints.

Fig. 2C is an equivalent circuit of the structures of Figs. 2A and 2B.

Claims (3)

A method for erasing a single-gate non-volatile memory. The non-volatile memory system includes a P-type semiconductor substrate, a transistor, and a capacitor structure. The transistor and the capacitor structure are disposed on the P-type semiconductor substrate. The transistor includes a first conductive gate and a plurality of first ion-doped regions, and the first ion-doped regions form a source and a drain on both sides of the first conductive gate respectively, and the capacitor structure The erasing method includes a second ion-doped region and a second conductive gate, and the first conductive gate and the second conductive gate are electrically connected to form a single floating gate. The erasing method is characterized by: A substrate voltage V _sub , a source voltage V _s and a drain voltage V _d are applied to the P-type semiconductor substrate, the source and the drain, respectively, and no voltage is applied to the second ion-doped region, And satisfy the following conditions: V _d > V _s ≧ V _sub ; and V _sub is ground. The method for erasing the single-gate non-volatile memory according to item 1 of the claim, wherein the first ion-doped regions and the second ion-doped regions are N-type doped regions, and the capacitor structure It is N-type capacitor or N-well capacitor. The method for erasing the single-gate non-volatile memory according to item 1 of the claim, wherein the transistor system is a metal-oxide-semiconductor field-effect transistor (MOSFET).