TW200301011A - Nonvolatile semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

The purpose of the present invention is to miniaturize or make the nonvolatile semiconductor memory device highly reliable. It has a memory cell comprising a source/drain diffusion layer 105 in p-well 101 formed on a silicon substrate 100, a floating gate 107b as a first gate, a control gate 110a (word line) as a second gate, and a third gate 103a, in which the floating gate 107b and the p-well 101 are isolated by a tunnel insulator film 106a, the third gate 103a and the p-well 101 are isolated by a gate insulator film 102, the floating gate 107b and the third gate 103a are isolated by an insulator film 106b, the floating gate 107b and the word line 110a (control gate) are isolated by an insulator film 109a (ONO film), and the third gate 103a and the word line (control gate) are isolated by a silicon oxide film, respectively, in which the thickness of the tunnel insulator film 106a is made larger than the thickness of the gate insulator film 102.

Description

200301011 A7 B7 V. Description of the invention (1) Technical field (please read the precautions on the back before filling out this page) The present invention is about semiconductor integrated circuit devices and their manufacturing technology, especially regarding the realization of non-volatile semiconductor memory devices High integration, high reliability or high performance. Conventional technology A non-volatile semiconductor memory device (EEPROM: Electrically Erasable Programmable Read Only Memory) capable of electrically writing and erasing, which is superior to portability, impact resistance, and electrical performance. The batch has been eliminated, and in recent years, the use of portable memory for program memory, or portable personal computers and digital still cameras and other small portable information equipment such as documents has rapidly expanded their needs. In addition, the microcomputer in the engine control system such as a car is also integrated with a crystal. The expansion of the market must reduce the area of the storage unit to reduce the bit cost, and there are proposals for various storage unit methods that can achieve this. One of them is a virtual ground-type memory cell using a three-layer polysilicon gate as disclosed in Japanese Unexamined Patent Publication No. 11-200242. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, the Consumer Cooperative, this type of storage unit, as shown in Figure 60, consists of the well 601 in the silicon substrate 600, the source and drain diffusion layer 605 in the well 601. 605, and the floating gate 603b of the first gate formed by the polycrystalline silicon film formed on the well, the control gate 611a of the second gate, and the third gate that can control the function of erasing the gate and dividing the channel 607a consists of three gates. This paper size applies to Chinese National Standard (CNS) A4 specification (210X297 mm) -5- 200301011 A7 B7 V. Description of the invention (2) (Please read the precautions on the back before filling this page) The gate made of each polycrystalline silicon film Between the electrodes 603b, 611a, and 607a, and between the gate and the well 601 formed by the polycrystalline silicon film, the insulating films 602, 606a, 606b, 608a, and 610 are separated. The control gate 611a is connected in the row direction to form a word line. The source and drain diffusion layers 605 are a virtual ground type of a diffusion layer that shares adjacent memory cells, thereby reducing the distance between the rows in the figure. The third gate electrode 607a is parallel to the channel, and is arranged perpendicular to the word line 611a. During writing, independent positive voltages are applied to the word line 611a, the drain electrode 605, and the third gate electrode 607a, respectively, to cause the well 601 and the source 605 'to overvoltage. As a result, thermal electrons are generated in the channel between the third gate and the boundary of the floating gate and injected into the floating gate 603b. Therefore, the threshold of the memory cell is increased. When cleared, a positive voltage is applied to the third gate 607a, which causes the word line 611a, the source 605, the drain 605, and the well 601 to overvoltage. As a result, electrons are discharged from the floating gate 603b to the third gate 607a, and the threshold value is reduced. In this way, the threshold voltage of the memory cell transistor is changed to determine the "0" and "Γ" of the information. However, when trying to increase the capacity of the above nonvolatile semiconductor memory device, a new problem has arisen. Intellectual Property of the Ministry of Economic Affairs Printed by the Bureau's Consumer Cooperatives First, the first point is the miniaturization of the storage unit. When this split gate type storage unit is further refined, it is important to reduce the gate length of the floating gate 603b and the third gate 607a. It is necessary to thin the respective gate insulating films 602 and 606a to improve the punch-through resistance. However, the review regarding the film thickness of each gate insulating film has not been discussed. The second point is high reliability. Flash memory needs to be repeated. After more than 100,000 rewrites, the data can not be guaranteed for more than 10 years. The disappearance of the data is caused by the leakage of the electrons stored in the floating gate. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297) (Central) -6-200301011 A7 B7 V. Description of the invention (3) (Please read the precautions on the back before filling out this page) Although there are many reasons for the leak, there are many reasons for this. As a result of the research, it has been determined that the mode in which the accumulated electrons of the floating gate of a specific bit leak to the substrate suddenly is the most important. This leakage mode and the gate insulation film between the floating gate and the substrate are 602 g of the gastric tunnel membrane. The film thickness is related, and the thinner the film, the more bad bits increase. In the inventor's review, especially the memory of two bits of data for a memory cell, it has been clear that the data is retained for 10 years. It is necessary to set the film thickness of the tunnel insulating film 602 to 9nm or more. Therefore, when miniaturizing the memory cell, it is necessary to develop a unit that considers the gate insulating film 602 and 606a film thickness. Consumption by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs The third point printed by the cooperative is the increase in the number of projects. Usually flash memory systems have peripheral circuits that apply voltage to the memory cells or perform logical operations. The circuits that apply voltage to the cells are applied, for example, to word lines. The applied high voltage of 18V causes the MOS (Metal Oxide Semiconductor) transistor constituting the circuit to have a high withstand voltage structure, and a thick gate insulating film, for example, 25nm is used. For circuits that perform logic operations, the applied voltage is, for example, 3V of the external power supply voltage, and high-speed operation is required. Therefore, the gate insulation film thickness of M0S that implements logic operation circuits is much thinner than that of high withstand voltage systems. Therefore, from the viewpoint of cost reduction, how to form the two gate insulating films of the peripheral circuits and the two gate insulating films of the memory cells has become an important issue to simplify the manufacturing process. The development of new non-volatile semiconductor memory devices and manufacturing methods required to solve the problems related to the gate insulating film of split gate memory cells is expected. This paper standard is applicable to the Chinese National Standard (CNS) A4 specification (21〇 > < 297 mm) 200301011 A7 B7 V. Description of the invention (4) The object of the present invention is to miniaturize a non-volatile semiconductor memory device. Other objects of the present invention are to illustrate the non-volatile semiconductor memory device. Bureau trust. Still another object of the present invention is to simplify the manufacturing process of a non-volatile semiconductor memory device. The above and other objects and novel features of the present invention will become clearer from the description of the specification and the attached drawings. Means to Solve the Problem Among the inventions disclosed in this case, the representative of the representative is briefly explained, but it is the next most important. (1) The above-mentioned problem lies in the field of forming a first conductivity type well formed in a silicon substrate, a second conductivity type source / drain diffusion layer formed in the well, and forming the diffusion layer area in a vertical direction. The channel, the floating gate of the first gate formed by the insulating film on the silicon substrate, and the control gate of the second gate formed by the floating gate and the insulating film, and connected to the control gate. The formed zigzag line is a non-volatile non-volatile memory cell formed with the silicon substrate, the floating gate, the control gate, and the insulating film and having a function different from that of the third gate of the floating gate and the control gate. The semiconductor memory device can be achieved by setting the thickness of the gate insulating film between the floating gate and the well to be larger than the thickness of the gate insulating film between the third gate and the well. (2) At this time, the third gate can control the gate of the split channel. (3) Or the third gate has a gate that can control the erasing of the gate and the split channel. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (21〇 > < 297mm) -------- Appeal-(Please read the notes on the back before filling this page)

, 1T Μ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -8-200301011 A7 B7 V. Description of the invention (5) Functions of both sides. (Please read the precautions on the back before filling out this page) (4) It is more suitable if the insulating film between the third gate and the well is the same as the gate insulating film of the low-voltage system part of the peripheral circuit. (5) Or, it is more suitable if the insulating film between the floating gate and the well is the same as the gate insulating film of the low-voltage system part of the peripheral circuit. (6) At this time, the film thickness of the insulating film between the floating gate and the third gate is larger than the film thickness of the insulating film between the floating gate and the well. (7) Alternatively, the film thickness of the insulating film between the floating gate and the third gate is approximately the same as the film thickness between the floating gate and the well. (8) At this time, the insulating film between the floating gate and the third gate is preferably a silicon oxide film with nitrogen added. (9) The above-mentioned subject is printed by a consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs in the field of having a first conductivity type well formed in a silicon substrate and a second conductivity type source / drain diffusion layer formed in the well. With a channel formed in the diffusion layer field in a vertical direction, a floating gate with a first gate formed by an insulating film on the silicon substrate, and a control gate with the second gate formed by the floating gate and the insulating film Pole, formed with the word line connected to the control gate, formed with the silicon substrate, the floating gate, the control gate, and the insulating film, and having a function different from the storage of the third gate of the floating gate and the control gate As one of the constituent elements, the unit is a non-volatile semiconductor memory device provided with peripheral circuits required to promote the operation of the above-mentioned storage unit. The peripheral circuit is composed of a MOS transistor of a low-voltage system and a high-voltage system, so that the MOS transistor of the low-voltage system. The film thickness of the gate insulating film is approximately the same as that of the third gate and the gate insulating film between the wells, and the gate insulating film of the high-voltage system MOS transistor, the gate insulating film between the floating electrode and the well, and the third Between the gate and the well Cis gate insulating film of the present paper is suitable China National Standard Scale (CNS) A4 size (210X 297 mm) -9- 200301011 A7 B7 V. Description of the Invention (6) film thickness of the insulating sequence but may be gradually increased to reach it. (Please read the precautions on the back before filling this page) (10) Or, in the field of having a first conductivity type well formed in a silicon substrate and a second conductivity type source / drain diffusion layer formed in the well Control with a channel formed in the diffusion layer field in a vertical direction, a floating gate with a first gate formed by an insulating film on the silicon substrate, and a second gate formed by the floating gate and the insulating film The gate is formed with a word line connected to the control gate, and formed with the silicon substrate, the floating gate, the control gate, and an insulating film, and has a function different from that of the third gate of the floating gate and the control gate. As one of the constituent elements, the memory cell is a non-volatile semiconductor memory device provided with peripheral circuits required to promote the operation of the memory cell. The peripheral circuit is constituted by a MOS transistor of a low-voltage system and a high-voltage system. The gate insulation film has approximately the same thickness as the gate insulation film between the floating gate and the well. The gate insulation film of the high-voltage system MOS transistor, the gate insulation film between the floating gate and the well, the third gate and Smoothing of gate insulation film between wells The thickness of the insulation can be increased gradually and reached it. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (11) For the solution of the above-mentioned problem, the hot-electron injection from the channel to the floating gate to implement the writing of the above-mentioned storage unit, and the discharge from the floating gate to the tunnel of the trap for implementation Elimination of the above memory cells. (12) Or, the above-mentioned memory cell writing can be performed by injecting hot electrons from the channel to the channel of the floating gate, and releasing it from the floating gate to the tunnel of the third gate to implement the elimination of the above-mentioned memory cell. (13) With another solution to the above-mentioned problem, the area between the first conductivity type well formed in the silicon substrate and the second conductivity type source / drain diffusion layer formed in the well is perpendicular to the vertical direction. The orientation is formed on the diffusion layer. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -10- 200301011 A7 B7. 5. Description of the invention (7) The channel of the domain and the dielectric film are formed on the sand substrate. The floating gate of the first gate above, and the control gate of the second gate formed by the floating gate and the channel and the insulation film, and the word line formed by connecting the control gate, and the silicon substrate. A non-volatile semiconductor memory device formed by a floating gate, a control gate, and an insulating film and having a function different from that of the third gate of the floating gate and the control gate. The thickness of the gate insulation film is set to be larger than the thickness of the gate insulation film separating the third gate from the well (14) At this time, the third gate eliminates the gate. (15) The film thickness of the insulating film between the floating gate and the control gate is larger than the film thickness between the floating gate and the well. (16) Alternatively, the film thickness of the insulating film between the floating gate and the control gate is approximately the same as the film thickness between the floating gate and the well. (17) At this time, the insulating film between the floating gate and the third gate is a silicon oxide film with nitrogen added. (1 8) The action method at this time is to implement the writing of the above-mentioned memory cell by injecting hot electrons from the channel to the channel of the floating gate, and to release the above-mentioned storage unit by the channel from the floating gate to the third gate. . (19) According to another solution to the above-mentioned problem, a field having a first conductivity type well formed in a sand substrate and a second conductivity type source / drain diffusion layer formed in the well may be provided in a vertical direction with The channel formed in the direction of the diffusion layer, the floating gate of the first gate formed by the dielectric film on the silicon substrate, and the control gate of the second gate formed by the floating gate and the channel and the insulating film. The paper size of the non-volatile semiconductor notebook paper with the storage unit as one of the constituent elements is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -------- install-(Please read the precautions on the back first (Fill in this page again), 11 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -11-200301011 A7 B7 V. Description of the invention (8) The memory device sets the thickness of the gate insulation film between the separation floating gate and the well as a ratio The thickness of the gate insulating film separating the control gate and the well is large. (Please read the precautions on the back before filling this page) (20) At this time, the above control gate can control the gate of the split channel. (21) Furthermore, the channel is injected with hot electrons from the channel to the floating gate to implement the writing of the above-mentioned memory cell, and the channel is released from the floating gate to the drain to implement the above-mentioned elimination of the memory cell. (22) The gate insulating film between the floating gate and the well, or the gate insulating film between the third gate and the well, is formed by the same process as the gate insulating film of the MOS transistor in the low-voltage part of the peripheral circuit. Yes. Embodiments of the Invention Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for explaining the embodiment, the same symbols are assigned to the same functions, and repeated descriptions thereof are omitted. (Embodiment 1) Printed using Figures 1 to 14 by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economics to explain the structure, operation method, and manufacturing of a nonvolatile semiconductor memory device (flash memory) according to Embodiment 1 of the present invention method. Fig. 1 is a plan view of a main part of a flash memory, and Figs. 3 to 14 are cross-sectional views of main parts of a substrate for flash memory manufacturing process description, respectively corresponding to A-A, line cross-sections of Fig. 1. FIG. 2 is a circuit diagram showing the configuration of a memory array when the memory cells are arranged in a matrix. First, the structure of the flash memory will be described. As shown in Figure 1 and Figure 14 of the A-A1 spring cross-section, this flash memory system consists of 100 silicon substrates. The paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) -12- 200301011 A7 B7____ V. Description of the invention (j forming the source / drain diffusion layer 105 in the P-well (semiconductor field) 101, (Please read the precautions on the back before filling this page) The floating gate of the first gate 107b , The second gate control gate (word line) 110a, and the third gate 103a. Each memory cell is formed in, for example, an area surrounded by a thick wire frame in FIG. 1. The predetermined number of The control electrode 110a of the memory cell M is connected in the row direction (X direction) to form a word line (WL0 to WLn in FIG. 2). The floating gate 107b and the P-type well 101 are formed by a gate insulating film 106a. The three gates 103a and P-type wells 101 are formed by a gate insulating film 102, the floating gate 107b and the third gate 103a are formed by an insulating mold 106b, the floating gate 107b and the word line (control gate) 110a are formed by an insulating mold (〇N 〇 film) 109a, and the third gate electrode 103a and the word line (control electrode) 110a are separated by sand oxide films 10 4 b and 10 9 a respectively. Source However, the drain / drain diffusion layer 105 is vertically arranged on the word line (control gate) 110a, and local source lines and local data lines connecting the source / drain of the column-direction (Y-direction) memory cells exist. That is, The non-volatile semiconductor memory device is composed of a so-called non-contact memory cell array in which each memory cell does not have a contact hole. A channel is formed in a vertical direction (X direction) of the source / drain diffusion layer 105. The side of the third gate 103a printed by the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed on the side extending in the Y direction, and the side extending in the Y direction among the above-mentioned floating gates • 107b, are opposed to each other through the insulating mold 106b It exists to the ground (refer to Figure 1). The floating gate 107b is buried in the gap between the majority of the third gates 103a existing in the vertical direction (γ direction) to the word line (control gate) 110a and the channel. The floating gate 107b is symmetrical to the third gate 103a, and the above-mentioned third gate i03a exists nominally to the floating gate 107b. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) ) -13- 200301011 A7 B7 V. Explanation (4 (Please read the precautions on the back before filling this page) In this embodiment, a source / drain pair of diffusion layer 105 is formed in an asymmetrical positional relationship with the pattern of floating gate 107b, and one side An offset structure in which the diffusion layer does not overlap the floating gate 107b. The third gate electrode 103a and the diffusion layer 105 overlap each other. Next, the write / erase operation will be described with reference to FIG. 2. When the memory cell M of FIG. 2 is selected for writing, a large positive voltage such as about 12V is applied to the word line WLm, a low voltage about 2V is applied to the third gate Age, and 4V is applied to the drain DLm. about. The source DLm — 1 and the well remain at 0V. As a result, a channel is formed in the well under the third gate 103a, and hot electrons are generated at the end channel of the floating gate on the source side, and electrons are injected into the floating gate. That is, the third gate electrode 103a functions to control the gate electrode of a channel existing in the lower portion thereof. According to this memory cell, compared with the conventional NOR-type flash memory bank, the generation of hot electrons can be increased and the injection efficiency can be improved, and writing can be performed in a field with a small channel current. Therefore, by knowing the current supply capability of the same degree, it is possible to write in parallel to most memory cells with thousands of ranks or more. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, when applied, the word line WLm is applied, such as a negative large voltage of 18V. At this time, the third gates AGe, AGO, all source / drain diffusion layers DL, and wells are kept at 0V. As a result, the electrons accumulated in the floating gate due to the tunnel phenomenon are released to the well. • The memory cell of this embodiment is different from the memory cell shown in FIG. 60, but as shown in FIG. 14, it is a gate insulation film 106a between the floating gate 107b and the P-well 101, and a so-called tunnel insulation. The film thickness is formed to be larger than the gate insulating film 102 between the third gate 103a and the P-well 101. This paper size applies Chinese National Standard (CNS) A4 specification (210X297mm) -14- 200301011 A 7 B7 V. Description of the invention (1) 1 (Please read the precautions on the back before filling this page) By using the tunnel insulation film The film thickness of 106a is formed to be large, which can suppress the charge retention failure caused by the sudden leakage of electrons accumulated in the floating gate to the substrate of a specific bit. In addition, by thinning the gate insulating film 102 of the third gate 103a, the MISFET (Metal Insulator Semiconductor Field Effect Transistor, referred to as "M〇") formed by the third gate 103a can be improved. S transistor ") can shorten the gate length of the third gate. In addition, according to this embodiment, since the gate insulating film 102 of the third gate 103a is formed into a thin film, the channel current can be increased, and the reading speed of the memory cell can be increased. Next, use FIG. 3 to FIG. 14 to show the manufacturing method of this storage unit. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs First, as shown in FIG. 3, after the P-well 101 is formed on the silicon substrate 100, the borrower The known thermal oxidation method forms a 7.5 mm gate insulating film 102 that can separate the third gate and the well. Next, as shown in FIG. 4, a phosphorus-doped polycrystalline silicon film 103 and a silicon oxide film 104 are sequentially deposited to form a third gate. Then, as shown in FIG. 5, the above-mentioned silicon oxide film 104 and the polycrystalline silicon film 103 are patterned by a well-known lithography and dry etching technique. As a result, the silicon oxide film and the polycrystalline silicon film become 104a and 103a (third gate), respectively. Then, as shown in FIG. 6, arsenic ions are implanted by the oblique ion implantation method to form a source / drain diffusion layer 105 that becomes a memory cell. Next, as shown in FIG. 7, by a known thermal oxidation method, a 9 nm thermal oxide film, a so-called tunnel insulating film 106a, is formed on a silicon substrate (p-well 101) to separate the floating gate and the substrate. At this time, the side wall of the third gate electrode 103a is formed about 20nm. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -15- 200301011 A7 B7 5. Description of the invention (enterprise thermal oxide film (insulating film) 106b The floating gate and the third gate can be separated. The film thickness of the thermal oxide film 106b is thicker than 106a, but it is doped with phosphorus in the polycrystalline silicon film of the third gate 103a material, which is caused by accelerated oxidation of the phosphorus Then, as shown in FIG. 8, the polycrystalline silicon film 107 that becomes a floating gate is deposited. At this time, the film thickness of the polycrystalline silicon film 107 is set to 値 that does not bury the gap between the laminated films of the silicon oxide film 104a. Thereafter, as shown in FIG. As shown, a fluid organic material 108, such as a resist material used in lithography or an anti-reflection mold, is applied to complete the gap between the laminated films in which the silicon oxide film 104a is buried. Then, as shown in FIG. The etching method repeatedly etches the organic material 108 having fluidity, leaving only the gap between the laminated film of the third gate electrode 103 and the silicon oxide film 104a. As a result, the organic material 108 having fluidity becomes 108a. Organic material i〇8a is made The mask was etched with the polycrystalline silicon film 107. As a result, the polycrystalline silicon film 107 retained the laminated film between the third gate 103a and the silicon oxide film 104a, and became the polycrystalline silicon film 108a. The organic material 108a became 108b. Secondly, as shown in FIG. 12, the organic material 108 b is removed by a known honing process. As shown in FIG. 13, a detachable floating gate and a word line are formed on a sand substrate by an oxide film with a film thickness of 13 nm. Silicon oxide film / silicon nitride film / 5th oxide film laminated film, so-called 0N 0 film 10 9. Then, as shown in FIG. 14, a stacked film of polycrystalline silicon film and tungsten silicide film, so-called polymer film (110). Next, the word line (control gate) is formed by patterning in the X direction shown in FIG. 1 by the well-known lithography and dry etching techniques. As a result, the polymer film 110 changes l10a ( The printed paper is again applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (please read the precautions on the back before filling this page). 1 = Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs-16- 200301011 A7 B7 V. Description of the invention (1) 3-wire, control (Please read the precautions on the back before filling this page.) Use the word line (control gate) 1 l0a as a mask, and sequentially etch the ONO film 109 and the polycrystalline silicon film 107a to complete the floating gate. As a result, the polycrystalline silicon film 107a becomes 107b (floating gate), the ONO film 109 becomes 109a, and the silicon oxide film 104a becomes silicon oxide film 104b. Although not shown, after the interlayer insulating film is formed on the silicon substrate ' Form contact holes reaching the word line (control gate) 110a, the source / drain diffusion layer 105, the P-well 101, and the third gate 103a, and then deposit metal and pattern the wirings. And complete the storage unit. The thickness of the gate insulating film 106a between the floating gate 107b and the P-well 101 is larger than that of the gate insulating film 102 between the third gate 103a and the P-well 101. Compared with setting the gate insulating film 106a to the same thickness or smaller than the gate insulating film 102, although the charge retention characteristics of the memory cell after repeated rewriting are the same, the gate length of the third gate is shortened and there is no punch-through. Phenomenon, stable operation can be performed. Moreover, a larger channel current can be obtained, and the reading speed of a non-volatile semiconductor memory device can be improved. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs According to this embodiment, it has the effect of maintaining the reliability of the non-volatile semiconductor memory device after repeated rewriting to reduce the area of the memory cell. It has the effect of increasing the reading speed. (Embodiment 2) Next, the structure, operation method, and manufacturing method of a nonvolatile semiconductor memory device (flash memory) according to Embodiment 2 of the present invention will be described with reference to Figs. 15 to 17. The difference from Embodiment 1, that is, the floating gate 107b and p apply the Chinese National Standard (CNS) A4 specification (210X297 mm) -17- 200301011 A7 B7 V. Description of the invention (1) 1 (Please read the back first (Notes on this page, please fill in this page again) The gate insulation film between the wells 101 is formed, and the thermal oxidation method is replaced by a low pressure chemical vapor growth method (LPCVD: Low Pressure Chemical Vapor Deposition method). The plan view of the main parts of the flash memory, the cross-sectional structure of the completed memory cell, and the structure of the memory array are the same as those of the first embodiment, and are omitted here. The manufacturing method of the memory cell is as follows. First, by the same method as Embodiment 1 described with reference to FIGS. 3 to 6, a P-type well 101, a gate insulating film 102, a third smell electrode 103 a, a sand oxide film 104 a and Source / drain diffusion layer 105 (FIG. 15). Next, as shown in FIG. 16, a llnm separable floating gate and a silicon oxide film 111 with a silicon substrate and a third gate are formed. The formation method is as follows. First, 11 urn silicon oxide film was deposited by low pressure chemical vapor growth method using silane and nitrous oxide as raw materials. Next, the sample was heat-treated in an ammonia atmosphere, and nitrogen was introduced into the silicon oxide film 111. After that, the samples were annealed in wet oxidation. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs The three-step process can reduce trace defects and electronic traps in the silicon oxide film 111. In addition, due to the use of a low-pressure chemical vapor growth method, the thickness of the silicon oxide film 111 deposited on the upper side of the third gate 103a and the silicon oxide film 104a and the sidewalls and the surface of the P-well 101 is almost the same. Therefore, the thickness of the silicon oxide film 111 between the side wall of the third gate 103a and the floating gate 107b is slightly the same as the thickness of the silicon oxide film (gate insulating film) 111 between the floating gate 107b and the P-well 101 (see FIG. 17). ). Then, as shown in FIG. 17, the paper size is applied in accordance with the Chinese National Standard (CNS) A4 specification (210 > < 297 mm) -18- 200301011 • A7 B7 V. Description of the invention (Same way 1 is to form floating gate 107b, ONO film 109a and word line (control gate) 11 0a to complete the memory cell. (please first (Please read the notes on the back and fill in this page again.) The memory cell formed by this embodiment is the same as that in Embodiment 1. Although the gate length of the third gate is reduced, it will not penetrate and can be used for stable operation. In addition, the channel can be increased The current increases the reading speed of the non-volatile semiconductor memory device. In addition, compared with Embodiment 1, this embodiment can reduce the thickness of the insulating film between the floating gate 107b and the third gate 103a sidewall. Therefore, by setting the selected word line to about 13V, the third gate to about 3V, and the source / drain and sink to 0V, and performing an erasing operation, an electronic discharge can be performed from the floating gate to the third gate. Compared with the first embodiment, the internal operating voltage can be reduced to reduce the area of the peripheral circuit area. According to this embodiment, the reliability of the nonvolatile semiconductor memory device after rewriting can be maintained to reduce the memory cell. It has the effect of increasing the reading speed. It also has the effect of reducing the internal operating voltage. It is printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs (Embodiment 3) This embodiment is different from the embodiment. 1 and 2 apply the present invention to a split-gate memory cell without a third gate. Regarding the structure, operation method, and method of a nonvolatile semiconductor memory device (flash memory) according to Embodiment 3 of the present invention, and The manufacturing method will be described with reference to FIGS. 18 to 25. First, the structure of the flash memory cell will be described. As shown in FIG. 25, the source memory 209 and the drain electrode in the P-type well 201 formed by the # memory cell 200 are formed by a silicon substrate 200. This paper size applies Chinese National Standard (CNS) A4 specification (210X297mm) -19- 200301011 A7 B7 V. Description of the invention (207, floating gate 203a, control gate 205a. (Please read the precautions on the back before (Fill in this page) Floating gate 203a and P-well 201 are separated by insulating film 204a, while floating gate 203a and control gate 205a are separated by insulating film 204b. Control gate 205a — part of the channel that overlaps the silicon substrate section, The remaining part also overlaps the top of the floating gate 203a. The source 209 and the drain 207 overlap the control gate 205a and the floating noise 203a through the gate insulating film 204a or 202, respectively. In the case of this storage unit, the control A so-called split-gate memory cell in which the transistor controlled by the gate 205a and the transistor controlled by the floating gate 203a are connected in series. When writing, about 2V is applied to the control gate 205a, 12V is applied to the drain 207, and the P-type The well 201 and the source electrode 209 are maintained at 0 V. As a result, thermionic electrons are generated at the source-side end channel of the floating gate 203a, and electrons are injected into the floating gate 203a. A voltage of 12V is applied to the control gate 205a so as not to deteriorate the gate insulating film 204a, for example, 4V, and the source 209 and the P-well 201 are maintained at 0V. As a result, the electrons accumulated in the floating news 203a due to the tunnel phenomenon are discharged to the drain electrode 207. The reasons for adopting such a elimination method are explained below. That is, as described later, since the thickness of the gate insulating film 204a between the control gate 205a and the P-well 201 is made thin, a high voltage cannot be applied to these spaces, and the voltage applied to the control gate 205a needs to be applied. Suppressed to about 4V. Therefore, in the elimination, the elimination method of applying a high potential (12V) to the drain 207 side and pulling the electrons on the drain 207 side cannot be adopted. This paper size applies Chinese National Standard (CNS) A4 specification (210X297mm) -20- 200301011 A7 B7 V. Description of invention ((Please read the precautions on the back before filling this page) The storage unit of this implementation mode is also different The gate insulation film 202 between the floating gate 203a and the P-type well 201 is thicker than the control gate insulation film 205a and the P-type well 201. The film 204a is large. By setting the film thickness of the tunnel insulation film to be large, it is possible to suppress the charge retention failure caused by the sudden leakage of electrons accumulated in the floating gate to the substrate due to the floating gate. Also, by controlling the gate electrode 205a, By thinning the gate insulating film 204a, the punch-through resistance of the MOS transistor formed by the control gate 205a can be improved, and the gate length of the control gate 205a can be shortened. Therefore, high reliability and miniaturization of the memory cell can be achieved. In addition, the channel current can be increased and the reading speed of the memory cell can be improved. Second, use Figure 18 to Figure 25 to show the manufacturing method of this memory cell. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, such as As shown in FIG. 18, after a P-type well 201 is formed on a silicon substrate 200, a 9nm gate insulating film 202 that separates the floating gate and the well is formed by a known thermal oxidation method, and then a polycrystalline silicon film that can become a floating gate and is mixed with phosphorus is deposited. 203. Next, as shown in FIG. 19, the above-mentioned polycrystalline silicon film 203 is patterned using a well-known lithography and dry etching technique. As a result, the polycrystalline silicon film 203 becomes 203a (floating gate). Further, as shown in FIG. After patterning the gate insulating film 202, a 7.5 nm thermal oxide film (gate insulating film) 204a capable of separating and controlling the gate and the substrate is formed on the silicon substrate by a known thermal oxidation method. At this time, the floating gate 203a A thermal oxide film 204b of about 20 nm is formed on the side wall and the top, which can separate the floating gate and the control gate. The film thickness of the thermal oxide film 204b is thicker than that of 204a. This paper size applies the Chinese National Standard (CNS) A4 specification ( 210X297 mm)-21-200301011 A7 B7 V. Description of the invention (Phosphorus is mixed in polycrystalline silicon film of one household which is the material of floating gate 203a, which will cause accelerated oxidation due to the phosphorus. (Please read the note on the back first) (Please fill in this page again) 'As shown in FIG. 21, a so-called polymer film 205, which is a laminated film of a polycrystalline sand film and a tungsten silicide film, which can be used as a floating gate, is stacked. As shown in FIG. 22, it is known as lithography. The polymer film 205 is patterned with a dry etching technique. As a result, the polymer film 205 becomes 205a (control gate). As shown in the figure, the control gate 205a extends from the polycrystalline silicon film 203a to the silicon substrate (from the center). p-well 201). Then, as shown in FIG. 23, a photoresist pattern 206 is formed on the silicon substrate, and phosphorus ions are implanted by an ion implantation method to perform heat treatment to form a drain region 207 of the memory cell. Next, as shown in FIG. 24, a photoresist pattern 208 is formed, and arsenic ions are implanted by ion implantation to form a source region 209 of the memory cell. The photoresist pattern 208 is removed (FIG. 25). After that, although not shown, after forming an interlayer insulating film on a silicon substrate, contact holes reaching the control gate 205a, the source region 209, the drain region 207, and the P-well 201 are formed, and then a metal film is deposited and deposited. The patterning is set as wiring to complete the memory cell. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs has printed the gate insulating film 202 between the floating gate 203a and the P-well 201 to have a larger film thickness than the gate insulating film 204a between the control gate 205a and the P-well 201. Compared with setting the gate insulating film 202 to the same thickness or smaller as the gate insulating film 204a, the memory cell has the same charge retention characteristics of the memory cell after repeated rewriting, but shortens the gate length of the control gate 205a. There is no punch-through phenomenon, and stable operation can be performed. Moreover, a larger channel current can be obtained. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -22- 200301011 A7 B7 V. Description of the invention (also improves the reading speed of non-volatile semiconductor memory devices (Please read the precautions on the back before filling out this page) If this embodiment is used, it can maintain the non-volatile semiconductor memory. The reliability of the memory device after rewriting is reduced to reduce the area of the memory cell. (Embodiment 4) In the present embodiment, the present invention is applied to a split gate type memory cell having a third gate and having a gate erased. The following uses FIG. 26 to FIG. 33 to The structure, operation method, and manufacturing method of the nonvolatile semiconductor memory device (flash memory) according to the fourth embodiment of the present invention will be described. First, the structure of the flash memory will be described. As shown in FIG. 32 and FIG. 32, X-X1 spring As shown in FIG. 33 in the cross section, this memory cell is controlled by a source / drain diffusion layer 303, a first gate floating gate 305b, and a second gate formed in a P-type well 301 formed on the main surface of a sand substrate 300. Gate 30 7a, and the third gate is made up of the elimination gate (third gate) 309a. The control gate 307a of each storage unit printed by the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is connected to the row direction and forms a word line. Floating gate 305b and P-type well 301 are formed by gate insulating film 304a, floating gate 305b and word line (control gate) 307a are formed by insulating film 306b, and gate 309a and word line (control gate) 307a are formed by insulating film 308 Separate them separately. Also, as shown in FIG. 33, the floating gate 305b and the erasing gate 309a are separated by an insulating film 311. The erasing gate 309a and the P-type well 301 are also separated by an insulating film 312. The insulating film 3 and 12 are buried in the P-well 301. The source / drain diffusion layer 303 is a local source line and a local paper which are vertically arranged on the word line (control gate) 307a 'to connect the source / drain of the column-direction memory cell. The dimensions apply to the Chinese National Standard (CNS) A4 specification (210X297 mm) -23- 200301011 A7 B7 V. Description of the invention (2) 3 (Please read the notes on the back before filling this page) The data line exists. That is, The non-volatile semiconductor memory device is not connected by each storage unit. The so-called non-contact array of holes is formed. A channel is formed in the vertical direction of the source / drain diffusion layer 303. When writing, about 12V is applied to the control gate 307a, and 4V is applied to the drain (303). The P-well 301 and the source electrode (303) are maintained at 0 V. As a result, thermal electrons are generated in the channel at the drain end, and electrons are injected into the floating gate 305b. When erasing, apply approximately 12 V to the erasing gate 309a to control the gate. The electrode 307a, the source (303), and the P-well 301 are maintained at 0V. As a result, the electrons accumulated in the floating gate 305b are released to the elimination gate 309a due to the tunnel phenomenon. In this embodiment, it is also different from the memory cell shown in FIG. 60. The gate between the floating gate 305b and the P-well 301 is The film thickness of the insulating film 304a and the so-called tunnel insulating film is larger than the gate insulating film 306a between the control gate 307a and the P-well 301. If the thickness of the tunnel insulating film 304a is made large, it is possible to suppress the charge retention failure caused by the sudden leakage of electrons accumulated in the floating gate to the substrate at a specific bit. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and by thinning the gate insulating film 306a of the control gate 307a, the punch-through resistance of the MOS transistor formed by the control gate 307a is improved, and the control gate can be shortened. Gate length of pole 307a. Therefore, it is possible to achieve high reliability and miniaturization of the memory cell. It can also increase the channel current during reading to improve the reading speed of the memory unit. Second, use Figure 26 to Figure 33 to show the manufacturing method of this memory unit. The paper size applies the Chinese National Standard (CNS) A4 specification ( 210x297 mm) -24- 200301011 A7 B7 Main and invention description (λ 〇 (Please read the notes on the back before filling in this page) First, as shown in FIG. 26, form a P-well 301 on the silicon substrate 300. Then As shown in FIG. 27, after a thin oxide film 302 is formed on the surface of the silicon substrate 300 (P-well 301), arsenic ions are implanted by ion implantation to form a diffusion layer 303 that becomes a source / drain of a memory cell. Next, as shown in FIG. 28, a 9nm gate insulating film 304 capable of separating the floating gate and the well, and a polycrystalline silicon film 305 that becomes a floating gate, is formed sequentially by a known thermal oxidation method. Next, as shown in FIG. 29 The polycrystalline silicon film 305 and the gate insulating film 304 are patterned by well-known lithography and dry etching techniques. As a result, the polycrystalline silicon film 305 becomes 305a, and the gate insulating film 304 becomes 304a. Intellectual Property Bureau, Ministry of Economic Affairs Employee spending Then, as shown in FIG. 30, a 7 nm thermal oxide film 306a is formed on the silicon substrate (P-well 301) by a known thermal oxidation method to separate the control gate from the substrate. At this time, on the sidewall of the polycrystalline silicon film 305a And the top surface forms a thermal oxide film 306b of about 20nm, which can separate the floating gate and the control gate. The film thickness of the thermal oxide film 306b is thicker than that of 3 0 6 a, but it is a polycrystalline sand film with a material of 3 0 5 b. Phosphorus is mixed in 3 0 5a, which is caused by accelerated oxidation due to the phosphorus. * Next, as shown in FIG. 31, a polycrystalline silicon film 307 is deposited, and this is patterned by a well-known lithography and dry etching technique. The word line (control gate) is formed. As a result, the polysilicon film 307 becomes 307a (word line, control gate) (see FIG. 33). The word line (control gate) 307a is sequentially used as a mask. The thermal oxide film 306b and polycrystalline silicon film 305a are etched to complete the floating gate. That is, the paper is thermally oxidized to the Chinese National Standard (CNS) A4 specification (210X297 mm) -25- 200301011 A7 ___ B7__ 5. Description of the invention (2) 2 film 3 06b becomes 306b, and polycrystalline silicon film 305a becomes 305b (floating gate) ( (Refer to Figure 33). (Please read the precautions on the back before filling in this page.) Then, as shown in Figure 32, an insulation pattern of a separable control gate and erasing gate and a separable floating gate and erasing gate is formed in sequence. 308, 3 11 and the polymer film (309), and patterning the polymer film (309) to form an erase gate 309a (see FIG. 33). After that, although not shown, after forming an interlayer insulating film on a silicon substrate , Forming a contact hole that reaches the word line (control gate) 307a, source / drain diffusion layer 303, P-well 301, and elimination gate 309a, and then deposits a metal film, patterning it into wiring, and the completion Storage unit. The thickness of the gate insulating film 304a between the floating gate 305b and the P-well 301 is set to be larger than that of the gate insulating film 306a between the control gate 307a and the P-well 301. The film thickness of the insulating film 304a is set to be the same as or smaller than that of the gate insulating film 306a. Although the charge retention characteristics of the memory cells after repeated rewriting are the same, the gate length of the control gate is shortened and there is no punch-through phenomenon, and stable operation can be performed. . Moreover, a larger channel current can be obtained, and the reading speed of a non-volatile semiconductor memory device can be improved. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs According to this embodiment, it has the effect of maintaining the reliability of the non-volatile semiconductor memory device after repeated rewriting to reduce the area of the memory cell. It has the effect of increasing the reading speed. In this embodiment, although the gate insulating film 304 that can separate the floating gate and the P-well is formed by a thermal oxidation method, it is formed by a low-pressure chemical vapor growth method in the same manner as in Embodiment 2, or it is added by using Nitrogen oxide film can also achieve the same effect. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -26- 200301011 A7 B7 V. Description of the invention (light (Embodiment 5) (Please read the precautions on the back before filling this page) In this implementation Form, that is, the gate insulating film of a memory cell of a non-volatile semiconductor memory device is formed at the same time as the gate insulating film of a low-voltage system MOS transistor, and it will be described using an example in which the manufacturing process is simplified. Use FIG. 34 to FIG. 46, the structure and manufacturing method of the non-volatile semiconductor memory device according to Embodiment 5 of the present invention will be described. As shown in FIG. 46, the non-volatile semiconductor memory device consists of a plurality of memory cells required for storing information in a matrix. The memory cell field is composed of a peripheral circuit field where a large number of peripheral circuit configuration MOS transistors (MISFETs) can be selected for rewriting or reading the required bits or generating the required voltage inside the chip. The circuit field can be divided into, for example, a low-voltage part to which only a small voltage such as 3.3 V is applied, and a high voltage required to be rewritten such as 18 V. High-voltage department. The printed low-voltage and high-voltage sections of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs are shown in Figure 46. Most of the NMOS transistors (Qnl) are formed on the P-wells 404b and 404c and the N-wells 405a and 405b. , Qn2) and PMOS transistors (Qpl, QP2). The memory cells formed in the memory cell field are the flash memory banks described in Embodiment 1, and are formed on the P-well 404a. Figures 34 to 46 are parallel A cross-sectional view of the word line (control gate 415a) of the memory cell and perpendicular to the word line (409c) of the peripheral circuit MOS transistor. Secondly, the non-volatile semiconductor memory shown in FIG. 34 to FIG. 46 is applicable to this paper. China National Standard (CNS) A4 specification (210X29? Mm) -27- 200301011 A7 B7__ 5. Description of invention (mandatory device manufacturing method. (Please read the precautions on the back before filling this page) First, as shown in Figure 34 As shown, a p-type Si substrate 401 with a plane orientation of (100) forms a shallow trench element separation region 402 that can separate each memory cell and peripheral circuit MOS transistors. Then, P-well regions 404a, 404b, and 404c are formed by ion implantation. , And N-well The domains 405a and 405b further form a separation region 403 between wells. Next, as shown in FIG. 35, a silicon oxide film 406 of about 23 nm which can be a gate insulating mode for the high-voltage part in the peripheral circuit field is formed by a thermal oxidation method. As shown in FIG. 36, a photoresist pattern 407 is formed, and the silicon oxide film 406 is left only in the high-voltage part of the peripheral circuit area by wet uranium etching. As a result, the silicon oxide film 406 becomes 406a. Then, as shown in FIG. As shown in FIG. 37, in the low-voltage part of the peripheral circuit field and the memory cell field by the thermal oxidation method, a gate insulating film that can be a peripheral MOS transistor and an insulating film that can separate the third gate and the well of the memory cell are formed. Thermal oxidation film 408. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs At this time, the thermal oxidation film thickness of the high-voltage part in the peripheral circuit area is 25nm. That is, the thickness of the silicon oxide film 406a is increased to become 406b (gate insulation film of the high-voltage portion). Then, as shown in FIG. 38, a polycrystalline silicon film 409 and a silicon oxide film 410 serving as electrodes of the peripheral MOS transistor and the third gate of the memory cell are sequentially deposited on the p-type Si substrate 401. Next, as shown in FIG. 39, the lithographic oxide film 41 0 and the polycrystalline sand film 409 were patterned using lithography and dry etching techniques. As a result, the silicon oxide film 410 and the polycrystalline silicon film 409 in the field of storage units have been changed to 410a. The paper size applies the Chinese National Standard (CNS) A4 specification (210x297 mm) ~ " • 28- 00 2 i ic 1c c

7 B Printed by jOTmrrt, a consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs --- --- 5. Description of the invention (2 $ and 409a. At this time, the silicon oxide film 410 and the polycrystalline silicon film 409 in the peripheral circuit field are not etched by uranium, but are presented The remaining patterns of 410b and 409b are arranged. Then, the same oblique implantation as in Embodiment 1 is performed to form the source / drain diffusion layer region 411 of the memory cell. Next, as shown in FIG. 40, it is the same as Embodiment 1. An insulating film 412 that can separate the floating gate from the well and between the floating gate and the third gate is formed by thermal oxidation. At this time, the thickness of the oxide film on the well is set to 7.5 nm. Then, as shown in FIG. 41, the stack becomes The polycrystalline silicon film 413 of the floating gate is processed by the repeated etching method using the fluid organic material described in Embodiment 1. As a result, the polycrystalline silicon film 413 becomes 413a (FIG. 43). Next, as shown in FIG. 43 It can be shown that the sequential stacking can become a laminated film of silicon oxide film / silicon nitride film / silicon oxide film that can separate the floating gate and the word line, a so-called 0N0 film 414, and a polymer film 415 that becomes a word line. Next, as shown in the figure As shown in 44, it is known for its lithography and intervention The engraving technique performs pattern formation to form a word line (control gate). As a result, the polymer film 415 becomes 415a (word line). The word line 415a is used as a mask to process the ON0 film 414 and the polycrystalline silicon film 413a. The floating gate is completed. That is, the ON0 film 414 and the polycrystalline silicon film 413a become 414a and 413b (floating orchid), respectively. After that, as shown in FIG. 45, the silicon oxide film of the peripheral circuit portion is lithographically and dry-etched. 410b and 409b are patterned to form the gate electrode of the peripheral circuit MOS transistor. That is, the silicon oxide films 410b and 409b become 410c and 409c (gate electrode, gate line), respectively. -------- HP -Installation-(Please read the notes on the back before filling this page) The size of the paper used in this edition applies to the Chinese National Standard (CNS) A4 (210X297 mm) -29- 200301011 A7 B7 V. Description of the Invention (Each time, As shown in Figure 46, the source / drain regions 416a, 416b, 417a, and 417b of the peripheral circuit MOS transistor are formed by the ion implantation method. (Please read the precautions on the back before filling this page) After the interlayer insulating film is deposited on the Si substrate, The insulating film forms a contact hole reaching the word line 415a, the gate electrode 410c of the surrounding MOS transistor (Qnl, Qn2, Qpl, Qp2), and the source / drain region (416a, 416b, 417a, 417b). After the film is processed into an electrode, a non-volatile semiconductor memory device is completed. In this embodiment, the gate insulating film 408 of the third gate of the memory cell and the gate insulating film of the MOS transistor of the low voltage portion of the peripheral circuit 408, but formed by the exact same project. Therefore, the four gate insulating films including the tunnel insulating film of the memory cell can be formed of three films. Therefore, it is possible to reduce the number of manufacturing processes as compared to forming the gate insulating films individually. As described in the first embodiment, by forming the gate insulating film 408 of the third gate to be thinner than the insulating film 412, the memory cell can be miniaturized and reliability can be ensured. Moreover, the reading speed of the graph memory unit is improved. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (Embodiment 6) In this embodiment, the gate insulating film of the storage unit of the non-volatile semiconductor memory device is simultaneously with the gate insulating film of the MOS transistor in the peripheral circuit of the low-voltage system. The formation will be explained by another example that the manufacturing process is simplified. The difference from Embodiment 5 is that the gate insulating film of the MOS transistor in the peripheral circuit of the low-voltage system, the gate insulating film between the floating gate and the well of the memory cell, and the so-called tunnel insulating film are formed in common. Figures 47 to 59 are used in this paper. The paper dimensions are applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -30- 200301011 A7 B7 V. Description of the invention (Part 'Describes the non-volatile semiconductor memory device of Embodiment 6 of the present invention (Please read the precautions on the back before filling out this page.) As shown in Figure 59, this non-volatile semiconductor memory device is a memory cell in which most of the memory cells required for information storage are arranged in rows and columns. The field is composed of a peripheral circuit field with a MOS transistor, which is configured with a number of bits that can be selected to perform rewriting or reading, or to generate a required voltage inside the chip. The peripheral circuit field can be divided into, For example, a low-voltage part to which only a small voltage such as a 3.3 V power supply voltage is applied, and a high-voltage part to which a high voltage required for rewriting such as 18 V is applied. Both the low-voltage part and the high-voltage part are shown in FIG. 59 As shown, it is composed of a plurality of NMOS transistors (Qnl, Qn2) and PMOS transistors (Qpl, QP2) formed on the P wells 504b, 504c and the N wells 505a, 505b. The memory cells formed in the field of memory cells, namely The flash memory bank described in Embodiment 1 is formed on the P-well 504a. Figure 47 to Figure 59 are parallel to the word line (516a) of the memory cell and perpendicular to the gate line (5 13c) of the MOS transistor of the peripheral circuit. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Next, the manufacturing method of the present non-volatile semiconductor memory device is shown using FIG. 47 to FIG. 59. First, as shown in FIG. The type Si substrate 401 forms a shallow trench element separation area 502 that can separate each memory cell and a peripheral circuit MOS transistor. Next, P-well areas 504a, 504b, and 504c, and N-well areas 505a, 505b, and more are formed by an ion implantation method. Formation of separation fields between wells 503. This paper size is applicable to Chinese National Standard (CNS) A4 (2H) X297 mm) -31-200301011 A7 B7 V. Description of the invention (Next, as shown in Figure 48, thermal oxidation method Form a 7.5nm silicon oxide film 506 that can be used as the third gate insulator of the memory cell. (Please read the precautions on the back before filling out this page} Then, as shown in Figure 49, it can be stacked in order to become a peripheral MOS. Transistor and storage The polycrystalline silicon film 507 and the silicon nitride film 508 of the third gate electrode of the storage cell. Next, as shown in FIG. 50, the polycrystalline silicon film 507 and the silicon nitride film 508 are patterned by using lithography and dry etching techniques. As a result, the polycrystalline silicon film 507 and the silicon nitride film 508 are changed to 508a and 508a, respectively. At this time, the silicon nitride film 508 and the polycrystalline silicon film 507 in the peripheral circuit area are etched and removed. Then, the same tilt as in the first embodiment is performed. To the source / drain diffusion layer region 509 of the memory cell. Next, as shown in FIG. 51, a 23 nm sand nitride film 5 10 can be formed on a P-type Si substrate by a combination of a thermal oxidation method and a CVD method, which can be used as a gate insulating film for a high-voltage portion in a peripheral circuit field. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Next, as shown in FIG. 52, a photoresist pattern 5 11 is formed, and the silicon oxide film 510 is retained only by the high-voltage portion of the peripheral circuit area by wet etching. As a result, the silicon oxide film 510 becomes 510a. Next, as shown in FIG. 53, the gate insulating film of the low-voltage portion of the peripheral circuit area of 9 nm is formed by a thermal oxidation method, and the floating gate and the well, and the floating gate and the third gate which can separate the memory cell can be separated. The insulating film 5 1 2 0 of the insulating film At this time, the thickness of the thermal oxidation film of the local voltage part of the peripheral circuit area is 25 nm. That is, the silicon oxide film 510a becomes 510b (gate insulation film). This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -32- 200301011 A7 B7 V. Invention Description (2) (Please read the precautions on the back before filling this page) Then, as shown in Figure 54 After stacking the polycrystalline silicon film 5 1 3 which can become a floating gate, the silicon oxide film 5 14 is deposited, and the silicon oxide film 514 is left in the peripheral circuit field by using lithography and dry etching technology (Figure 55). As shown in FIG. 56, the polycrystalline silicon film 5 1 3 is processed by the repeated etching method using a flowable organic material shown in Embodiment 1 as a mask. As a result, the polycrystalline silicon film 513 becomes 513a. Then, wet etching is performed. The silicon oxide film 5 is removed by method 14. The polycrystalline silicon film exposed in the peripheral circuit area is 513b. Next, as shown in FIG. 57, a silicon oxide film / silicon nitride that can separate the floating gate and the word line is sequentially deposited on the Si substrate. Film / silicon film laminated film, so-called ONO film 515, and polymer film 516 which can be word lines. Next, as shown in FIG. 58, it is patterned by well-known lithography and dry etching techniques. Formation of word lines (control That is, the polymer film 516 becomes 516a (word line). Furthermore, the ONO film 5 1 5 and the polycrystalline silicon film pattern are processed with the word line 516a as a mask, and the floating gate is completed. That is, ON 〇The film 515 and the polycrystalline silicon film 513a become 515a and 51 3b (floating gates) respectively. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, this also forms peripheral MOS transistors. That is, polymer films 516 and 0N0 in the field of peripheral circuits. The film 515 and the polycrystalline silicon film 513b become 516b, 515b, and 513c, respectively. Next, as shown in FIG. 59, the source / drain regions 517a, 517b, 518a, and 518b of the MOS transistor of the peripheral circuit are formed by ion implantation. Then, although not shown, after the interlayer insulating film is deposited on the Si substrate, a word line (control gate), a gate electrode 5 1 3c of a peripheral MOS transistor, and a source / drain are formed on the interlayer insulating film. The contact holes in the field are stacked again. The paper size is applicable to the National Standard (CNS) A4 specification (210X 297 mm) -33- 200301011 A7 B7_________ 5. Description of the invention (3jb metal film, which is processed into an electrode and completed Non-volatile semiconductor memory device In this embodiment, the gate insulating film 512 of the floating gate of the memory cell and the gate insulating film 512 of the MOS transistor of the low-voltage portion of the peripheral circuit are formed by exactly the same process. Therefore, as in the fifth embodiment, the storage The four types of gate insulation films including the tunnel insulation film of the unit can be formed by three types of films. Therefore, 'the number of manufacturing processes can be reduced compared to forming each of the gate insulation films individually.' As in the first embodiment, the first The gate insulating film 506 of the three gates is formed thinner than the gate insulating film 512 of the floating gate, so that the miniaturization of the memory cell and the reliability of the reliability can be achieved. In addition, the reading speed of the graph memory unit is improved. In Embodiments 1 to 6, although an n-channel memory cell in which a n-type diffusion layer is formed in a p-type well is described as an example, a p-channel memory cell in which the well is an n-type and the diffusion layer is p-type The same effect can be obtained. In Embodiments 1 to 6, although the third gate electrode of the memory cell or the gate insulating film controlling the gate electrode is described by taking a thermal oxide film as an example, a film containing a silicon nitride film or a high permittivity is used. Materials, it can shorten the gate length or increase the reading current. Moreover, in any embodiment, although the state of the electrons accumulated in the floating gate needs to be at least two states at the time of writing, a level of more than four states is formed, and a so-called multi-level memory suitable for a memory cell to store more than two bits of data is also can. For general multi-memory storage, although the accumulated electron quantity of the floating gate is controlled with high precision to compress and compress the threshold distribution of each level, it has the lowest paper size than double-memory storage—Zhongguanjia Standard (CNS) Α4 specification (210 × 297 mm) " '--34-(Please read the precautions on the back before filling this page) Pack-Order Printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs 200301011 A7 B7

V. Description of the Invention (A large difference between the threshold state and the highest threshold state. Therefore, the rewriting speed of the FN (Flwer-Nordheim) tunneling type will be slower (please read the precautions on the back before filling in This page) or the problem of high write voltage. However, according to the present invention, since writing and erasing can be reduced to about 13V, in other words, the speed of writing can be increased, it is extremely effective for multi-memory. Although the invention created by the present inventors will be specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and can be changed as long as it does not deviate from the gist thereof. For example, the present invention can also be applied to A monolithic microcomputer (semiconductor device) having a storage unit including a nonvolatile semiconductor memory and device. Effects of the Invention In the invention disclosed in this case, the effects obtained by a representative person are briefly explained, but they are as follows. The gate insulating film between the floating gate and the substrate (well) is formed to be thicker than the gate insulating film between the third gate or the control gate and the substrate. Memory area of small non-volatile semiconductor memory devices. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, it can improve the reliability of non-volatile semiconductor memory devices after rewriting. 'Furthermore, non-volatile semiconductor memory can be sought. The operating speed of the device is improved. Also, the gate insulating film between the floating gate and the substrate, or the gate insulating film between the third gate and the substrate is the same as the gate insulating film of the MOS transistor in the low-voltage part of the peripheral circuit. The project is formed, so it is possible to plan the non-volatile semi-paper size to apply the Chinese National Standard (CNS) A4 specification (210X297 mm) -35- 200301011 A7 B7__ 5. Description of the invention (The manufacturing process of the conductor memory device is simplified. Please read the precautions on the back before filling this page.) Brief description of the diagram. Figure 1 is a plan view of the main part of a substrate showing a non-volatile semiconductor memory device (flash memory) according to Embodiment 1 of the present invention. An array configuration circuit diagram of a nonvolatile semiconductor memory device according to a first embodiment of the present invention. Fig. 3 shows a nonvolatile semiconductor memory device according to the first embodiment of the present invention. Sectional view of main parts of a substrate for a method of manufacturing a conductive memory device. Fig. 4 is a cross-sectional view of main parts of a substrate showing a method for manufacturing a nonvolatile semiconductor memory device according to Embodiment 1 of the present invention. Sectional view of main parts of a substrate for a method of manufacturing a semiconductor memory device. Fig. 6 is a cross-sectional view of main parts of a substrate showing a method for manufacturing a nonvolatile semiconductor memory device according to Embodiment 1 of the present invention. Cross-sectional view of a main part of a substrate for a method of manufacturing a semiconductor memory device. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs FIG. 8 is a cross-sectional view of a main part of a substrate showing a non-volatile semiconductor memory device manufacturing method according to Embodiment 1 of the present invention. A cross-sectional view of a main part of a substrate showing a method for manufacturing a nonvolatile semiconductor memory device according to the first embodiment of the present invention. Fig. 10 is a sectional view of a main part of a substrate showing a method for manufacturing a nonvolatile semiconductor memory device according to the first embodiment of the present invention. FIG. 11 shows that the paper size of the non-volatile semiconductor memory according to Embodiment 1 of the present invention applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -36- 200301011 A7 ___B7_ V. Description of the invention (3) 3 Device manufacturing method Sectional view of main parts of the substrate. (Please read the precautions on the back before filling out this page.) Figure 12 is a cross-sectional view of a main part of a substrate showing a method for manufacturing a nonvolatile semiconductor memory device according to the first embodiment of the present invention. Fig. 13 is a sectional view of a main part of a substrate showing a method for manufacturing a nonvolatile semiconductor memory device according to the first embodiment of the present invention. Fig. 14 is a sectional view of a main portion of a substrate of a nonvolatile semiconductor memory device according to the first embodiment of the present invention. Fig. 15 is a sectional view of a main part of a substrate showing a method for manufacturing a nonvolatile semiconductor memory device according to a second embodiment of the present invention. Fig. 16 is a sectional view of a main part of a substrate showing a method for manufacturing a nonvolatile semiconductor memory device according to a second embodiment of the present invention. Fig. 17 is a sectional view of a main portion of a substrate of a nonvolatile semiconductor memory device according to a second embodiment of the present invention. Fig. 18 is a sectional view of a main part of a substrate showing a method for manufacturing a nonvolatile semiconductor memory device according to a third embodiment of the present invention. Fig. 19 is a sectional view of a main part of a substrate showing a method for manufacturing a nonvolatile semiconductor memory device according to a third embodiment of the present invention. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs Fig. 20 is a sectional view of a main part of a substrate showing a method for manufacturing a nonvolatile semiconductor memory device according to a third embodiment of the present invention. Fig. 21 is a sectional view of a main part of a substrate showing a method for manufacturing a nonvolatile semiconductor memory device according to a third embodiment of the present invention. Fig. 22 is a sectional view of a main part of a substrate showing a method for manufacturing a nonvolatile semiconductor memory device according to a third embodiment of the present invention. FIG. 23 shows the non-volatile semiconductor memory paper according to the third embodiment of the present invention. The paper size is suitable for financial and domestic use (CNS) A4i (210X297 mm) " I'-37- 200301011 A7 B7 5. Description of the invention (Please read the precautions on the back before filling out this page) Figure 24 is a sectional view of the main part of a substrate showing a method for manufacturing a nonvolatile semiconductor memory device according to Embodiment 3 of the present invention. Figure 25 is A cross-sectional view of a main portion of a substrate of a nonvolatile semiconductor memory device according to a third embodiment of the present invention. Fig. 26 is a cross-sectional view of a main portion of a substrate showing a method of manufacturing a non-volatile semiconductor memory device according to a fourth embodiment of the present invention. Sectional view of main parts of a substrate for a method of manufacturing a nonvolatile semiconductor memory device according to a fourth embodiment of the invention. Fig. 28 is a cross-sectional view of main parts of a substrate showing a method for manufacturing a nonvolatile semiconductor memory device according to a fourth embodiment of the invention. Sectional view of a main part of a substrate of a method for manufacturing a nonvolatile semiconductor memory device according to a fourth embodiment of the present invention. Fig. 30 shows a nonvolatile semiconductor device according to the fourth embodiment of the present invention. Sectional view of a main part of a substrate for a memory device manufacturing method. Fig. 31 is a cross-sectional view of a main part of a substrate showing a non-volatile semiconductor memory device manufacturing method according to a fourth embodiment of the present invention. Sectional view of a main part of a substrate of a nonvolatile semiconductor memory device according to a fourth embodiment of the present invention. Fig. 33 is a cross-sectional view of a main part of a substrate of a nonvolatile semiconductor memory device according to the fourth embodiment of the present invention. Fig. 34 is a view showing the present invention. Sectional view of main parts of a substrate for a method for manufacturing a nonvolatile semiconductor memory device according to Embodiment 5. FIG. 35 is a diagram showing a nonvolatile semiconductor memory according to Embodiment 5 of the present invention. The paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297). (Mm) -38-200301011 A7 B7 V. Description of the Invention (Cross-section view of the main part of the substrate of the device manufacturing method. _36 is a cross-sectional view of the main part of the substrate showing the non-volatile semiconductor memory device manufacturing method according to the fifth embodiment of the present invention. 37 is a sectional view of a main part of a substrate showing a method for manufacturing a nonvolatile semiconductor memory device according to Embodiment 5 of the present invention. 38 is a sectional view of a main part of a substrate showing a method for manufacturing a nonvolatile semiconductor memory device according to a fifth embodiment of the present invention. FIG. 39 is a sectional view of a main part of a substrate showing a method for manufacturing a nonvolatile semiconductor memory device according to the fifth embodiment of the present invention. 40 is a sectional view of a main part of a substrate showing a method for manufacturing a nonvolatile semiconductor memory device according to a fifth embodiment of the present invention. FIG. 41 is a sectional view of a main part of a substrate showing a method for manufacturing a nonvolatile semiconductor memory device according to the fifth embodiment of the present invention. 42 is a sectional view of a main part of a substrate showing a method for manufacturing a nonvolatile semiconductor memory device according to a fifth embodiment of the present invention. FIG. 43 is a sectional view of a main part of a substrate showing a method for manufacturing a nonvolatile semiconductor memory device according to the fifth embodiment of the present invention. Fig. 44 is a sectional view of a main part of a substrate showing a method for manufacturing a nonvolatile semiconductor memory device according to a fifth embodiment of the present invention. Fig. 45 is a sectional view of a main part of a substrate showing a method for manufacturing a nonvolatile semiconductor memory device according to a fifth embodiment of the present invention. Fig. 46 is a sectional view of a main portion of a substrate of a nonvolatile semiconductor memory device according to a fifth embodiment of the present invention. FIG. 47 shows the non-volatile semiconductor memory according to Embodiment 6 of the present invention. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -------- 0 ^ ---- (Please read the back (Please fill in this page again)

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs-39- 200301011 A7 B7 V. Description of the invention (3 ^ Sectional view of the main part of the substrate of the device manufacturing method. FIG. 48 is a nonvolatile semiconductor memory showing Embodiment 6 of the present invention Sectional view of a main part of a substrate for a device manufacturing method. Fig. 49 is a cross-sectional view of a main part of a substrate showing a method for manufacturing a nonvolatile semiconductor memory device according to a sixth embodiment of the present invention. Fig. 50 is a non-volatile semiconductor memory showing a sixth embodiment of the present invention. Sectional view of a main part of a substrate for a device manufacturing method. Fig. 51 is a cross-sectional view of a main part of a substrate showing a non-volatile semiconductor memory device manufacturing method according to a sixth embodiment of the present invention. Fig. 52 is a non-volatile semiconductor showing a sixth embodiment of the present invention. Sectional view of a main part of a substrate of a memory device manufacturing method. Fig. 53 is a cross-sectional view of a main part of a substrate showing a non-volatile semiconductor memory device manufacturing method according to a sixth embodiment of the present invention. Fig. 54 is a non-volatile semiconductor showing a sixth embodiment of the present invention. Sectional view of main parts of a substrate for a memory device manufacturing method. Fig. 55 is a non-volatile semiconductor device showing a sixth embodiment of the present invention. Sectional view of a main part of a substrate of a memory device manufacturing method. Fig. 56 is a cross-sectional view of a main part of a substrate showing a non-volatile semiconductor memory device manufacturing method according to a sixth embodiment of the present invention. Fig. 57 is a non-volatile semiconductor showing a sixth embodiment of the present invention. Sectional view of a main part of a substrate of a memory device manufacturing method. Fig. 58 is a cross-sectional view of a main part of a substrate showing a non-volatile semiconductor memory device manufacturing method according to a sixth embodiment of the present invention. Fig. 59 is a non-volatile semiconductor showing a sixth embodiment of the present invention. The size of this paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page) _Packing and Ordering Printed by the Intellectual Property Bureau of the Ministry of Economy Staff Consumer Cooperatives -40- 200301011 A7 B7 V. Description of the Invention (Cross-section view of the main part of the substrate of the known device. (Please read the precautions on the back before filling out this page) Figure 60 is a cross-sectional view of the main part of the substrate of the non-volatile semiconductor memory device required to show the effect of the present invention. DESCRIPTION OF SYMBOLS 100: silicon substrate, 101: p-type well, 102: gate insulating film, 103: polycrystalline silicon film, 103a: third gate, 104: silicon Film, 104a: silicon oxide film, 104b: silicon oxide film, 105: source / drain diffusion layer, 106a: gate insulating film (tunnel insulating film), 106b: insulating film (thermal oxide film), 107 : Polycrystalline silicon film, 107a: polycrystalline silicon film, 107b: floating gate, 107b: floating gate pattern, 108 organic material, 108a: organic material, 108b: organic material, 109: ONO film, 109a: ONO film ( Insulation film), 110: polymer film, 110a: word line (control gate), 111: silicon oxide film, 200: silicon substrate, printed by the Consumer Cooperatives of Intellectual Property Bureau of the Ministry of Economic Affairs 201: p-well, 202 : Gate insulating film (tunnel insulating film), 203: Polycrystalline silicon film, 203a: Polycrystalline silicon film (floating gate), 204a: Gate insulating film, 204b: Insulating film (thermal oxide film), 205: Polymer film , 205a: control gate, 206: photoresist pattern, 207: drain (drain region), 208: photoresist pattern, 209 source (source region), 300: silicon substrate, 301: p-type well 302: oxide film, 303: source / drain diffusion layer, 304: gate insulating film, 304a: gate insulating film (tunnel insulating film), 305: polycrystalline silicon film , 305a: polycrystalline sand film, 3 0 5 b: floating news, 3 0 6 a: anode insulating film (thermal oxide film), 306b: insulating film (thermal oxide film), 307: polycrystalline silicon film, 307a: word line (Control gate), 308 ·· Insulation film, 309: Polymer film, 309a: Elimination gate, 311: Insulation film, 312: Insulation film, 401: p-type Si substrate, 402: This paper size applies to Chinese national standards (CNS) A4 specification (210X297 mm) -41-200301011 A7 B7 V. Description of the invention (▲ (Please read the notes on the back before filling this page) '' Component separation field, 403: separation field, 404a: p , 404b, 404c: p-well, 405a, 405b: N-well, 406: silicon oxide film, 406a: silicon oxide film, 407: photoresist pattern, 408: thermal oxide film, 409: polycrystalline silicon film, 4 0 9 b: Polycrystalline sand film, 4 0 9 c: Gate electrode, 410: Sand oxide film, 41 Ob: Silicon oxide film, 411: Source / drain diffusion layer field, 41 2: Insulating film, 413: Polycrystalline silicon film, 413a Polycrystalline silicon film, 413b: floating gate, 414: ONO film, 415: polymer film, 415a: word line (control gate), 416a, 417a: source / drain area, 416b 417b: source / drain area, 501: p-type Si substrate, 502: element separation area, 503: separation area, 504a, 504b, 504c: p-well (p-well area), 505a, 505b: N-well (N-well area ), 506: silicon oxide film, 507: polycrystalline silicon film, 508: silicon nitride film, 509: source / drain diffusion layer field, 510: silicon oxide film, 510a: silicon oxide film, 5 11: photoresist pattern , 5 1 2: insulating film, 5 1 3: polycrystalline silicon film, 513a: polycrystalline silicon film, 513b: floating gate, 514: silicon oxide film, 515: ONO film, 516: polymer film, 516a: word line (control gate ), 517a, 518a: source / drain field, 517b, 518b: source / drain field, 600: silicon substrate, 601: well, 602: gate insulation film (tunnel insulation film), employees of Intellectual Property Bureau of the Ministry of Economic Affairs, employee consumption Cooperative printed 603b: floating gate, 605: drain diffusion layer field, 605 ': source, 607a: third gate, 611a: word line (control gate), AGe, AGo: third gate. Dm— 2 ~ Dm + 2: source or drain, M: memory cell, WLm, WLm + 1: word line WL0 ~ WLn — 1: word line, STTr: select transistor This paper size is applicable to China Associate (CNS) A4 size (210X297 mm) -42-

Claims (1)

200301011 A8 B8 C8 D8 6. Scope of Patent Application 1 1 · A non-volatile semiconductor memory device, which is characterized by: (Please read the precautions on the back before filling out this page) (a) Semiconductor substrates in semiconductor substrates The formed source and drain regions, and * (b) a first smell electrode formed between the above source and drain electrodes through a first insulating film; and (c) formed at A second gate electrode on the first gate electrode; and (d) a third gate electrode formed between the source electrode and the drain electrode via a third insulating film; (e) a film thickness ratio of the first insulating film The film thickness of the third insulating film is large. 2. For the non-volatile semiconductor memory device according to the scope of the patent application, the source and drain regions extend in the first direction, and the second gate extends in the second direction orthogonal to the first direction. Direction 5 The third gate extends in the first direction. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 3. For the non-volatile semiconductor memory device under the scope of patent application, the third gate is the gate that controls the divided channel. 4. For the non-volatile semiconductor memory device according to item 1 of the patent application, wherein the third gate has the functions of controlling the erasing of the gate and the gate of the divided channel. 5. The non-volatile semiconductor memory device according to item 1 of the scope of patent application, wherein the channel formed between the source and the drain is used to inject the hot electrons into the first gate for writing, and Ik paper The standard applies to China National Standard (CNS) A4 specification (210 X 297 mm) = 43-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 200301011 A8 B8 C8 D8 VI. Application for patent scope 2 The semiconductor field emits electrons for elimination. 6. For a non-volatile semiconductor memory device according to item 1 of the patent application scope, wherein the above-mentioned memory cell is configured by injecting hot electrons into the first gate electrode through a channel formed between the source and drain electrodes constituting the above-mentioned memory cell. Write, and release electrons to the third gate by the first gate for erasing. 7. The non-volatile semiconductor memory device according to item 1 of the application, wherein a fourth insulating film is disposed between the first gate and the third gate, and the first gate of the fourth insulating film is disposed. The film thickness between the third gate electrode is larger than the film thickness of the first insulating film. '8. The non-volatile semiconductor memory device according to item 1 of the scope of patent application, wherein a fourth insulating film is disposed between the first gate and the third gate, and the first gate of the fourth insulating film The film thickness between the electrode and the third gate is about the same as the film thickness of the first insulating film. 9. The non-volatile semiconductor memory device according to item 1 of the application, wherein a fourth insulating film is arranged between the first gate and the third gate, and the fourth insulating film is made of nitrogen-containing Made of oxide film. _ 10. A non-volatile semiconductor memory device, which includes: a memory cell formed in the field of a memory cell on a semiconductor substrate, and a peripheral sheet formed on the paper. Applicable to China National Standard (CNS) A4 (210X297 mm 公)- 44- I .--------------- Order ----- (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 200301011 A8 B8 C8 D8 VI. Patent application scope 3 MISFETs in the field of circuits, characterized in that the above-mentioned memory cells have: (a) source and drain fields formed in the semiconductor field in the field of memory cells; and (b) isolation A first gate formed between the source and the drain by a first insulating film; and (c) a second gate formed on the first gate by a second insulating film; and (d) A third gate formed between the source and the drain via a third insulating film having a film thickness smaller than the first insulating film; the MISFET has: (a) a source formed in a peripheral circuit field, The drain region; and (b) through the same layer as the third insulating film An edge film is formed on the gate electrode between the source and the drain. 11. For example, the non-volatile semiconductor memory device in the scope of the patent application No. 10 is formed by borrowing from the source and the drain. Channel to inject hot electrons into the first gate for writing, and release the electrons to the semiconductor field for elimination by using the first gate. 12. For example, for a non-volatile semiconductor memory device under the scope of patent application No. 10, The memory cell is configured to inject a hot electron to the first gate for writing by a channel formed between a source and a drain constituting the memory cell, and to the third gate by the first gate. Emission of electrons for elimination. This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) _ 45-L ----- »------ install ------ order --- --- (Please read the precautions on the back before filling this page) 200301011 A8 B8 C8 _ D8 VI. Patent Application Scope 4 (Please read the precautions on the back before filling this page) 1 3 · —A kind of non-volatile semiconductor Memory device having: formation A memory cell in a memory cell field on a semiconductor substrate, and a low-voltage MISFET and a high-voltage MISFET formed in a peripheral circuit field are characterized in that the memory cell has: (a) a semiconductor field formed in the memory cell field; Inside the source and drain regions; and (b) a first gate formed between the source and the drain via a first insulating film; and (c) formed on the above via a second insulating film A second gate electrode on the first gate electrode; and (d) a third gate electrode formed between the source electrode and the drain electrode via a third insulating film having a smaller thickness than the first insulating film; The voltage MISFET has: (a) a source and a drain region formed in the first field of the peripheral circuit field; and (b) formed on the source and the drain via an insulating film in the same layer as the third insulating film. The gate electrode above the electrodes; the above-mentioned high-voltage MISFET printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs has: (a) the source and drain areas of the second field formed in the peripheral circuit field; and (b) the barrier Thicker than the third insulating film A fourth insulating film formed on the source electrode, a drain electrode on the inter-alarm. 14. A non-volatile semiconductor memory device, comprising: a memory cell formed in the field of a memory cell having a semiconductor substrate; and a paper size formed around the paper, applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -46 -200301011 A8 B8 C8 D8 VI. Patent application scope 5 MISFETs in the field of circuits, characterized in that the above memory cells have: (Please read the precautions on the back before filling out this page) (a) Semiconductors formed in the field of memory cells A source and a drain in the field; and (b) a first gate formed between the source and the drain through the first insulating film; and (c) a second gate A second gate electrode on the first gate electrode; and (d) a third gate electrode formed between the source electrode and the drain electrode via a third insulating film having a smaller thickness than the first insulating film; The MISFET has: (a) a source and a drain formed in a peripheral circuit field; and (b) a gate formed between the source and the drain via an insulating film in the same layer as the first insulating film electrode. 15. For example, the non-volatile semiconductor memory device of the scope of application for patent No. 14, wherein the channel formed between the source and the drain is used to inject hot electrons into the first gate for writing, and it is economical. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Printing printed out the above-mentioned first gate to release electrons to the semiconductor field for elimination. 16. For a non-volatile semiconductor memory device according to item 14 of the application, wherein the memory cell is configured to inject hot electrons into the first gate for writing through a channel formed between a source and a drain of the memory cell. Into, and by using the first gate to emit electrons to the third gate for elimination. This paper size applies to China National Standard (CNS) A4 (210X297 mm) -47 _ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -48- 200301011 A8 B8 C8 D8 VI. Application for patent scope 6 17. — Non-volatile A semiconductor memory device includes: a memory cell in a memory cell field formed on a semiconductor substrate; and a low-voltage MISFET and a high-voltage MISFET formed in a peripheral circuit field, wherein the memory cell has: (a) A source and a drain region formed in a semiconductor field in the memory cell field; and (b) a first gate formed between the source and the drain via a first insulating film; and (c) a barrier A second gate electrode formed on the first gate electrode by a second insulating film; and (d) formed on the source electrode and the drain electrode via a third insulating film having a film thickness smaller than that of the first insulating film. A third gate in between; the above-mentioned MISFET for low voltage has: (a) a source and a drain region formed in the first field of the peripheral circuit field; and (b) an interlayer of the same layer as the third insulating film Shaped insulation film A gate electrode between the source and the drain; the above-mentioned MISFET for local voltage has: (a) a source and a drain field formed in a second field of the peripheral circuit field; and (b) separated from the first field An insulating film is a thick fourth insulating film to form a gate electrode between the source electrode and the drain electrode. 18. A type of non-volatile semiconductor memory device, which is characterized by: (a) a source formed in a semiconductor field in a semiconductor substrate, a paper size applicable to the Chinese National Standard (CNS) A4 specification (21 × 297) Dong) L ---------- t-- (Please read the notes on the back before filling out this page), 1T 200301011 A8 B8 C8 D8 VI. Patent scope 7-pole field; and (b) separated A first gate electrode formed between the source and drain electrodes by a first insulating film; and (C) formed on the first gate electrode through a second insulating film and formed on a first insulating film through a third insulating film. A second gate electrode in the semiconductor field; and (d) a second smell electrode formed in the semiconductor field through a fourth insulating film, (e) a film thickness of the first insulating film is larger than that of the third gate electrode; The thickness of the insulating film is large. 19. The non-volatile semiconductor memory device as claimed in claim 18, wherein the source and drain regions extend in a first direction, and the second gate extends in a direction orthogonal to the first direction. In the second direction, the third gate is formed between the second gates extending in the second direction. • 20. The non-volatile semiconductor memory device according to item 18 of the patent application scope, wherein the third gate has the function of eliminating the gate. 21. For example, the non-volatile semiconductor memory device under the scope of patent application No. 18, wherein the channel formed between the source and the drain is used to inject hot electrons into the first gate for writing, and borrowed from the above The first gate electrode emits electrons to the third smell electrode for elimination. 22. The non-volatile semiconductor memory device according to item 18 of the scope of patent application, wherein a fifth 1 μλ scale is arranged between the first gate sidewall and the second gate, and is applicable to Chinese National Standard (CNS) A4 specifications ( 210X297 mm) -49- L ---- Μ, ---- φ-pack—— (Please read the precautions on the back before filling in this page) Order. Read printed by the Employee Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 200301011 A8 B8 C8 D8 7. Apply for a patent for 8-layer insulation film, and (please read the precautions on the back before filling this page) The film thickness between the first gate sidewall and the second gate of the fifth insulation film is greater than the above The first insulating film has a large film thickness. 23. The non-volatile semiconductor memory device according to item 18 of the application, wherein a fifth insulating film is disposed between the first gate sidewall and the second gate, and the first gate of the fifth insulating film is disposed. The film thickness between the side wall and the second gate electrode is about the same as the film thickness of the first insulating film. 24. The non-volatile semiconductor memory device according to item 18 of the application, wherein a fifth insulating film is arranged between the first gate sidewall and the second gate, and the fifth insulating film is made of nitrogen-containing An oxide film is formed. 25. A non-volatile semiconductor memory device, comprising: (a) a source and a drain region formed in a semiconductor field in a semiconductor substrate; and (b) formed on the above through a first insulating film. The first gate between the source and the drain; and printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (c) formed on the first gate through the second insulating film and formed on the third gate through the third insulating film The second gate in the semiconductor field, and (e) the film thickness of the first insulating film is larger than the film thickness of the third insulating film. 26. The non-volatile semiconductor memory device according to the scope of application for patent No. 25, wherein the second gate is a gate for controlling a divided channel. 27. If the paper size of the non-volatile semiconductor memory paper for item 25 of the scope of patent application applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) "50-200320031111 A8 B8 C8 D8 Among them, the channel formed between the source and the drain is used to inject hot electrons into the first gate for writing, and (please read the precautions on the back before filling this page) to borrow the first gate Emitting electrons to the drain region for elimination 2 8. A method for manufacturing a non-volatile semiconductor memory device, comprising: a memory cell field formed on a semiconductor substrate including a floating gate, a control gate, and a third gate A memory cell; and a method for manufacturing a nonvolatile semiconductor memory device of a MISFET formed in a peripheral circuit field, which is characterized by: (a) a process of forming a first insulating film in the above-mentioned memory cell field and peripheral circuit field ; And (b) the process of forming the third gate electrode of the memory cell on the first insulating film in the memory cell field; and (c) the first The project of forming the gate electrode of the MISFET on an insulating film; and (d) the project of forming a second insulating film having a larger thickness than the first insulating film in the memory cell field; and the employee's consumption of the Intellectual Property Bureau of the Ministry of Economic Affairs The cooperative prints (e) a project of forming the floating gate on the second insulating film; and (f) a project of forming a control gate on the floating gate through a third insulating film. 29. A non-volatile semiconductor A method for manufacturing a memory device is a nonvolatile semiconductor memory including a memory cell formed on a semiconductor substrate and including a floating gate, a control gate, and a third gate, and a MISFET formed in a peripheral circuit field. The manufacturing method of the device is characterized in that the paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -51-200301011 A8 B8 C8 D8 々, the scope of patent application 10 has: (a) In the field of the above storage unit and A process of forming a first insulating film in the peripheral circuit field; and (b) forming a third gate of the memory cell on the first insulating film in the memory cell field Engineering; and (c) forming a second insulating film having a larger thickness than the first insulating film in the memory cell field and the peripheral circuit field; and (d) a second insulating film in the peripheral circuit field. Forming the gate electrode of the MISFET; and (e) forming the floating gate on the second insulating film in the memory cell field; and (f) forming control on the floating gate through the third insulating film Gate Engineering (Please read the notes on the back before filling out this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives This paper is printed in accordance with China National Standard (CNS) A4 (210X297 mm) -52-