US20020113272A1 - Embedded type flash memory structure and method for operating the same - Google Patents
Embedded type flash memory structure and method for operating the same Download PDFInfo
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- US20020113272A1 US20020113272A1 US09/781,430 US78143001A US2002113272A1 US 20020113272 A1 US20020113272 A1 US 20020113272A1 US 78143001 A US78143001 A US 78143001A US 2002113272 A1 US2002113272 A1 US 2002113272A1
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 230000008569 process Effects 0.000 claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 230000005283 ground state Effects 0.000 claims description 11
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 claims description 5
- 239000000463 material Substances 0.000 claims 2
- 230000000694 effects Effects 0.000 description 7
- 230000002093 peripheral effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
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- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
Definitions
- the present invention relates to a non-volatile memory structure and, more particularly, to a flash memory structure having the characteristics of low operational voltage and high density and a method for operating the same.
- Flash memories have been widely used in small electronic products such as notebook computers or digital cameras. Moreover, along with the trend of miniaturization of electronic products, the sizes of flash memories need to be smaller and smaller. However, when small-size flash memories are manufactured by means of sub-micrometer fabrication technology, the transistors of memory cells in the memory cell array must be operated at a small voltage about 3V because of short channel effects.
- FIG. 1 shows a memory cell structure of a prior art flash memory.
- N-type doped-regions used as a source 12 and a drain 14 are formed in a p-type semiconductor substrate 10 , and a channel is formed in the substrate 10 between the source 12 and drain 14 .
- a silicon dioxide layer 16 , a trapping layer 18 (e.g., silicon nitride), and a silicon dioxide layer 20 are formed in turn on the surface of the substrate 10 .
- a control gate 22 is then formed on the surface of the silicon dioxide layer 20 .
- the operational voltage of a prior art flash memory cannot be easily reduced so that the operational voltage is too high.
- the structure of the memory cell array is required to be denser and denser so that the channel length is reduced therewith, resulting in mutual influence of operation between each memory cell. If the operational voltage cannot be relatively reduced, short channel effects will arise so that the phenomenon of punch through will occur.
- complex design of peripheral circuits is required for higher operational voltages, the above high-voltage operational method will complicate the design of peripheral circuits.
- the simplest way to resolve the above short channel effects is to reduce the operational voltage or to change the operational mode to facilitate the miniaturization of memory cell. Accordingly, the present invention proposes an improved structure of flash memory cell and a method for operating the same to resolve the above problems in the prior art.
- the primary object of the present invention is to provide an improved structure of flash memory cell and a method for operating the same.
- a shallow doped-region is added below the doped-region used as the drain. Using these two different doped-regions to share the voltage, the voltage can be controlled and the operational voltage of the memory cell can be reduced. Moreover, the design of peripheral circuits will be simpler.
- Another object of the present invention is to provide an embedded type flash memory structure having the characteristics of low operational voltage and high density and a method for operating the same.
- an n-well is formed in a p-type substrate.
- a shallow p-well is formed in the n-well, and a drain and a source of shallower n-type doped-regions are formed in the shallow p-well and the n-well, respectively.
- a dielectric insulating layer and a poly-silicon gate are stacked above the n-well to connect all the drains.
- FIG. 1 is a diagram of the memory cell structure of a prior art flash memory
- FIG. 2 is a diagram of the flash memory cell structure of the present invention.
- FIG. 3 is a diagram of the memory array of the present invention.
- FIGS. 4 (A), 4 (B), and 4 (C) show the programming process, the erasing process, and the reading process according to an embodiment of the present invention, respectively.
- the present invention is characterized in that a second doped-region is added to share the voltage of a first shallow doped-region used as a drain to reduce the operational voltage of the memory cell so that both the effects of low operational voltage and high density can be achieved.
- a flash memory cell structure is shown in FIG. 2.
- a first deep doped-region is formed in a p-type semiconductor substrate 32 by means of ion implantation.
- the first doped-region is an n-well 34 .
- a second doped-region is formed in the n-well 34 .
- the second doped-region is a shallow p-well 35 .
- N-type ions are implanted in the surface of the n-well 34 and the shallow p-well 35 to form first shallow doped-regions.
- the first shallow doped-region in the n-well 34 is used as a source 38
- the first shallow doped-region in the shallow p-well 35 is used as a drain 36 .
- the doping depth of the n-well 34 is much larger than that of the first shallow doped-region used as the drain 36 .
- a dielectric insulating layer 40 is stacked above the n-well 34 between the drain 36 and the source 38 .
- the dielectric insulating layer 40 comprises a silicon oxide layer 42 , a trapping layer 44 (usually being silicon nitride), and a silicon oxide layer 46 .
- the dielectric insulating layer 40 is thus called an oxide-nitride-oxide film, briefly termed an ONO film.
- a gate 48 such as highly doped poly-silicon is used to connect all the drains 36 . Because of the functions of the n-type drain 36 and the shallow p-well 35 thereunder, the original higher voltage in the prior art drain is split into two parts so that the operational voltage can be effectively reduced. The operational voltage will be clearly described below.
- the poly-silicon gate 48 of the flash memory cell 30 forms a word line 50
- the drain 36 forms a bit line 52 .
- a shallow p-well 35 is implanted below the n-type drain 36 between every two adjacent word lines 50 . Every two word lines 50 share a shallow p-well 35 .
- the object of reducing the operational voltage is accomplished by individually applying voltages to the shallow p-well 35 and the bit line 52 .
- the above trapping layer 42 in the dielectric insulating layer 40 is used as a charge-storing region for accepting and keeping electrons or holes injected into the dielectric insulating layer 40 so as to perform the programming or erasing process.
- a source line voltage V S , a bit line voltage V BL , and a word line voltage V WL are applied to the source 38 , the drain 36 , and the gate 48 of the flash memory cell 30 , respectively.
- a shallow p-well voltage V PW is also applied to the shallow p-well 35 to facilitate the operations of programming, erasing, and reading of the memory cell 30 .
- FIG. 4(A) shows a programming process of the flash memory cell 30 .
- a positive bit line voltage V BL about 2 ⁇ 5V, e.g., V BL 2.5V, is applied to the drain 36 .
- a sufficiently large negative voltage about ⁇ 2 ⁇ 5V, e.g., V PW ⁇ 2.5V, is applied to the p-well 35 .
- BTBT band-to-band tunneling
- FIG. 4(B) shows an erasing process of the flash memory cell 30 .
- the bit line voltage V BL is a floating state.
- a negative voltage about ⁇ 3 ⁇ 7V, e.g., V PW ⁇ 5V, is applied to the p-well. This sufficiently large negative voltage and the OV of the drain and the channel are exploited so that a sufficiently large BTBT current can be generated in the channel region.
- FIG. 4(C) shows a reading process of the flash memory cell 30 .
- the word line voltage V WL of a positive voltage about 2 ⁇ 5V, e.g., V WL 3.3V, is applied to the gate 48 .
- the present invention exploits the functions of an n-type drain and another shallow doped p-well to respectively control and share the voltage so as to reduce the operational voltage of the flash memory cell.
- the design of peripheral circuits can also be simplified. Because short channel effects or the phenomenon of punch through will not occur in the present invention, the miniaturization of the memory cell can be enhanced so that both the effects of high density and low operational voltage can be achieved.
- the present invention uses a flash memory cell having a p-type semiconductor substrate to illustrate the structure and the operational method of the present invention.
- the present invention can also use a flash memory cell having an n-type semiconductor substrate to achieve the same effect.
- the flash memory cell having an n-type semiconductor substrate the first deep doped-region and the first shallow doped-region are changed to be p-type doped-regions, and the second doped-region is a corresponding n-type doped-region.
- the other structure and the relevant positions are the same as above and thus will not be further illustrated.
- the operations of programming, erasing, and reading of the flash memory cell having an n-type semiconductor substrate can be accomplished by only applying voltages reverse to those of the above flash memory cell having a p-type semiconductor substrate. That is, during the operational process, positive and negative voltages applied to the flash memory cell having a p-type semiconductor substrate are respectively changed to negative and positive voltages, and original zero voltages, ground states, and floating states are kept invariant. Thereby, the operations of programming, erasing, and reading of the flash memory cell having an n-type semiconductor substrate can be accomplished through these reverse operational voltages.
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- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
Abstract
Description
- The present invention relates to a non-volatile memory structure and, more particularly, to a flash memory structure having the characteristics of low operational voltage and high density and a method for operating the same.
- Flash memories have been widely used in small electronic products such as notebook computers or digital cameras. Moreover, along with the trend of miniaturization of electronic products, the sizes of flash memories need to be smaller and smaller. However, when small-size flash memories are manufactured by means of sub-micrometer fabrication technology, the transistors of memory cells in the memory cell array must be operated at a small voltage about 3V because of short channel effects.
- FIG. 1 shows a memory cell structure of a prior art flash memory. N-type doped-regions used as a
source 12 and adrain 14 are formed in a p-type semiconductor substrate 10, and a channel is formed in thesubstrate 10 between thesource 12 anddrain 14. Asilicon dioxide layer 16, a trapping layer 18 (e.g., silicon nitride), and asilicon dioxide layer 20 are formed in turn on the surface of thesubstrate 10. Acontrol gate 22 is then formed on the surface of thesilicon dioxide layer 20. When a programming process is performed to the memory cell, a sufficiently large voltage must be applied to the drain and the source so that the above action can be accomplished by means of the channel formed by this high voltage difference. Therefore, the operational voltage of a prior art flash memory cannot be easily reduced so that the operational voltage is too high. Moreover, the structure of the memory cell array is required to be denser and denser so that the channel length is reduced therewith, resulting in mutual influence of operation between each memory cell. If the operational voltage cannot be relatively reduced, short channel effects will arise so that the phenomenon of punch through will occur. Furthermore, because complex design of peripheral circuits is required for higher operational voltages, the above high-voltage operational method will complicate the design of peripheral circuits. - The simplest way to resolve the above short channel effects is to reduce the operational voltage or to change the operational mode to facilitate the miniaturization of memory cell. Accordingly, the present invention proposes an improved structure of flash memory cell and a method for operating the same to resolve the above problems in the prior art.
- The primary object of the present invention is to provide an improved structure of flash memory cell and a method for operating the same. A shallow doped-region is added below the doped-region used as the drain. Using these two different doped-regions to share the voltage, the voltage can be controlled and the operational voltage of the memory cell can be reduced. Moreover, the design of peripheral circuits will be simpler.
- Another object of the present invention is to provide an embedded type flash memory structure having the characteristics of low operational voltage and high density and a method for operating the same.
- According to the present invention, an n-well is formed in a p-type substrate. A shallow p-well is formed in the n-well, and a drain and a source of shallower n-type doped-regions are formed in the shallow p-well and the n-well, respectively. A dielectric insulating layer and a poly-silicon gate are stacked above the n-well to connect all the drains.
- The various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawings, in which:
- FIG. 1 is a diagram of the memory cell structure of a prior art flash memory;
- FIG. 2 is a diagram of the flash memory cell structure of the present invention;
- FIG. 3 is a diagram of the memory array of the present invention; and
- FIGS.4(A), 4(B), and 4(C) show the programming process, the erasing process, and the reading process according to an embodiment of the present invention, respectively.
- The present invention is characterized in that a second doped-region is added to share the voltage of a first shallow doped-region used as a drain to reduce the operational voltage of the memory cell so that both the effects of low operational voltage and high density can be achieved.
- A flash memory cell structure is shown in FIG. 2. A first deep doped-region is formed in a p-
type semiconductor substrate 32 by means of ion implantation. The first doped-region is an n-well 34. A second doped-region is formed in the n-well 34. The second doped-region is a shallow p-well 35. N-type ions are implanted in the surface of the n-well 34 and the shallow p-well 35 to form first shallow doped-regions. The first shallow doped-region in the n-well 34 is used as asource 38, and the first shallow doped-region in the shallow p-well 35 is used as adrain 36. The doping depth of the n-well 34 is much larger than that of the first shallow doped-region used as thedrain 36. Adielectric insulating layer 40 is stacked above the n-well 34 between thedrain 36 and thesource 38. Thedielectric insulating layer 40 comprises asilicon oxide layer 42, a trapping layer 44 (usually being silicon nitride), and asilicon oxide layer 46. Thedielectric insulating layer 40 is thus called an oxide-nitride-oxide film, briefly termed an ONO film. Agate 48 such as highly doped poly-silicon is used to connect all thedrains 36. Because of the functions of the n-type drain 36 and the shallow p-well 35 thereunder, the original higher voltage in the prior art drain is split into two parts so that the operational voltage can be effectively reduced. The operational voltage will be clearly described below. - Please also refer to FIG. 3. The poly-
silicon gate 48 of theflash memory cell 30 forms aword line 50, and thedrain 36 forms abit line 52. A shallow p-well 35 is implanted below the n-type drain 36 between every twoadjacent word lines 50. Every twoword lines 50 share a shallow p-well 35. The object of reducing the operational voltage is accomplished by individually applying voltages to the shallow p-well 35 and thebit line 52. - The
above trapping layer 42 in thedielectric insulating layer 40 is used as a charge-storing region for accepting and keeping electrons or holes injected into thedielectric insulating layer 40 so as to perform the programming or erasing process. - The operational method corresponding to the flash memory cell structure of the present invention will be illustrated below. Please refer to FIGS. 2 and 3 simultaneously. A source line voltage VS, a bit line voltage VBL, and a word line voltage VWL are applied to the
source 38, thedrain 36, and thegate 48 of theflash memory cell 30, respectively. A shallow p-well voltage VPW is also applied to the shallow p-well 35 to facilitate the operations of programming, erasing, and reading of thememory cell 30. - FIG. 4(A) shows a programming process of the
flash memory cell 30. A positive bit line voltage VBL about 2˜5V, e.g., VBL=2.5V, is applied to thedrain 36. The source line voltage is a ground state (VS=0) . A sufficiently large negative voltage about −2˜−5V, e.g., VPW=−2.5V, is applied to the p-well 35. A negative word line voltage about −2˜−7V, e.g., VWL=−3.3V, is also exploited to generate a sufficiently large band-to-band tunneling (BTBT) current between the interfaces of thegate 48 and thedrain 36 and the shallow p-well 35 so that induced thermal holes will pass through thesilicon oxide layer 42 to let the holes be trapped in the charge-storing region of thetrapping layer 44. Thereby, the charge status after the programming process can be stored to achieve the function of programming. - FIG. 4(B) shows an erasing process of the
flash memory cell 30. The bit line voltage VBL is a floating state. The source line voltage is a ground state (VS=0). The word line voltage VWL is a sufficiently large positive voltage about 2˜5V, e.g., VWL=3.3V. Thereby, a device channel will be formed. A negative voltage about −3˜−7V, e.g., VPW=−5V, is applied to the p-well. This sufficiently large negative voltage and the OV of the drain and the channel are exploited so that a sufficiently large BTBT current can be generated in the channel region. Part of hot electrons will be attracted by the sufficiently large vertical electric field of the word line voltage VWL to pass the energy barrier of thesilicon oxide layer 42 and reach thetrapping layer 44 to be trapped in the same charge-storing region as that in the above programming process of thetrapping layer 44. Thereby, holes in the charge-storing region can be compensated. The operation of erasing is thus completed. - FIG. 4(C) shows a reading process of the
flash memory cell 30. The word line voltage VWL of a positive voltage about 2˜5V, e.g., VWL=3.3V, is applied to thegate 48. The bit line voltage is a ground state (VBL=0). The source line voltage Vs is a lower positive voltage (VS=1V). The voltage of the p-well Vpw is a ground state (VPW=0). The operation of reading to the bit of theflash memory cell 30 is thus completed. - The present invention exploits the functions of an n-type drain and another shallow doped p-well to respectively control and share the voltage so as to reduce the operational voltage of the flash memory cell. The design of peripheral circuits can also be simplified. Because short channel effects or the phenomenon of punch through will not occur in the present invention, the miniaturization of the memory cell can be enhanced so that both the effects of high density and low operational voltage can be achieved.
- The present invention uses a flash memory cell having a p-type semiconductor substrate to illustrate the structure and the operational method of the present invention. The present invention can also use a flash memory cell having an n-type semiconductor substrate to achieve the same effect. In the flash memory cell having an n-type semiconductor substrate, the first deep doped-region and the first shallow doped-region are changed to be p-type doped-regions, and the second doped-region is a corresponding n-type doped-region. The other structure and the relevant positions are the same as above and thus will not be further illustrated. The operations of programming, erasing, and reading of the flash memory cell having an n-type semiconductor substrate can be accomplished by only applying voltages reverse to those of the above flash memory cell having a p-type semiconductor substrate. That is, during the operational process, positive and negative voltages applied to the flash memory cell having a p-type semiconductor substrate are respectively changed to negative and positive voltages, and original zero voltages, ground states, and floating states are kept invariant. Thereby, the operations of programming, erasing, and reading of the flash memory cell having an n-type semiconductor substrate can be accomplished through these reverse operational voltages.
- Although the present invention has been described with reference to the preferred embodiments thereof, it will be understood that the invention is not limited to the details thereof. Various substitutions and modifications have been suggested in the foregoing description, and other will occur to those of ordinary skill in the art. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the invention as defined in the appended claims.
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Cited By (5)
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US20040161896A1 (en) * | 2002-07-03 | 2004-08-19 | Jiun-Ren Lai | [structure of a memory device and fabrication method thereof] |
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US20050093055A1 (en) * | 2003-11-05 | 2005-05-05 | Leo Wang | Flash memory and method thereof |
US20110116323A1 (en) * | 2006-12-27 | 2011-05-19 | Yukio Hayakawa | Semiconductor device, method of controlling the same, and method of manufacturing the same |
US20110267897A1 (en) * | 2006-11-20 | 2011-11-03 | Taiwan Semiconductor Manufacturing Company Ltd. | Non-Volatile Memory Cells Formed in Back-End-of-Line Processes |
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US8716082B2 (en) * | 2006-12-27 | 2014-05-06 | Spansion Llc | Semiconductor device, method of controlling the same, and method of manufacturing the same |
US20150001611A1 (en) * | 2006-12-27 | 2015-01-01 | Spansion Llc | Semiconductor device, method of controlling the same, and method of manufacturing the same |
US9472564B2 (en) * | 2006-12-27 | 2016-10-18 | Cypress Semiconductor Corporation | System with memory having voltage applying unit |
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