JP2007096038A - Nonvolatile memory element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile memory element for solving various problems of the conventional technologies. <P>SOLUTION: The nonvolatile memory element comprises a memory cell and a high-voltage MOS transistor. The memory cell is provided in a memory array region, and comprises a PMOS access transistor and a PMOS storage transistor connected in series to the access transistor via a floating and common p-type doped region. The PMOS access transistor comprises an access gate, an access gate oxide film, and a p-type source doped region used for its drain. The PMOS storage transistor comprises a control gate, a charge storing structure, and a p-type drain doped region used for its source. The high-voltage MOS transistor is provided in a peripheral circuit region and comprises a high-voltage gate and a high-voltage gate oxide film, having thickness matching that of the access gate oxide film. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor nonvolatile memory element, and more particularly to a nonvolatile memory element made of a single polysilicon film.

  With the spread of portable electronic products such as digital cameras, PDAs and notebook personal computers, the importance of nonvolatile memories in semiconductor memory devices is increasing day by day. In recent years, ONO (silicon oxide-silicon nitride-silicon oxide) nonvolatile memory elements have attracted attention because their SONOS structure has a low voltage and can be programmed and compared with other nonvolatile memories (for example, those utilizing floating gate technology). Not only can erasing be performed and tail bits are not generated, but also the manufacturing process can be simplified.

  As the degree of integration of semiconductor devices increases, in the manufacture of current memory integrated circuits, a memory cell array and other elements are often integrated into a single embedded memory. For example, in general, a memory array and a high-speed logic circuit element are manufactured on one chip, thereby saving an area and increasing a signal processing speed.

  The non-volatile memory element is characterized in that an insulating dielectric film made of silicon nitride is used as a charge trapping medium. Utilizing a high-density silicon nitride film, trapping hot electrons that enter the silicon nitride film by the tunnel effect to form a non-uniform concentration distribution, thereby speeding up data reading and preventing leakage current Can do. On the other hand, the conventional floating gate flash memory uses a floating gate to store charges, and therefore requires a separate control gate on the floating gate.

  If the ONO nonvolatile memory device and the floating gate flash memory are compared, the former is simple to manufacture and low in cost. On the other hand, the latter has a three-stage gate stack structure of a floating gate, an intermediate dielectric film, and a control gate, which not only requires a complicated manufacturing process but also has a high manufacturing cost.

  An object of the present invention is to provide a non-volatile memory device for solving the above-mentioned problems.

  The nonvolatile memory device according to the present invention includes a memory cell and a high voltage MOS transistor. The memory cell is provided in a memory array region of the nonvolatile memory element, and includes a PMOS access transistor and a PMOS storage transistor connected in series with the PMOS access transistor through a floating and shared P-type doped region. Among them, the PMOS access transistor includes an access gate, an access gate oxide film, and a P-type source doped region, and the floating and shared P-type doped region serves as the drain of the PMOS access transistor. The PMOS storage transistor includes a control gate, a charge storage structure, and a P-type drain doped region, and the floating and shared P-type doped region is a source of the PMOS storage transistor. The high voltage MOS transistor is provided in the peripheral circuit region of the nonvolatile memory element, and includes a high voltage gate and a high voltage gate oxide film. Among them, the thickness of the high-voltage gate oxide film matches the thickness of the access gate oxide film.

  Other nonvolatile memory devices according to the present invention include a memory cell, a high voltage MOS transistor, and a MOS transistor. The memory cell is provided in a memory array region of the nonvolatile memory element, and includes a PMOS access transistor and a PMOS storage transistor connected in series with the PMOS access transistor through a floating and shared P-type doped region. Among them, the PMOS access transistor includes an access gate, an access gate oxide film, and a P-type source doped region, and the floating and shared P-type doped region serves as the drain of the PMOS access transistor. The PMOS storage transistor includes a control gate, a charge storage structure, and a P-type drain doped region, and the floating and shared P-type doped region is a source of the PMOS storage transistor. The high voltage MOS transistor is provided in the peripheral circuit region of the nonvolatile memory element, and includes a high voltage gate and a high voltage gate oxide film. Among them, the thickness of the high-voltage gate oxide film matches the thickness of the access gate oxide film. The MOS transistor is provided in the peripheral circuit region and includes a gate and a charge storage structure.

  Other non-volatile memory devices according to the present invention include memory cells, high voltage MOS transistors, and low voltage MOS transistors. The memory cell is provided in a memory array region of the nonvolatile memory element, and includes a PMOS access transistor and a PMOS storage transistor connected in series with the PMOS access transistor through a floating and shared P-type doped region. Among them, the PMOS access transistor includes an access gate, an access gate oxide film, and a P-type source doped region, and the floating and shared P-type doped region serves as the drain of the PMOS access transistor. The PMOS storage transistor includes a control gate, a charge storage structure, and a P-type drain doped region, and the floating and shared P-type doped region is a source of the PMOS storage transistor. The high voltage MOS transistor is provided in the peripheral circuit region of the nonvolatile memory element, and includes a high voltage gate and a high voltage gate oxide film. Among them, the thickness of the high-voltage gate oxide film matches the thickness of the access gate oxide film. The low voltage MOS transistor is provided in the peripheral circuit region, and includes a low voltage gate and a low voltage gate oxide film. Of these, the thickness of the low-pressure gate oxide film is smaller than the thickness of the high-pressure gate oxide film.

  In the nonvolatile memory device according to the present invention, since the gate oxide film of the access transistor is made thick, it can receive a higher voltage. The nonvolatile memory device according to the present invention separately includes a transistor having a structure similar to that of the storage transistor in the memory array region, in addition to the high-voltage MOS transistor in the peripheral circuit region. The transistor can be a circuit element that trims the reference circuit in the sense amplifier to increase the accuracy of the sense amplifier, or can be plugged into the sense amplifier to provide a reference current to the sense amplifier.

  In order to detail the features of such an apparatus, a specific example will be given and described below with reference to the drawings.

  Please refer to FIG. 1 is a cross-sectional view of a nonvolatile memory according to Embodiment 1 of the present invention. According to FIG. 1, a memory array region 101 and a peripheral circuit region 102 are provided on a semiconductor substrate 100 (for example, a P-type silicon substrate). An ion well 110 (for example, N type) formed by ion implantation is provided in the memory array region 101, and a groove type insulating structure 130 (for example, shallow trench isolation (STI)) is formed on the surface of the substrate 100. .

  One or more nonvolatile memory cells 200 are provided on the N-type ion well 110 in the memory array region 101, and the nonvolatile memory cell 200 includes an access transistor 210 and a storage transistor 220. According to this embodiment, both the access transistor 210 and the storage transistor 220 are PMOS transistors, of which the access transistor 210 includes a gate 214, a gate oxide film 212 provided between the gate 214 and the N-type well 110, and P The storage transistor 220 includes a gate 224 and an ONO dielectric provided between the gate 224 and the N-type well 110, including a type drain / source doped region 216, a P type drain / source doped region 232, and a P type lightly doped drain 218. It includes a film 150, a P-type drain / source doped region 232, a P-type drain / source doped region 226, and a P-type lightly doped drain 228.

  In addition, side wall spacers 230 are formed on the side walls of the gates 214 and 224. The ONO dielectric film 150 includes a lower silicon oxide film 151, a silicon nitride capturing film 152, and an upper oxide film 153. In this embodiment, the thickness of the lower silicon oxide film 151 is 15 to 35 angstroms, the thickness of the silicon nitride trap film 152 is 50 to 100 angstroms, and the thickness of the upper silicon oxide film 153 is 45 to 100 angstroms. Is desirable. As shown in FIG. 1, the access transistor 210 and the storage transistor 220 constituting the nonvolatile memory cell 200 are connected in series via a P-type drain / source doped region 232.

  The peripheral circuit region 102 is provided with a high-voltage MOS transistor 310, and the high-voltage MOS transistor 310 is electrically isolated via the groove type insulating structure 130. According to this embodiment, the high-voltage MOS transistor 310 is a PMOS transistor or an NMOS transistor, and includes a gate 314, a sidewall spacer 330 provided on the sidewall of the gate 314, and a gate oxide film provided between the gate 314 and the semiconductor substrate 100. 312, a drain / source doped region 316, and a lightly doped drain 318. The thickness of the gate oxide film 312 of the high-voltage MOS transistor 310 can be adjusted in accordance with the manufacturing process or product requirements. Since there is only this single gate oxide film in the peripheral circuit region, the number of masks required for the manufacturing process is small (since there is no low-voltage element in the peripheral circuit region), and simple and low-cost manufacturing can be realized.

  The feature of the present invention is that the thickness of the gate oxide film 212 of the access transistor 210 in the memory array region 101 and the thickness of the gate oxide film 312 of the high-voltage MOS transistor 310 in the peripheral circuit region 102 are the same. In addition, both the access transistor 210 and the storage transistor 220 of the nonvolatile memory cell 200 according to the present invention are PMOS transistors. Another feature of the present invention is that an access transistor 210 and a storage transistor 220 constituting a memory cell are connected in series. Therefore, the nonvolatile memory according to the present invention has a NOR structure instead of a NAND structure.

  Please refer to FIG. 2 to FIG. These drawings are cross-sectional views showing a method of manufacturing the embedded nonvolatile memory according to the first embodiment of the present invention. According to FIG. 2, a memory array region 101 and a peripheral circuit region 102 are defined on the semiconductor substrate 100. Regarding the fabrication, first, an N-type ion well 110 is formed in the memory array region 101 of the substrate 100 by an ion implantation process, and then a groove-type insulating structure 130 is formed on the surface of the substrate 100. However, it is also possible to perform ion implantation of the ion wells 110 and 120 after the groove-type insulating structure 130 is formed first. Subsequently, an ONO process is performed to form an ONO stack film 150 on the surface of the substrate 100. As described above, the ONO deposition film 150 includes the lower silicon oxide film 151, the silicon nitride capture film 152, and the upper silicon oxide film 153. Subsequently, a photoresist mask pattern 410 that defines a channel region of the storage transistor is formed on the ONO deposited film 150 in the memory array region 101.

  Subsequently, as shown in FIG. 3, an etching process is performed using the photoresist mask pattern 410 as an etching hard mask, and a portion of the ONO stack film 150 that is not covered with the photoresist mask pattern 410 is removed. Thereafter, the photoresist mask pattern 410 is removed.

As shown in FIG. 4, a thermal oxidation process is performed to grow a silicon dioxide film 112 having a thickness t ₁ on the semiconductor substrate 100, and this silicon dioxide film 112 is formed with the gate oxide film of the high-voltage MOS transistor in the peripheral circuit region 102. The gate oxide film of the access transistor in the memory array region 101 is used. In this embodiment, the thickness t ₁ of the silicon dioxide film 112 is 50 to 200 angstroms.

  Subsequently, as shown in FIG. 5, a doped polysilicon film 114 is deposited on the semiconductor substrate 100, and then a photoresist for determining the gate positions and patterns of the peripheral circuit region 102 and the memory array region 101 is formed on the doped polysilicon film 114. A mask pattern 430 is formed.

  As shown in FIG. 6, a dry etching process is performed using the photoresist mask pattern 430 as an etching hard mask to remove portions of the doped polysilicon film 114 and the silicon dioxide film 112 that are not covered with the photoresist mask pattern 430. The gates of the peripheral circuit region 102 and the memory array region 101 are defined, and a gate oxide film 312 and a gate structure 214, a gate structure 224, a gate oxide film 312 and a gate structure 314 are formed in the memory array region 101, respectively.

As shown in FIG. 7, after removing the photoresist mask pattern 430, drain source lightly doped regions (LDD) 218, 228, and 318 are formed in the semiconductor substrate 100 on both sides of the gate by an ion implantation process. Subsequently, a sidewall spacer process is performed, and an ion implantation process is performed again to form drain source highly doped regions (N ⁺ / P ⁺ ) 216, 226, 232, and 316 in the semiconductor substrate 100 on both sides of the gate sidewall spacer.

  Please refer to FIG. FIG. 8 is a cross-sectional view of a nonvolatile memory according to Embodiment 2 of the present invention. According to FIG. 8, a memory array region 101 and a peripheral circuit region 102 are provided on a semiconductor substrate 100 (for example, a P-type silicon substrate). An ion well 110 (for example, N type) formed by ion implantation is provided in the memory array region 101, and a groove type insulating structure 130 (for example, STI) is formed on the surface of the substrate 100. Unlike the first embodiment shown in FIG. 1, in the second embodiment, the peripheral circuit region 102 includes, in addition to the high-voltage MOS transistor 310, a transistor 510 having the same structure as the storage transistor 220 in the memory array region 101. Transistor 510 includes an ONO dielectric film 512, a gate 514, and a drain / source doped region 516. Transistor 510 is either a circuit element that trims the reference circuit in the sense amplifier to increase the accuracy of the sense amplifier, or is inserted into the sense amplifier and used to provide a reference current to the sense amplifier. Thus, the reference current by the reference circuit can be tracked according to the characteristics of the memory elements in the memory region, and the memory window of the chip is increased accordingly, and a better yield and reliability can be obtained.

  Please refer to FIG. 9 to FIG. These drawings are cross-sectional views showing a method for manufacturing the embedded nonvolatile memory according to the second embodiment of the present invention. According to FIG. 9, a memory array region 101 and a peripheral circuit region 102 are defined in the semiconductor substrate 100. Regarding the fabrication, first, an N-type ion well 110 is formed in the memory array region 101 of the substrate 100 by an ion implantation process, and then a groove-type insulating structure 130 is formed on the surface of the substrate 100. However, it is also possible to perform ion implantation of the ion wells 110 and 120 after the groove-type insulating structure 130 is formed first. Subsequently, an ONO process is performed to form an ONO stack film 150 on the surface of the substrate 100. As described above, the ONO deposition film 150 includes the lower silicon oxide film 151, the silicon nitride capture film 152, and the upper silicon oxide film 153. Subsequently, a photoresist mask pattern 410 that defines a channel region of the storage transistor is formed on the ONO deposited film 150 in the memory array region 101.

  Subsequently, as illustrated in FIG. 10, an etching process is performed using the photoresist mask pattern 410 as an etching hard mask, and a portion of the ONO stack film 150 that is not covered with the photoresist mask pattern 410 is removed. Thereafter, the photoresist mask pattern 410 is removed.

As shown in FIG. 11, a thermal oxidation process is performed to grow a silicon dioxide film 112 having a thickness t ₂ on the semiconductor substrate 100, and this silicon dioxide film 112 is formed with the gate oxide film of the high-voltage MOS transistor in the peripheral circuit region 102. The gate oxide film of the access transistor in the memory array region 101 is used. In this embodiment, the thickness t2 of the silicon dioxide film 112 is 30 to ₂₀₀ angstroms. Subsequently, a photoresist mask pattern 420 is formed on the semiconductor substrate 100. The photoresist mask pattern 420 exposes the active region 102b in the peripheral circuit region 102 where the low voltage MOS transistor is to be formed while covering the memory array region 101 and the active region 102a in which the high voltage MOS transistor is to be formed in the peripheral circuit region 102.

  As shown in FIG. 12, an etching process such as wet etching is performed to remove a portion of the silicon dioxide film 112 that is not covered with the photoresist mask pattern 420. Thereafter, the photoresist mask pattern 420 is removed.

As shown in FIG. 13, a thermal oxidation process such as an oxidation furnace thermal oxidation method is performed to grow a silicon dioxide film 122 having a thickness t _{3 in} the active region 102b where the low-voltage MOS transistor is to be formed in the peripheral circuit region 102, of which the thickness _{t 3} is smaller than the thickness _{t 2.} The thermal oxidation process is increased until the silicon dioxide film 112 had a thickness t ₂ in the thickness t _4. In this embodiment, the thickness _{t 3} is 15 to 100 angstroms, the thickness _{t 4} is 50 to 200 angstroms. However, this does not limit the invention.

  Subsequently, a doped polysilicon film 114 is deposited on the semiconductor substrate 100, and then a photoresist mask pattern 430 that defines the gate positions and patterns of the peripheral circuit region 102 and the memory array region 101 is formed on the doped polysilicon film 114.

  As shown in FIG. 14, a dry etching process is performed using the photoresist mask pattern 430 as an etching hard mask, and a portion of the doped polysilicon film 114 that is not covered with the photoresist mask pattern 430 is removed. The gates of the memory array region 101 are defined, and a gate oxide film 212 and a gate structure 214, a gate structure 224, a gate oxide film 312 and a gate structure 314, and a gate oxide film 322 and a gate structure 324 are formed in the memory array region 101, respectively.

  Thereafter, after removing the photoresist mask pattern 430, drain source lightly doped regions 218, 228, 318, and 328 are formed in the semiconductor substrate 100 on both sides of the gate by an ion implantation process. Subsequently, a sidewall spacer process is performed, and an ion implantation process is performed again to form drain source highly doped regions 216, 226, 232, 316, and 326 in the semiconductor substrate 100 on both sides of the gate sidewall spacer.

  The thickness of the gate oxide film 312 of the high voltage transistor 310 in the peripheral circuit region 102 formed in this way matches the thickness of the gate oxide film 212 of the access transistor 210 in the memory array region 101.

  Refer to FIG. 15 is a sectional view of a nonvolatile memory according to Embodiment 3 of the present invention. According to FIG. 15, a memory array region 101 and a peripheral circuit region 102 are provided on a semiconductor substrate 100 (for example, a P-type silicon substrate). An ion well 110 (for example, N type) formed by ion implantation is provided in the memory array region 101, and a groove type insulating structure 130 (for example, STI) is formed on the surface of the substrate 100. Unlike the first embodiment shown in FIG. 1, in the second embodiment, the peripheral circuit region 102 is a transistor having the same structure as the storage transistor 220 in the memory array region 101 in addition to the high-voltage MOS transistor 310 and the low-voltage MOS transistor 320. The transistor 510 includes an ONO dielectric film 512, a gate 514, and a drain / source doped region 516. The transistor 510 can be a circuit element that trims the reference circuit in the sense amplifier.

  In the fourth embodiment of the present invention, in addition to the high voltage MOS transistor 310 and the low voltage MOS transistor 320, the peripheral circuit region 102 includes a medium voltage MOS transistor (not shown), and the thickness of the gate oxide film is the high voltage MOS transistor. It depends on the thickness of the gate oxide film 310 and the thickness of the gate oxide film of the low-voltage MOS transistor 320.

  The above are preferred embodiments of the present invention, and do not limit the scope of the present invention. Therefore, any modifications or changes that can be made by those skilled in the art, which are made within the spirit of the present invention and have an equivalent effect on the present invention, shall belong to the scope of the claims of the present invention. To do.

  In the nonvolatile memory device according to the present invention, since the gate oxide film of the access transistor is made thick, it can receive a higher voltage.

It is sectional drawing of the non-volatile memory by Example 1 of this invention. It is 1st sectional drawing showing the manufacturing method of the embedded non-volatile memory by Example 1 of this invention. It is a 2nd sectional drawing showing the manufacturing method of the embedded non-volatile memory by Example 1 of this invention. It is a 3rd sectional view showing the manufacturing method of the embedded non-volatile memory by Example 1 of this invention. It is a 4th sectional view showing a manufacturing method of an embedded type non-volatile memory by Example 1 of this invention. It is a 5th sectional view showing the manufacturing method of the embedded non-volatile memory by Example 1 of this invention. It is a 6th sectional view showing a manufacturing method of an embedded type non-volatile memory by Example 1 of this invention. It is sectional drawing of the non-volatile memory by Example 2 of this invention. It is 1st sectional drawing showing the manufacturing method of the embedded non-volatile memory by Example 2 of this invention. It is 2nd sectional drawing showing the manufacturing method of the embedded non-volatile memory by Example 2 of this invention. It is 3rd sectional drawing showing the manufacturing method of the embedded non-volatile memory by Example 2 of this invention. It is a 4th sectional view showing the manufacturing method of the embedding type non-volatile memory by Example 2 of this invention. It is a 5th sectional view showing the manufacturing method of the embedded non-volatile memory by Example 2 of this invention. It is a 6th sectional view showing a manufacturing method of an embedded type non-volatile memory by Example 2 of this invention. It is sectional drawing of the non-volatile memory by Example 3 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Semiconductor substrate 101 Memory array area 102 Peripheral circuit area 102a, 102b Active area 110 N type ion well 112, 122 Silicon dioxide film 114 Doped polysilicon film 130 Groove type insulation structure 150 ONO stack film 151 Bottom silicon oxide film 152 Silicon nitride capture Film 153 Silicon oxide film 200 Nonvolatile memory cell 210 Access transistor 212, 312, 322 Gate oxide film 214 Access gate 216, 226, 232 P-type drain / source doped region 218 P-type lightly doped drain 220 Storage transistor 224, 314, 324, 514 Gate 310 High voltage MOS transistor 316, 326, 516 Drain / source doped region 318, 328 Low doped drain 320 Low voltage MOS transistor Jisuta 330 sidewall spacers 410, 420, 430 photoresist mask pattern 510 transistor 512 ONO dielectric film

Claims (29)

A non-volatile memory device,
A PMOS access transistor is provided in the memory array region of the nonvolatile memory device, and includes a PMOS storage transistor connected in series with the PMOS access transistor through a floating and shared P-type doped region. , Including an access gate oxide film and a P-type source doped region, and the floating and shared P-type doped region is a drain of the PMOS access transistor, and the PMOS storage transistor is a control gate, a charge storage structure, and a P-type drain doped A memory cell in which the floating and shared P-type doped region is the source of a PMOS storage transistor;
It is provided in the peripheral circuit area of the nonvolatile memory element, and includes a high voltage gate and a high voltage gate oxide film, and includes a high voltage MOS transistor in which the thickness of the high voltage gate oxide film matches the thickness of the access gate oxide film. Non-volatile memory device characterized.   2. The nonvolatile memory element according to claim 1, wherein the charge storage structure includes a lower silicon oxide film, a silicon nitride trapping film, and an upper silicon oxide film.   3. The nonvolatile memory element according to claim 2, wherein the thickness of the lower silicon oxide film is 15 to 35 angstroms.   3. The nonvolatile memory device according to claim 2, wherein the silicon nitride trapping film has a thickness of 50 to 100 angstroms.   3. The nonvolatile memory element according to claim 2, wherein the thickness of the upper silicon oxide film is 45 to 100 angstroms.   2. The nonvolatile memory device according to claim 1, wherein the access gate oxide film has a thickness of 50 to 200 angstroms.   The nonvolatile memory element according to claim 1, wherein the high-voltage gate oxide film is silicon dioxide.   The nonvolatile memory device according to claim 1, wherein the memory cell is formed on an N-type ion well. A non-volatile memory device,
A PMOS access transistor is provided in the memory array region of the nonvolatile memory device, and includes a PMOS storage transistor connected in series with the PMOS access transistor through a floating and shared P-type doped region. , Including an access gate oxide film and a P-type source doped region, and the floating and shared P-type doped region is a drain of the PMOS access transistor, and the PMOS storage transistor is a control gate, a charge storage structure, and a P-type drain doped A memory cell in which the floating and shared P-type doped region is the source of a PMOS storage transistor;
A high voltage MOS transistor provided in a peripheral circuit region of the non-volatile memory element, including a high voltage gate and a high voltage gate oxide film, of which the thickness of the high voltage gate oxide film matches the thickness of the access gate oxide film;
A non-volatile memory device comprising a gate and a MOS transistor including a charge storage structure provided in a peripheral circuit region.   The nonvolatile memory element according to claim 9, wherein the charge storage structure includes a lower silicon oxide film, a silicon nitride trapping film, and an upper silicon oxide film.   11. The nonvolatile memory element according to claim 10, wherein the thickness of the lower silicon oxide film is 15 to 35 angstroms.   11. The nonvolatile memory device according to claim 10, wherein the silicon nitride trapping film has a thickness of 50 to 100 angstroms.   11. The non-volatile memory device according to claim 10, wherein the upper silicon oxide film has a thickness of 45 to 100 angstroms.   10. The non-volatile memory device according to claim 9, wherein the access gate oxide film has a thickness of 50 to 200 angstroms.   The nonvolatile memory element according to claim 9, wherein the high-voltage gate oxide film is silicon dioxide.   The nonvolatile memory device according to claim 9, wherein the memory cell is formed on an N-type ion well. A non-volatile memory device,
A non-volatile memory device includes a PMOS storage transistor provided in a memory array region and connected in series via a PMOS access transistor and a PMOS access transistor and a floating and shared P-type doped region, and the PMOS access transistor includes an access gate, , Including an access gate oxide film and a P-type source doped region, and the floating and shared P-type doped region is a drain of the PMOS access transistor, and the PMOS storage transistor is a control gate, a charge storage structure, and a P-type drain doped A memory cell in which the floating and shared P-type doped region is the source of a PMOS storage transistor;
A high voltage MOS transistor provided in a peripheral circuit region of the non-volatile memory element, including a high voltage gate and a high voltage gate oxide film, of which the thickness of the high voltage gate oxide film matches the thickness of the access gate oxide film;
A non-volatile memory device comprising: a low-voltage gate and a low-voltage gate oxide film provided in a peripheral circuit region, wherein the low-voltage gate oxide film includes a low-voltage MOS transistor whose thickness is smaller than that of the high-voltage gate oxide film.   The low-voltage gate oxide film of the peripheral circuit is formed by performing an etching process using a photoresist mask pattern covering the memory array region and the high-voltage transistor region of the peripheral circuit, and removing an unnecessary oxide film in the low-voltage transistor region. 18. The non-volatile memory device according to claim 17, wherein the non-volatile memory device is formed by further removing the photoresist mask pattern and re-growing a gate oxide film necessary for the low-voltage transistor of the peripheral circuit.   18. The nonvolatile memory device according to claim 17, further comprising a MOS transistor provided in a peripheral circuit region and having a gate and a charge storage structure.   18. The nonvolatile memory element according to claim 17, further comprising an intermediate voltage MOS transistor provided in a peripheral circuit region and having an intermediate voltage gate and an intermediate voltage gate oxide film.   18. The nonvolatile memory device according to claim 17, wherein the charge storage structure includes a lower silicon oxide film, a silicon nitride trapping film, and an upper silicon oxide film.   The nonvolatile memory element according to claim 21, wherein the thickness of the lower silicon oxide film is 15 to 35 angstroms.   The non-volatile memory device according to claim 21, wherein the silicon nitride trapping film has a thickness of 50 to 100 angstroms.   The nonvolatile memory element according to claim 21, wherein the upper silicon oxide film has a thickness of 45 to 100 angstroms.   The nonvolatile memory device of claim 17, wherein the access gate oxide film has a thickness of 50 to 200 Å.   The non-volatile memory device of claim 17, wherein the low-pressure gate oxide film has a thickness of 15 to 100 Å.   The nonvolatile memory element according to claim 17, wherein the low-pressure gate oxide film is silicon dioxide.   The nonvolatile memory element according to claim 17, wherein the high-voltage gate oxide film is silicon dioxide.   The nonvolatile memory device of claim 17, wherein the memory cell is formed on an N-type ion well.

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