JP2007208152A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide techniques for lowering the cost of a semiconductor device and techniques for forming a well matching characteristics of a memory cell and a high-dielectric-strength MISFET. <P>SOLUTION: A resist pattern 25 is formed which covers memory cell formation regions M1 to M3 and a low-dielectric-strength MISFET formation region T, and exposes a high-dielectric-strength MISFET formation region K. This resist pattern 25 is used as a mask to form a p-type well 26 in the high-dielectric-strength MISFET formation region K. Then a channel formation region 27 is formed by using the resist pattern 25 as a mask. Further, a resist pattern is formed which covers the high-dielectric-strength MISFET formation region K and low-dielectric-strength MISFET formation region T and exposes the memory cell formation regions M1 to M3. This resist pattern is used as a mask to form a p-type well and a channel formation region in the memory cell formation regions M1 to M3. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technique effective when applied to a semiconductor device including a nonvolatile memory cell and its peripheral circuit and a manufacturing technique thereof.

  Japanese Patent Laying-Open No. 2003-37250 (Patent Document 1) discloses a semiconductor memory manufacturing method capable of obtaining a stable and high-performance peripheral circuit transistor. Specifically, a method for manufacturing a semiconductor memory in which a cell array composed of nonvolatile memory transistors and a peripheral circuit are integrated is disclosed. In this patent document, a p-type well is formed in a cell array region by performing ion implantation in a cell array region of a silicon substrate via a sacrificial oxide film, and a sacrificial oxide film is also formed in a high voltage transistor forming region of a peripheral circuit. Ion implantation is performed to form a p-type well and an n-type well for a high-voltage transistor. At this time, the p-type well formed in the cell array region and the p-type well formed in the high voltage transistor region are formed simultaneously.

Thereafter, a tunnel insulating film for the nonvolatile memory transistor is formed on the silicon substrate, and the tunnel insulating film is removed while leaving the cell array region. Then, a gate insulating film for a high voltage transistor is formed in the peripheral circuit region. Ions are implanted through this gate insulating film to form p-type wells and n-type wells for low-voltage transistors. Thereafter, a gate insulating film for a low voltage transistor is formed.
JP 2003-37250 A

  Electrically rewritable non-volatile semiconductor memory devices (semiconductor devices) can be rewritten on-board, which can shorten product development time and improve development efficiency. Applications are expanding in applications such as response and tuning by destination. Particularly in recent years, there is a great need for microcomputers with built-in EEPROM (Electrically Erasable Programmable Read Only Memory).

  Until now, an EEPROM using a polysilicon film as a charge storage film has been mainly used as an electrically rewritable nonvolatile semiconductor memory device.

  However, in an EEPROM using a polysilicon film as a charge storage film, if there is a defect in any part of the oxide film surrounding the polysilicon film, the charge storage film is a conductor. There is a problem that all the electrons that are sent out. In particular, it is considered that this problem will become more prominent when miniaturization progresses and the degree of integration increases.

Therefore, an MNOS (Metal Nitride Oxide Semiconductor) structure and a MONOS (Metal Oxide Nitride Oxide Semiconductor) structure using a silicon nitride film (Si ₃ N ₄ ) as a charge storage film instead of a polysilicon film have been proposed. In this structure, electrons are stored in the discrete trap levels of the silicon nitride film, which is an insulator. Therefore, even if a defect occurs in some part of the charge storage film and abnormal leakage occurs, All the electrons stored in the storage film will not escape. For this reason, the reliability of data retention can be improved.

  In the nonvolatile semiconductor memory device as described above, a memory cell array in which a plurality of memory cells having a MONOS structure are arranged two-dimensionally and a peripheral circuit for driving the memory cell array are formed. The peripheral circuit includes a high breakdown voltage MISFET (Metal Insulator Semiconductor Field Effect Transistor) having a relatively high breakdown voltage, and the high breakdown voltage MISFET is used for a drive circuit (decoder) of a memory cell, a booster circuit, and the like. . Although these memory cell, high withstand voltage MISFET and low withstand voltage MISFET are formed on the same semiconductor substrate, the voltage applied to the memory cell and the high withstand voltage MISFET is similar. The cell and the well of the high voltage MISFET are formed at the same time in the same process. Hereinafter, a technique for forming a well of a memory cell and a high voltage MISFET in the technique studied by the present inventors will be described.

  First, an element isolation region is formed on a semiconductor substrate using, for example, an STI method (Shallow Trench Isolation). Then, a well isolation layer is formed using a photolithography technique and an ion implantation method. Thereafter, a silicon oxide film is formed on the surface of the semiconductor substrate, and a well forming resist pattern is formed on the silicon oxide film. The well forming resist pattern is patterned to expose the memory cell formation region and the high breakdown voltage MISFET formation region and cover the other regions.

  Next, the same p-type well is simultaneously formed in the memory cell formation region and the high breakdown voltage MISFET formation region by ion implantation using the well formation resist pattern as a mask. Subsequently, after removing the well formation resist pattern, a first channel formation region resist pattern for forming a channel formation region of the high breakdown voltage MISFET is formed. The resist pattern for the first channel formation region exposes only the high breakdown voltage MISFET formation region and covers the other regions. Then, a channel formation region of the high breakdown voltage MISFET is formed by ion implantation using the resist pattern for the first channel formation region as a mask.

  Next, after removing the resist pattern for the first channel formation region, a resist pattern for the second channel formation region for forming the channel formation region of the memory cell is formed on the semiconductor substrate. The resist pattern for the second channel formation region exposes only the memory cell formation region and covers the other regions. Then, the channel formation region of the memory cell is formed by ion implantation using the second channel formation region resist pattern as a mask.

  Thus, in order to form the well and channel forming region of the memory cell, the high voltage MISFET, three different resist patterns are required. However, in order to reduce the cost of the semiconductor device, it is required to reduce the number of resist patterns. Further, in the technique studied by the present inventors, the well of the memory cell and the high voltage MISFET are formed in the same process. That is, the well of the memory cell and the well of the high voltage MISFET are the same. For this reason, there is a problem that it is impossible to individually form an optimum well suitable for the characteristics of the memory cell or the high breakdown voltage MISFET.

  An object of the present invention is to provide a technique capable of reducing the cost of a semiconductor device. Another object of the present invention is to provide a technique capable of forming wells that match the characteristics of a memory cell and a high voltage MISFET.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A method for manufacturing a semiconductor device according to the present invention includes a memory cell formed in a first region of a semiconductor substrate, a high breakdown voltage MISFET formed in a second region of the semiconductor substrate, and a third of the semiconductor substrate. The present invention relates to a method for manufacturing a semiconductor device having a low breakdown voltage MISFET having a relatively low breakdown voltage formed in a region. And (a) a step of forming a first well of the memory cell, and (b) a step of forming a second well of the high breakdown voltage MISFET, wherein the step (a) and the step (b) are different. It is characterized by being implemented in a process.

  According to the method of manufacturing a semiconductor device of the present invention, a well is formed in the semiconductor substrate by (a) a step of forming a resist pattern on the semiconductor substrate and (b) ion implantation using the resist pattern as a mask. With the process. And (c) forming a channel formation region by ion implantation using the resist pattern used as a mask when forming the well.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: a memory cell formed in a first region of a semiconductor substrate; a high breakdown voltage MISFET formed in a second region of the semiconductor substrate; The present invention relates to a method of manufacturing a semiconductor device having a low breakdown voltage MISFET having a relatively low breakdown voltage formed in a third region. And (a) a step of forming an insulating film on the semiconductor substrate; and (b) a first resist that covers the memory cell formation region and the low breakdown voltage MISFET formation region on the insulating film and exposes the high breakdown voltage MISFET formation region. Forming a pattern. And (c) forming a second well of the high voltage MISFET in the semiconductor substrate by ion implantation using the first resist pattern as a mask, and (d) using the second well formed. Forming a channel formation region of the high voltage MISFET in the semiconductor substrate by ion implantation using the first resist pattern as a mask. (E) removing the first resist pattern; and (f) exposing the memory cell formation region on the semiconductor substrate and covering the low breakdown voltage MISFET formation region and the high breakdown voltage MISFET formation region. Forming a resist pattern. And (g) forming a first well of the memory cell in the semiconductor substrate by ion implantation using the second resist pattern as a mask. And (h) forming a channel formation region of the memory cell in the semiconductor substrate by ion implantation using the second resist pattern used for forming the first well as a mask, and (i) the first 2 removing the resist pattern.

  A semiconductor device according to the present invention includes a memory cell formed in a first region of a semiconductor substrate, a high breakdown voltage MISFET formed in a second region of the semiconductor substrate, and a low breakdown voltage MISFET formed in a third region of the semiconductor substrate. The present invention relates to a semiconductor device having the same. (A) a first well of the memory cell; and (b) a second well of the high breakdown voltage MISFET, wherein the impurity concentration of the first well and the impurity concentration of the second well are different.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  Since the well and channel formation region of the memory cell and the well and channel formation region of the high breakdown voltage MISFET can be formed with two different resist patterns, the manufacturing cost of the semiconductor device can be reduced. Further, since the well of the memory cell and the well of the high breakdown voltage MISFET are formed separately, a well suitable for the characteristics of the memory cell and the high breakdown voltage MISFET can be formed. For this reason, the performance of the semiconductor device can be improved.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, it is substantially the same. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

  In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
The first embodiment is a semiconductor device having a low breakdown voltage MISFET (Metal Insulator Semiconductor) that is driven at a relatively low voltage and a high breakdown voltage MISFET that is driven at a relatively high voltage to enable high voltage drive. Thus, the present invention is applied to a semiconductor device including a rewritable nonvolatile memory cell and a manufacturing method thereof. In the MISFET, the breakdown voltage refers to a pn junction breakdown voltage generated at the boundary between the source region and the semiconductor substrate (well) or the drain region and the semiconductor substrate (well) constituting the MISFET, or a breakdown voltage of the gate insulating film. In the first mode, a high breakdown voltage MISFET having a relatively high breakdown voltage and a low breakdown voltage MISFET having a relatively low breakdown voltage are formed on a semiconductor substrate.

  The structure of the semiconductor device in the embodiment will be described with reference to FIGS.

  FIG. 1 is a top view showing a layout configuration of each element formed on a chip (semiconductor substrate) 1. In FIG. 1, a chip 1 includes a CPU (Central Processing Unit) 2, a ROM (Read Only Memory) 3, a RAM (Random Access Memory) 4, an EEPROM (Electrically Erasable Programmable Read Only Memory) 5, an analog circuit 6, and an electrostatic protection. Circuits 7a to 7g are included.

  The CPU (circuit) 2 is also called a central processing unit and is the heart of a computer or the like. The CPU 2 reads and decodes instructions from the storage device, and performs a wide variety of operations and controls based on the instructions, and requires high processing speed. Accordingly, the MISFET constituting the CPU 2 requires a relatively large current driving force among the elements formed on the chip 1. That is, it is formed of a low breakdown voltage MISFET.

  A ROM (circuit) 3 is a memory in which stored information is fixed and cannot be changed, and is called a read-only memory. The configuration of the ROM 3 includes a NAND type in which MISFETs are connected in series and a NOR type in which MISFETs are connected in parallel. The NAND type emphasizes integration density, whereas the NOR type is often used for the purpose of focusing on operation speed. Since this ROM 3 is also required to operate at high speed, the MISFET constituting the ROM 3 requires a relatively large current driving force. That is, it is formed of a low breakdown voltage MISFET.

  The RAM (circuit) 4 is a memory that can read stored information at random, that is, read stored information at any time, or write new stored information, and is also called a memory that can be written and read at any time. There are two types of RAM as an IC memory: DRAM (Dynamic RAM) using a dynamic circuit and SRAM (Static RAM) using a static circuit. DRAM is an occasional writing / reading memory that requires a memory holding operation, and SRAM is an occasional writing / reading memory that does not require a memory holding operation. Since these RAMs 3 are also required to operate at high speed, the MISFETs constituting the RAMs 3 require a relatively large current driving force. That is, it is formed of a low breakdown voltage MISFET.

  The EEPROM 5 is a kind of non-volatile memory that can be electrically rewritten for both writing and erasing operations, and is also called an electrically erasable programmable read-only memory. The memory cell of the EEPROM 5 is composed of, for example, a MONOS (Metal Oxide Nitride Oxide Semiconductor) type transistor or a MNOS (Metal Nitride Oxide Semiconductor) type transistor for storage (memory). For example, hot electron injection or Fowler-Nordheim tunneling is used for the writing operation of the EEPROM 5, and Fowler-Nordheim tunneling or hot hole injection is used for the erasing operation. Of course, hot electron injection and hot hole injection may be reversed.

  A high potential difference (about 12 V) is generated in the memory MONOS transistor during the writing operation of the EEPROM 5 or the like, so that a relatively high breakdown voltage transistor is required as the memory MONOS transistor.

  The analog circuit 6 is a circuit that handles a voltage or current signal that changes continuously in time, that is, an analog signal, and includes, for example, an amplifier circuit, a conversion circuit, a modulation circuit, an oscillation circuit, and a power supply circuit. The analog circuit 6 uses a high breakdown voltage MISFET having a relatively high breakdown voltage among the elements formed on the chip 1.

  The electrostatic protection circuits 7a to 7g are circuits provided at external terminals in order to prevent the internal circuits from being destroyed by the voltage or heat generated by the discharge of the charged charges in the elements and insulating films. Examples of the charged electric charge include those caused by static electricity accumulated in a human body or an object. The electrostatic protection circuits 7a and 7c are provided at the input / output terminals, and the electrostatic protection circuit 7b is provided at the monitor terminal. The electrostatic protection circuit 7d is provided at the Vss terminal, and the electrostatic protection circuit 7e is provided at the CLK (clock) terminal. Furthermore, the electrostatic protection circuit 7f is provided at an RST (reset) terminal, and the electrostatic protection circuit 7g is provided at a Vcc terminal. Since a high voltage is applied to the electrostatic protection circuits 7a and 7c to 7g, a relatively high withstand voltage high voltage MISFET is used among the elements formed on the chip 1.

  Next, FIG. 2 shows an example of the internal configuration of the EEPROM 5 shown in FIG. 2, the EEPROM 5 has a memory array 10 and a direct peripheral circuit section 11 and an indirect peripheral circuit section 12 of the memory array 10 as drive circuits for driving the memory array.

  The memory array 10 corresponds to a storage unit of the EEPROM 5, and a large number of memory cells are arranged two-dimensionally in the vertical and horizontal directions. The memory cell is a circuit for storing 1-bit unit information, and is composed of a MONOS transistor that is a storage unit.

  The drive circuit is a circuit for driving the memory array 10, and as the direct peripheral circuit unit 11, for example, a booster circuit that generates a voltage several times from the power supply voltage, a booster clock generator circuit, a voltage clamp circuit, a row, A column decoder, a row decoder, a column latch circuit, a WELL control circuit, and the like for selecting a column are included. The MISFET constituting the direct peripheral circuit section 11 is formed of a high breakdown voltage MISFET that requires a relatively high breakdown voltage among the elements formed on the chip 1.

  The indirect peripheral circuit unit 12 is formed as a memory array rewrite control circuit, and includes a circuit having a setting circuit, a normal rewrite clock generation circuit, a high-speed rewrite clock generation circuit, a rewrite timing control circuit, and the like. The MISFET constituting the indirect peripheral circuit section 12 is formed of a low withstand voltage MISFET that is driven at a relatively low voltage among the elements formed on the chip 1 and is capable of high-speed operation.

Next, FIG. 3 shows a cross-sectional view of the MONOS transistors Q _{1 to} Q ₃ , the high voltage MISFET Q ₄ and the low voltage MISFET Q ₅ formed on the chip 1. 3, a memory cell forming region M1~M3 is, EEPROM shows a plurality of memory cell formation region of the (rewritable nonvolatile memory) 5, MONOS type transistor _Q 1 to Q ₃ are formed. High voltage MISFET formation region K is a region where high-voltage MISFET Q ₄ is formed, is considered for example formation region of the analog circuit 6, a region driving circuit (such as a decoder) is formed in EEPROM5 is . The high-voltage MISFET Q _4, for example, operate with the supply voltage of about 5V. The low breakdown voltage MISFET formation region T indicates a region where the low-voltage MISFET Q ₅ that requires a large current driving force in order to enable high-speed operation is formed. Such regions low breakdown voltage MISFET Q ₅ is formed, for example, forming regions of the CPU2 or RAM4 is considered. This low withstand voltage MISFET operates with a power supply voltage of about 1.5V, for example.

  An element isolation region 21 for isolating elements is formed on the semiconductor substrate 20 in the chip 1, and the active regions isolated by the element isolation region 21 are the memory cell formation regions M1 to M3 and the high breakdown voltage MISFET formation region, respectively. K and the low breakdown voltage MISFET formation region T.

  In FIG. 3, n-type semiconductor regions 22 used for well isolation layers are formed in the memory cell formation regions M1 to M3 of the semiconductor substrate 20. A p-type well (first well) 29 is formed on the n-type semiconductor region 22. The same p-type well 29 is formed in the memory cell formation regions M1 to M3, but the rightmost memory cell formation region M3 and the other two memory cell formation regions M1 among the memory cell formation regions M1 to M3. , M2 are separated by a well isolation layer (well isolation region B) 23 made of, for example, an n-type semiconductor region. That is, in the first embodiment, in the memory array including the plurality of memory cell formation regions M1 to M3, for example, the p-type well 29 is separated by the well isolation layer 23 for each byte unit. However, the p-type well 29 separated by the well separation layer 23 is the same. That is, the p-type wells 29 formed in the plurality of memory cell formation regions M1 to M3 are formed with the same impurity concentration.

  Of the three memory cell formation regions M1 to M3, the leftmost memory cell formation region M1 and the central memory cell formation region M2 are formed by a common p-type well 29, and these memory cell formation regions M1 , M2 is formed with a well power supply region A for supplying power to the p-type well 29. A p-type semiconductor region 53 is formed in the well power feeding region A.

Next, an n-type semiconductor region 22 used for a well isolation layer is formed in the high breakdown voltage MISFET formation region K of the semiconductor substrate 20, and a p-type well (second well) 26 is formed on the n-type semiconductor region 22. Is formed. The p-type well 26 is different from the p-type well 29 formed in the memory cell formation regions M1 to M3. That is, the impurity concentration of the p-type well 26 formed in the high breakdown voltage MISFET formation region K is different from the impurity concentration of the p-type well 29 formed in the memory cell formation regions M1 to M3. This is one of the features of the present invention. As a result, the p-type well 29 of the MONOS transistors Q _{1 to} Q ₃ and the p-type well 26 of the high breakdown voltage MISFET Q ₄ can be individually formed with an optimum impurity concentration. Therefore, it is possible to form a well having an optimum impurity concentration that fully draws out the performance of each transistor.

Conventionally, the p-type well 29 in the MONOS transistors Q _{1 to} Q ₃ and the p-type well 26 in the high-breakdown-voltage MISFET Q ₄ are similar in applied voltage, and thus are formed in the same process and have the same impurity concentration. Was. However, if the p-type well 29 of the MONOS transistors Q _{1 to} Q ₃ and the p-type well 26 of the high breakdown voltage MISFET Q ₄ are formed with the same impurity concentration, it is not possible to realize further higher performance of the individual transistors. There is a problem. Therefore, in the first embodiment, the p-type well 29 of the MONOS transistors Q _{1 to} Q ₃ and the p-type well 26 of the high breakdown voltage MISFET Q ₄ are formed with different impurity concentrations. Thereby, further enhancement of performance of each transistor can be realized. Specifically, by making the impurity concentration of the p-type well 29 larger than the impurity concentration of the p-type well 26, further enhancement of performance of each transistor can be achieved. That is, in order to optimize the threshold voltage of the MONOS transistor _Q 1 to Q ₃ is an impurity concentration of the p-type well 29 of the MONOS type transistor _Q 1 to Q ₃ in the p-type well 26 of the high voltage MISFET Q ₄ It needs to be higher than that. In addition, since it is necessary to reduce the leakage current between the memory cells, it is necessary to increase the impurity concentration of the p-type well 29 immediately below the element isolation region 21 that separates the memory cells. For this reason, when the value is larger than the impurity concentration of the p-type well 26 with an impurity concentration of the p-type well 29 in the MONOS type transistor _Q 1 to Q ₃ in the high-voltage MISFET Q _4, a MONOS type transistor _Q 1 to Q ₃ We are trying to improve performance.

  Furthermore, as will be described later, in the first embodiment in which the p-type well 29 and the p-type well 26 are formed in separate steps, compared to the case where the p-type well 29 and the p-type well 26 are formed in common. Since the mask used in the manufacturing process can be reduced, the manufacturing cost of the semiconductor device can be reduced.

Next, an n-type semiconductor region 22 used for a well isolation layer is formed in the low breakdown voltage MISFET formation region T of the semiconductor substrate 20, and a p-type well (third well) 37 is formed on the n-type semiconductor region 22. Is formed. The p-type well 37 is formed with a different impurity concentration from the p-type well 29 formed in the memory cell formation regions M1 to M3 and the p-type well 26 formed in the high breakdown voltage MISFET formation region K. This is because such a voltage applied to the low-voltage MISFET Q ₅ is different from the voltage applied to the MONOS type transistor _Q 1 to Q ₃ and the high-voltage MISFET Q _4.

Next, the configuration of the MONOS transistors Q _{1 to} Q ₃ shown in FIG. 3 will be described.

First, the MONOS transistors Q _{1 to} Q ₃ formed in the memory cell formation regions M _{1 to} M ₃ have the following configuration. That is, a gate insulating film (first potential barrier film) 31 is formed on a p-type well 29 formed in the semiconductor substrate 20, and a charge storage film 32 is formed on the gate insulating film 31. An insulating film (second potential barrier film) 33 is formed on the charge storage film 32, and a gate electrode 34 made of a conductive film is formed on the insulating film 33. The gate electrode 34 is made of, for example, a polysilicon film, and sidewalls 48 made of, for example, an insulating film are formed on the sidewalls on both sides of the gate electrode 34 in order to form an LDD (Lightly Doped Drain) structure.

  In the semiconductor substrate 20 below the sidewall 48, a low concentration n-type impurity diffusion region 45 and a high concentration n-type impurity diffusion region 50 are formed as semiconductor regions. A channel formation region 30 made of an n-type semiconductor region is formed in the p-type well 29 immediately below the gate insulating film 31.

In the MONOS transistors Q _{1 to} Q ₃ configured as described above, the gate insulating film 31 is formed of, for example, a silicon oxide film, and also has a function as a tunnel insulating film. For example, the MONOS transistors Q _{1 to} Q ₃ inject electrons from the semiconductor substrate 20 into the charge storage film 32 via the gate insulating film 31, and discharge electrons stored in the charge storage film 32 to the semiconductor substrate 20. In order to store and erase data, the gate insulating film 31 functions as a tunnel insulating film.

  The charge storage film 32 is a film provided to store charges that contribute to data storage, and is formed of, for example, a silicon nitride film.

  Conventionally, a polysilicon film has been mainly used as the charge storage film 32, but when a polysilicon film is used as the charge storage film 32, there is a defect in some part of the oxide film surrounding the charge storage film 32. Since the charge storage film 32 is a conductor, all charges stored in the charge storage film 32 may be lost due to abnormal leakage.

  Therefore, as described above, a silicon nitride film that is an insulator has been used as the charge storage film 32. In this case, charges that contribute to data storage are accumulated in discrete trap levels (capture levels) existing in the silicon nitride film. Therefore, even if a defect occurs in a part of the oxide film surrounding the charge storage film 32, since charges are stored at discrete trap levels of the charge storage film 32, all charges are transferred from the charge storage film 32. There is no escape. For this reason, the reliability of data retention can be improved.

  For this reason, not only the silicon nitride film but also a film including discrete trap levels can be used as the charge storage film 32 to improve data retention reliability.

The side wall 48 is formed so that the source region and the drain region, which are semiconductor regions of the MONOS transistors Q _{1 to} Q ₃ , have an LDD structure. That is, the source region and the drain region of the MONOS transistors Q _{1 to} Q ₃ are formed by the low-concentration n-type impurity diffusion region 45 and the high-concentration n-type impurity diffusion region 50. At this time, the source region and the drain region under the side wall 48 are the low-concentration n-type impurity diffusion region 45 so that the electric field concentration under the end of the gate electrode 34 can be suppressed.

Next, the configuration of the high voltage MISFET Q ₄ shown in FIG. 3 will be described. In the high voltage MISFET Q ₄ , a gate insulating film 39 is formed on the p-type well 26 formed in the semiconductor substrate 20, and a gate electrode 41 is formed on the gate insulating film 39. The gate insulating film 39 is made of, for example, a silicon oxide film, and the gate electrode 41 is made of, for example, a polysilicon film.

  Sidewalls 48 are formed on the side walls on both sides of the gate electrode 41. In the semiconductor substrate 20 below the sidewalls 48, low-concentration n-type impurity diffusion regions 46 and high-concentration n-type impurities are formed as semiconductor regions. A diffusion region 51 is formed. A channel formation region 27 made of a p-type semiconductor region is formed in the p-type well 26 immediately below the gate insulating film 31.

Next, the configuration of the low voltage MISFET Q ₅ shown in FIG. In the low breakdown voltage MISFET Q ₅ , a gate insulating film 40 is formed on a p-type well 37 formed in the semiconductor substrate 20, and a gate electrode 43 is formed on the gate insulating film 40. The gate insulating film 40 is made of, for example, a silicon oxide film, and the gate electrode 43 is made of, for example, a polysilicon film.

  Side walls 49 are formed on the side walls on both sides of the gate electrode 43, and a low concentration n-type impurity diffusion region 47 and a high concentration n-type impurity are formed as semiconductor regions in the semiconductor substrate 20 below the side walls 49. A diffusion region 52 is formed. A channel formation region 38 made of a p-type semiconductor region is formed in the p-type well 37 directly below the gate insulating film 40.

It will be described as high-voltage MISFET Q ₄ the differences of the low voltage MISFET Q _5. First, the width of the side walls 48 of the high voltage MISFET Q ₄ is wider than the width of the side wall 49 of the low voltage MISFET Q _5. Since a relatively high potential difference (about 5 V) is applied to the high breakdown voltage MISFET Q ₄ during operation, the width of the sidewall 48 is relatively widened to increase the pn between the source / drain region and the semiconductor substrate (p-type well 26). This is because it is necessary to improve the junction breakdown voltage. On the other hand, the low breakdown voltage MISFET Q _5, because it is not relatively low potential (about 1.5V) only applied during the operation, so as to improve high speed of operation and the width of the side wall 49 relatively narrow.

The gate length of the gate electrode 41 in the high-voltage MISFET Q ₄ is longer than the gate length of the gate electrode 43 in the low-voltage MISFET Q _5. In the low-voltage MISFET Q _5, by shortening the gate length of the gate electrode 43, reducing the resistance between the source region and the drain region, it is necessary to improve the current driving force. On the other hand, the high-voltage MISFET Q _4, since a relatively high potential is applied, shortening the gate length is because the punch-through occurs between the source region and the drain region.

Further, since a high voltage is applied to the high breakdown voltage MISFET Q ₄ compared to the low breakdown voltage MISFET Q ₅ , the gate insulating film 39 is thicker than the gate insulating film 40 of the low breakdown voltage MISFET Q ₅ . Thereby, thereby improving the dielectric strength of the gate insulating film 39 of the high voltage MISFET Q _4.

On the MONOS transistors Q _{1 to} Q ₃ , the high breakdown voltage MISFET Q ₄ and the low breakdown voltage MISFET Q ₅ configured as described above, an interlayer insulating film made of the silicon nitride film 54 and the silicon oxide film 55 is formed. A contact hole 56 is formed in the interlayer insulating film, and a plug 57 is formed so as to fill the contact hole 56. The plug 57 is formed of a barrier film made of, for example, a titanium / titanium nitride film and a tungsten film. A wiring 58 made of, for example, an aluminum film or an aluminum alloy film is formed on the interlayer insulating film on which the plug 57 is formed.

In FIG. 3, n-channel MISFETs are shown as the high breakdown voltage MISFET Q ₄ and the low breakdown voltage MISFET Q ₅ , but p-channel MISFETs are also formed (not shown).

  The semiconductor device according to the first embodiment is configured as described above, and the operation of a memory cell (nonvolatile memory cell) included in the semiconductor device will be described with reference to the drawings.

  FIG. 4 is an explanatory diagram showing an example of the memory array structure and operating conditions (1 cell / 1 transistor) of the EEPROM 5 shown in FIG. Each memory cell shown in FIG. 4 is an example in which the memory cell includes only a memory transistor that accumulates charges.

  The memory cell is composed of a MONOS type transistor shown in FIG. 3, and constitutes cell transistors CT1 to CT8 as shown in FIG. The gate electrodes of the cell transistors CT1 to CT8 are connected to the word lines WL1 to WL2, and the source regions are connected to the source lines SL1 to SL4. The drain region is connected to the data lines DL1 to DL4. Further, the back gates of the cell transistors CT1-2, CT5-6 are connected to the well WE1, and the back gates of the cell transistors CT3-4, CT7-8 are connected to the well WE2.

  FIG. 4 shows a case where memory cells are arranged in 2 rows and 4 columns for the sake of simplicity. However, the present invention is not limited to this. In reality, more memory cells are arranged in a matrix. Arranged to constitute a memory array. In FIG. 4, the memory cell array on the same well and the same word line has, for example, a two-column configuration of cell transistors CT1-2. A transistor is formed. In this case, the memory cell is erased and written in units of 1 byte.

  Next, erase, write, and read operations of the 1-cell 1-transistor memory cell will be described with reference to FIG.

  First, the erase operation will be described. For example, consider a case where data stored in the cell transistors CT1 and CT2 is erased as a memory cell (selected memory cell) from which data is erased. The potential of the selected well WE1 is 1.5V, the potential of the word line WL1 is -8.5V, the potential of the source lines SL1-2 is 1.5V, and the data lines DL1-2 are floated. Then, the charges accumulated in the charge accumulation films of the cell transistors CT1 and CT2 are extracted to the semiconductor substrate side, and data is erased. For other memory cells (non-selected memory cells) CT3 to 8 that are not erased, the potential of the well WE2 not selected is −8.5V, the potential of the word line WL2 is 1.5V, and the source lines SL3 to 4 The potential is 1.5 V, and the potentials of the data lines DL3 to DL4 are made floating. As a result, the charges stored in the charge storage films of the cell transistors CT3 to 8 do not escape and are not erased.

  Next, the write operation will be described. For example, consider a case where data is written to the cell transistor CT1 as a memory cell (selected memory cell) to which data is written. The potential of the selected well WE1 is set to -10.5V, the potential of the word line WL1 is set to 1.5V, the potential of the source line SL1 is set to -10.5V, and the data line DL1 is floated. Then, charges are injected into the charge storage film of the cell transistor CT1, and data is written. At this time, for the other memory cells (non-selected memory cells) CT2 to 8 which are not written, the potential of the unselected well WE2 is -10.5V, the potential of the word line WL2 is -10.5V, and the source line SL2 4 is set to 1.5 V, and the potentials of the data lines DL2 to DL4 are floated. This prevents charge from being injected into the charge storage films of the cell transistors CT2-8.

  Next, the reading operation will be described. For example, it is assumed that data “1” is written in the cell transistor CT1 and the threshold voltage of the transistor is high, and data “0” is stored in the cell transistor CT2 and the threshold voltage of the transistor is low. When reading data from the cell transistors CT1-2, the potential of the selected well WE1 is -2V, the potential of the word line WL1 is 0V, the potential of the source lines SL1-2 is 0V, and the potential of the data lines DL1-2 is 1V. To do. Thereby, the data of the cell transistors CT1 and CT2 are read out. In this case, since the threshold voltage of the cell transistor CT1 is high and the threshold voltage of the cell transistor CT2 is low, the potential of the data line DL1 does not change and the potential of the data line DL2 decreases. For the other cell transistors CT3 to 8 that are not read, the potential of the unselected well WE2 is -2V, the potential of the word line WL2 is -2V, the potential of the source lines SL3-4 is 0V, and the data lines DL3-4 Is set to 0V so that the cell transistors CT3 to CT8 are not turned on. By reducing the back gate potential of the non-selected memory cell at the time of reading, a selection transistor is not required for the memory cell.

  Next, a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to the drawings.

  First, as shown in FIG. 5, a semiconductor substrate 20 in which a P-type impurity such as boron (B) is introduced into, for example, single crystal silicon is prepared. Next, an element isolation region 21 is formed on the main surface of the semiconductor substrate 20. The element isolation region 21 is made of, for example, a silicon oxide film, and is formed by an STI (Shallow Trench Isolation) method, a LOCOS (Local Oxidization Of Silicon), or the like. FIG. 5 shows an element isolation region 21 formed by the STI method in which a silicon oxide film is embedded in a groove formed in the semiconductor substrate 20.

  Subsequently, as shown in FIG. 6, an n-type semiconductor region 22 called NiSO is formed in the semiconductor substrate 20 using a photolithography technique and an ion implantation method. The n-type semiconductor region 22 is formed by introducing an n-type impurity such as phosphorus (P) or arsenic (As) into the semiconductor substrate 20.

  Next, as shown in FIG. 7, a well isolation layer 23 for isolating the well is formed by using a photolithography technique and an ion implantation method. The well isolation layer 23 is formed from a p-type semiconductor region into which a p-type impurity such as boron (B) is introduced.

  Subsequently, as shown in FIG. 8, an insulating film 24 made of a silicon oxide film is formed on the semiconductor substrate 20 by using, for example, a thermal oxidation method, and then a resist film is applied on the insulating film 24. Then, a resist pattern (first resist pattern) 25 is formed by performing exposure / development processing on the resist film. The resist pattern 25 is patterned so as to cover the memory cell formation regions M1 to M3 and the low breakdown voltage MISFET formation region T and to expose the high breakdown voltage MISFET formation region K. Since this resist pattern 25 is used as a mask when forming a well as will be described later, the film thickness is large. For example, the film thickness is 2 μm or more and 3 μm or less.

Thereafter, a p-type well 26 is formed in the high breakdown voltage MISFET formation region K by ion implantation using the resist pattern 25 as a mask. The p-type well 26 is formed by introducing a p-type impurity such as boron, and has an impurity concentration of 2 × 10 ¹² / cm ³ , for example. In this step, since the p-type well 26 is formed only in the high breakdown voltage MISFET formation region K, the p-type well 26 can be formed with an impurity concentration optimum for the characteristics of the high breakdown voltage MISFET. For this reason, the characteristics of the high voltage MISFET can be improved.

Next, the channel formation region 27 is formed on the surface of the high breakdown voltage MISFET formation region K using the resist pattern 25 used to form the p-type well 26 as it is. The channel formation region 27 is formed, for example, by introducing a p-type impurity such as boron by an ion implantation method. By forming the channel formation region 27, the threshold voltage of the high voltage MISFET can be adjusted. The concentration of the p-type impurity introduced to form the channel formation region 27 is, for example, 1 × 10 ¹² / cm ³ .

  In the first embodiment, the p-type well 26 is formed using the resist pattern 25 that exposes only the high breakdown voltage MISFET formation region K. Therefore, the channel formation region 27 of the high breakdown voltage MISFET can be formed using the resist pattern 25 as it is. This is one of the features of the present invention. Since the formation of the p-type well 26 and the channel formation region 27 can be formed with one mask, the number of masks used in the manufacturing process can be reduced, and the manufacturing cost can be reduced. Reduction is possible.

  The p-type well 26 can be formed by injecting a plurality of times (for example, four times) while changing the implantation energy of the p-type impurity. Since the p-type well 26 is formed even inside the semiconductor substrate 20, the energy to be injected becomes high. For this reason, the thickness of the resist pattern 25 is increased so that p-type impurities are not introduced into the region covered with the resist pattern 25. Here, the resist pattern 25 is also used for forming the channel formation region 27 after the p-type well 26 is formed. In the ion implantation used for forming the channel formation region 27, the energy for implanting the p-type impurity is lower than that in the case of forming the p-type well 26, and therefore there is no problem even if the resist pattern 25 is used.

  Next, as shown in FIG. 9, after removing the resist pattern 25, a new resist film is applied on the insulating film 24. Then, a resist pattern (second resist pattern) 28 is formed by subjecting the applied resist film to exposure / development processing. The resist pattern 28 is patterned so as to expose the memory cell formation regions M1 to M3 and cover the high breakdown voltage MISFET formation region K and the low breakdown voltage MISFET formation region T. Further, the well isolation region A is also covered. Since this resist pattern 28 is also used as a mask for forming wells, the film thickness is large. For example, the film thickness is 2 μm or more and 3 μm or less.

Subsequently, a p-type well 29 is formed in the memory cell formation regions M1 to M3 by ion implantation using the resist pattern 28 as a mask. The p-type well 29 is formed by introducing a p-type impurity such as boron, for example, and the impurity concentration is 4 × 10 ¹² / cm ³ , for example. As described above, the impurity concentration of the p-type well 29 formed in the memory cell formation regions M1 to M3 is higher than the impurity concentration of the p-type well 26 formed in the high breakdown voltage MISFET formation region K. Thus, by increasing the impurity concentration of the p-type well 29 as compared with the impurity concentration of the p-type well 26, the threshold voltage of the MONOS transistor formed in the memory cell formation regions M1 to M3 is optimized. be able to. In addition, since the impurity concentration of the p-type well 29 immediately below the element isolation region 21 that isolates the memory cells can be increased, the leakage current between the memory cells can be reduced. That is, by making the impurity concentration of the p-type well 29 higher than the impurity concentration of the p-type well 26, the performance of the MONOS transistor constituting the memory cell can be improved. This can be realized by separately forming the p-type well 29 formed in the memory cell formation regions M1 to M3 and the p-type well 26 formed in the high breakdown voltage MISFET formation region K as shown in the first embodiment. Is. Therefore, according to the first embodiment, the performance of the MONOS transistor and the high breakdown voltage MISFET can be improved.

Next, the channel formation region 30 is formed on the surfaces of the memory cell formation regions M1 to M3 using the resist pattern 28 used to form the p-type well 29 as it is. The channel forming region 30 is formed by introducing an n-type impurity such as phosphorus or arsenic by ion implantation. By forming the channel formation region 30, it is possible to adjust the threshold voltage of the MONOS transistor constituting the memory cell. The concentration of the n-type impurity introduced to form the channel formation region 30 is, for example, 1 × 10 ¹² / cm ³ . The reason why the n-type impurity is introduced into the channel formation region 30 is to reduce the threshold voltage to about 0V.

  In this way, the p-type well 29 and the channel formation region 30 can be formed in the memory cell formation regions M1 to M3. In the first embodiment, the p-type well 26 and the channel formation region 27 are formed in the high breakdown voltage MISFET formation region K using the resist pattern 25, and the p-type well is formed in the memory cell formation regions M1 to M3 using the resist pattern 28. 29 and a channel forming region 30 are formed. That is, the p-type well 29 and the channel formation region 30 are formed in the memory cell formation regions M1 to M3 using two different types of resist patterns, and the p-type well 26 and the channel formation region 27 are formed in the high breakdown voltage MISFET formation region K. Forming. Therefore, the number of masks can be reduced and the manufacturing cost of the semiconductor device can be reduced as compared with the conventional technique using three different types of resist patterns for forming the p-type well and the channel formation region. it can. That is, according to the first embodiment, the performance of the MONOS transistor and the high breakdown voltage MISFET can be improved, and the manufacturing cost can be reduced.

  A conventional technique using three different resist patterns for comparison will be described below. First, an insulating film is formed on a semiconductor substrate, and a well forming resist pattern is formed on the insulating film. This well formation resist pattern is a first mask, and is patterned so as to expose the memory cell formation region and the high breakdown voltage MISFET formation region. Then, a common p-type well is formed in the memory cell formation region and the high breakdown voltage MISFET formation region by ion implantation using the well forming resist pattern as a mask. Next, for example, the first channel formation region is formed in the high breakdown voltage MISFET formation region. The well formation resist pattern used when forming the p-type well exposes the memory cell formation region and the high breakdown voltage MISFET formation region. Therefore, it cannot be used as it is because p-type impurities are also introduced into the memory cell formation region. Therefore, after removing the well forming resist pattern, a new first channel forming resist pattern is formed. This resist pattern for forming the first channel is a second mask, and is patterned so as to cover the memory cell formation region and expose only the high breakdown voltage MISFET formation region. Then, the first channel formation region is formed in the high breakdown voltage MISFET formation region by ion implantation using the first channel formation resist pattern as a mask. Next, a second channel formation region is formed in the memory cell formation region. The first channel formation resist pattern covers the memory cell formation region and exposes the high breakdown voltage MISFET formation region. It cannot be used for ion implantation. Therefore, after removing the first channel forming resist pattern formed on the insulating film, a new second channel forming resist pattern is formed. This resist pattern for forming the second channel is a third mask, and is patterned so as to cover the high breakdown voltage MISFET formation region and expose only the memory cell formation region. Then, a second channel formation region is formed in the memory cell formation region by ion implantation using the second channel formation resist pattern as a mask. In this manner, the p-type well, the first channel formation region, and the second channel formation region can be formed in the memory cell formation region and the high breakdown voltage MISFET formation region using three different types of resist patterns.

  On the other hand, according to the first embodiment, the p-type wells 26 and 29 and the channel formation region 27 are formed in the memory cell formation regions M1 to M3 and the high breakdown voltage MISFET formation region K with two different types of masks as described above. 30 can be formed, so that the manufacturing cost can be reduced. The reason why the mask can be reduced in the first embodiment is that different p-type wells 26 and 29 are formed using different masks in the memory cell formation regions M1 to M3 and the high breakdown voltage MISFET formation region K. This is because the channel forming regions 27 and 30 are formed using the individual masks used for forming the p-type wells 26 and 29 as they are. That is, one of the features in the first embodiment is that the p-type well 26 and the channel formation region 27 or the p-type well 29 and the channel formation region 30 are formed with the same resist pattern. From the viewpoint of forming the p-type wells 26 and 29, if a common p-type well is formed as in the prior art, it can be formed with one mask. On the other hand, when the p-type well 29 in the memory cell formation regions M1 to M3 and the p-type well 26 in the high breakdown voltage MISFET formation region K are separately formed as in the first embodiment, two masks are required. . However, considering the process of forming the channel formation region, in the conventional technique, it is necessary to form the channel formation region separately in the memory cell formation region and the high breakdown voltage MISFET formation region. A total of three masks are required. On the other hand, in the first embodiment, since the p-type wells 26 and 29 are formed separately, each mask can be used for forming a channel formation region. Therefore, a total of two masks are sufficient even including the step of forming the channel formation region. For this reason, in the first embodiment, by separately forming the p-type wells 26 and 29, the performance of the MONOS transistor and the high breakdown voltage MISFET can be improved, and the p-type wells 26 and 29 and By forming the channel formation regions 27 and 30 with the same mask, the mask can be reduced and the manufacturing cost can be reduced.

  Next, as shown in FIG. 10, etching is performed by using the resist pattern 28 used for forming the p-type well 29 and the channel formation region 30 in the memory cell formation regions M1 to M3. That is, the insulating film 24 formed in the memory cell formation regions M1 to M3 is removed by wet etching using the resist pattern 28 as a mask. At this time, the resist pattern 28 is formed on the well isolation region B between the memory cell formation region M2 and the memory cell formation region M3. Therefore, the insulating film 24 remains in the well isolation region B. In the resist pattern 28 formed on the well isolation region B, side etching in the lateral direction proceeds, so that the resist pattern 28 formed on the well isolation region B is likely to collapse. In particular, in the first embodiment, since the p-type well 29 and the channel formation region 30 are formed by the same resist pattern 28, the thickness of the resist pattern is larger than that of the resist pattern for forming only the channel formation region. It is thick. For example, the film thickness of the resist pattern for forming only the channel formation region is about 1 μm, whereas the film thickness of the resist pattern 28 used in the first embodiment is 2 μm or more and 3 μm or less. For this reason, the aspect ratio (height / width) of the resist pattern 28 formed in the well isolation region B is increased, and the resist pattern 28 is easily tilted. When the resist pattern 28 falls down, the yield of the manufacturing process is reduced.

  Therefore, in the first embodiment, the width between the element isolation regions 21 formed in the well isolation region B, that is, the width of the well isolation region B is increased. Alternatively, the width of the element isolation region 21 itself is increased. As a result, the width of the resist pattern 28 formed in the well isolation region B is widened, and the width of the resist pattern 28 relative to the film thickness (height) of the resist pattern 28 is relatively widened, thereby improving the aspect ratio. be able to. In this way, even if side etching occurs, the resist pattern 28 formed in the well isolation region B becomes difficult to fall down, and the generation of foreign matter can be suppressed. Therefore, even if the thick resist pattern 28 is used as in the first embodiment, it is possible to prevent a decrease in yield in the manufacturing process of the semiconductor device.

Subsequently, after removing the resist pattern 28, a gate insulating film (first potential barrier film) 31 is formed on the main surface of the semiconductor substrate 20. The gate insulating film 31 is made of, for example, a silicon oxide film, and can be formed using a thermal oxidation method. Then, a charge storage film 32 is formed on the gate insulating film 31. The charge storage film 32 is made of, for example, a silicon nitride film, and can be formed using a CVD (Chemical Vapor Deposition) method in which silane gas (SiH ₄ ) and ammonia gas (NH ₃ ) are chemically reacted. Although the silicon nitride film is used as the charge storage film 32, the present invention is not limited to this. For example, a film including a trap level in a film such as a silicon oxynitride film (SiON) may be used.

Next, an insulating film (second potential barrier film) 33 is formed on the charge storage film 32. The insulating film 28 is made of, for example, a silicon oxide film, and can be formed by a CVD method in which a silane gas and an oxygen gas (O ₂ ) are chemically reacted.

Subsequently, a polysilicon film is formed on the insulating film 28. The polysilicon film can be formed by, for example, a CVD method in which silane gas is thermally decomposed in nitrogen gas (N ₂ ). When forming the polysilicon film, a conductive impurity such as phosphorus is added. Note that after the formation of the polysilicon film is completed, the conductive impurity may be implanted into the polysilicon film by using an ion implantation method.

  Thereafter, a cap insulating film 35 is formed on the polysilicon film. The cap insulating film 35 is made of, for example, a silicon oxide film. The silicon oxide film can be formed by using, for example, a CVD method. The cap insulating film 35 has a function of protecting the gate electrode 34 formed in the subsequent process.

  Next, after applying a resist film on the cap insulating film, the resist film is patterned by exposure and development. The patterning is performed so that the resist film remains in the region where the gate electrode 34 is to be formed. Then, a gate electrode 34 as shown in FIG. 11 is formed by etching using the patterned resist film as a mask. In this way, the gate electrode 34 can be formed in the memory cell formation regions M1 to M3.

  Subsequently, as shown in FIG. 12, after a resist film is applied on the main surface of the semiconductor substrate 20, a resist pattern 36 is formed by subjecting the resist film to exposure / development processing. The resist pattern 36 is patterned so as to cover the memory cell formation regions M1 to M3 and the high breakdown voltage MISFET formation region K and to expose the low breakdown voltage MISFET formation region T. Then, a p-type well 37 is formed in the low breakdown voltage MISFET formation region T by ion implantation using the resist pattern 36 as a mask. A p-type impurity such as boron is introduced into the p-type well 37, and the impurity concentration is adjusted to the characteristics of the low breakdown voltage MISFET.

  Next, the channel formation region 38 is formed using the resist pattern 36 used when forming the p-type well 37 as it is. The channel formation region 38 is formed by ion implantation using the resist pattern 36 as a mask, and p-type impurities are introduced.

  Subsequently, after removing the resist pattern 36, a gate insulating film is formed on the main surface of the semiconductor substrate 20. The gate insulating film is formed of, for example, a silicon oxide film, and can be formed using a thermal oxidation method. Thereafter, the gate insulating film formed in the low breakdown voltage MISFET formation region T is removed. The gate insulating film can be removed using, for example, a photolithography technique and an etching technique.

  Then, the gate insulating film 40 is formed on the gate insulating film and the semiconductor substrate 20. The gate insulating film 40 is made of, for example, a silicon oxide film, and can be formed by, for example, a CVD method. Thus, as shown in FIG. 13, a relatively thick gate insulating film 39 is formed in the high breakdown voltage MISFET formation region K, and a relatively thin gate insulation film is formed in the low breakdown voltage MISFET formation region T. A film 40 can be formed. Although an example in which a silicon oxide film is used as the gate insulating films 39 and 40 is shown, the present invention is not limited thereto, and for example, a material having a higher dielectric constant than silicon oxide, a so-called High-k film may be used. For example, it may be formed from a film of aluminum oxide, hafnium oxide, zirconium oxide, silicon nitride, or the like.

  Subsequently, for example, a polysilicon film is formed as a conductive film on the entire main surface of the semiconductor substrate 20. The polysilicon film can be formed by using, for example, a CVD method as described above. Note that a conductive impurity is added during or after the formation of the polysilicon film. This conductive impurity is introduced to reduce the resistance of the polysilicon film.

  Next, as shown in FIG. 14, a cap insulating film 42 is formed on the polysilicon film. The cap insulating film 42 has a function of protecting the gate electrodes 41 and 43 formed in a later process, and is formed of, for example, a silicon oxide film. For example, a CVD method is used as a method for forming the silicon oxide film.

  Subsequently, after applying a resist film on the cap insulating film 42, the resist film is patterned by exposure and development. The patterning is performed so that the resist film remains in the region where the gate electrodes 41 and 43 are formed. Then, etching is performed using the patterned resist film as a mask to form the gate electrode 41 in the high breakdown voltage MISFET formation region K and the gate electrode 43 in the low breakdown voltage MISFET formation region T. At this time, processing is performed so that the gate length of the gate electrode 43 is shorter than the gate length of the gate electrode 41.

  Here, when the gate electrodes 41 and 43 are formed by etching, etching residues made of a polysilicon film remain on the side walls of the gate electrode 34 formed in the memory cell formation regions M1 to M3. Therefore, in order to remove this etching residue, a resist pattern that covers the high breakdown voltage MISFET formation region K and the low breakdown voltage MISFET formation region T and exposes the memory cell formation regions M1 to M3 is formed. Then, etching residues formed on the side walls of the gate electrode 34 are removed by etching using the resist pattern as a mask.

  Next, the low-concentration n-type impurity diffusion region 45 is formed in the memory cell formation regions M1 to M3 by using a photolithography technique and an ion implantation method. The low-concentration n-type impurity diffusion region 45 can be formed by introducing an n-type impurity such as phosphorus or arsenic into the semiconductor substrate 20 and then performing a heat treatment for activating the introduced n-type impurity. Similarly, a low concentration n-type impurity diffusion region 46 is formed in the high breakdown voltage MISFET formation region K, and a low concentration n type impurity diffusion region 47 is formed in the low breakdown voltage MISFET formation region T.

  Subsequently, as shown in FIG. 15, after a laminated film made of a silicon oxide film, a silicon nitride film, and a silicon oxide film is formed on the semiconductor substrate 20, a resist pattern that exposes only the low breakdown voltage MISFET formation region T is formed. . Then, the laminated film formed in the low breakdown voltage MISFET formation region T is anisotropically etched using the resist pattern as a mask. Thereafter, after removing the resist pattern, the side walls 48 and 49 are formed by anisotropically etching the laminated film made of the silicon oxide film, the silicon nitride film, and the silicon oxide film. By these steps, a relatively wide sidewall 48 is formed on the sidewall of the gate electrode 34 formed in the memory cell formation regions M1 to M3 and the sidewall of the gate electrode 41 formed in the high breakdown voltage MISFET formation region K. Can be formed. On the other hand, a relatively narrow sidewall 49 can be formed on the sidewall of the gate electrode 43 formed in the low breakdown voltage MISFET formation region T.

  Next, a high-concentration n-type impurity diffusion region 50 is formed in the memory cell formation regions M1 to M3 using a photolithography technique and an ion implantation method. The high-concentration n-type impurity diffusion region 50 can be formed by introducing an n-type impurity such as phosphorus or arsenic into the semiconductor substrate 20 and then performing a heat treatment for activating the introduced n-type impurity. Similarly, a high concentration n-type impurity diffusion region 51 is formed in the high breakdown voltage MISFET formation region K, and a high concentration n type impurity diffusion region 52 is formed in the low breakdown voltage MISFET formation region T. In these high-concentration n-type impurity diffusion regions 50 to 52, n-type impurities are introduced at a higher concentration than the low-concentration n-type impurity diffusion regions 45 to 47, respectively. Further, the p-type semiconductor region 53 is formed in the well power supply region A.

As described above, the MONOS transistors Q _{1 to} Q ₃ can be formed in the memory cell formation regions M _{1 to} M ₃ . Similarly, the high breakdown voltage MISFET Q ₄ can be formed in the high breakdown voltage MISFET formation region K, and the low breakdown voltage MISFET Q ₅ can be formed in the low breakdown voltage MISFET formation region T.

  Next, the wiring process will be described. As shown in FIG. 3, a silicon nitride film 54 is formed on the main surface of the semiconductor substrate 20. The silicon nitride film 54 can be formed by, for example, a CVD method. Then, a silicon oxide film 55 is formed on the silicon nitride film 54. This silicon oxide film 55 can also be formed using, for example, a CVD method. Thereafter, the surface of the silicon oxide film 55 is planarized using, for example, a CMP (Chemical Mechanical Polishing) method.

  Next, contact holes 56 are formed in the silicon oxide film 55 by using a photolithography technique and an etching technique. Subsequently, a titanium / titanium nitride film is formed on the silicon oxide film 55 including the bottom surface and inner wall of the contact hole 56. The titanium / titanium nitride film is composed of a laminated film of a titanium film and a titanium nitride film, and can be formed by using, for example, a sputtering method. This titanium / titanium nitride film has a so-called barrier property that prevents, for example, tungsten, which is a material of a film to be embedded in a later process, from diffusing into silicon.

  Subsequently, a tungsten film is formed on the entire main surface of the semiconductor substrate 20 so as to fill the contact hole 56. This tungsten film can be formed using, for example, a CVD method. Then, the plug 57 can be formed by removing the unnecessary titanium / titanium nitride film and tungsten film formed on the silicon oxide film 55 by, for example, the CMP method.

  Next, a titanium / titanium nitride film, an aluminum film, and a titanium / titanium nitride film are sequentially formed on the silicon oxide film 55 and the plug 57. These films can be formed by using, for example, a sputtering method. Subsequently, these films are patterned by using a photolithography technique and an etching technique to form wirings 58. Furthermore, although wiring is formed in the upper layer of the wiring 58, description here is abbreviate | omitted.

  In this manner, the semiconductor device according to the first embodiment can be formed.

(Embodiment 2)
In the first embodiment, the example in which the p-type well 26 in the high breakdown voltage MISFET formation region is formed first and then the p-type well 29 in the memory cell formation regions M1 to M3 is formed has been described. In the second embodiment, an example will be described in which the p-type well 29 in the memory cell formation regions M1 to M3 is formed first, and then the p-type well 26 in the high breakdown voltage MISFET formation region is formed.

  A method for manufacturing a semiconductor device according to the second embodiment will be described with reference to the drawings.

  5 to 7 are the same as those in the first embodiment. Subsequently, as shown in FIG. 16, an insulating film 24 is formed on the semiconductor substrate 20, and a resist film is applied on the insulating film 24. Then, a resist pattern 28 is formed by subjecting this resist film to exposure / development processing. The resist pattern 28 is patterned so as to cover the high breakdown voltage MISFET formation region K and the low breakdown voltage MISFET formation region T and expose the memory cell formation regions M1 to M3. The well isolation region B is also covered.

  Subsequently, a p-type well 29 is formed in the memory cell formation regions M1 to M3 by ion implantation using the resist pattern 28 as a mask. A p-type impurity such as boron is introduced into the p-type well 29. Then, the channel formation region 30 is formed using the resist pattern 28 used for forming the p-type well 29 as it is. For example, an n-type impurity such as phosphorus or arsenic is introduced into the channel formation region 30.

  Next, after removing the resist pattern 28, a new resist film is applied on the insulating film 24. Then, the resist pattern 25 is formed by performing exposure / development processing on the resist film. The resist pattern 25 is patterned so as to cover the memory cell formation regions M1 to M3 and the low breakdown voltage MISFET formation region T and to expose the high breakdown voltage MISFET formation region K.

  Subsequently, a p-type well 26 is formed in the high breakdown voltage MISFET formation region K by ion implantation using the resist pattern 25 as a mask. A p-type impurity such as boron is introduced into the p-type well 26. Then, a channel formation region 27 is formed using the resist pattern 25 used for forming the p-type well 26 as it is. A p-type impurity such as boron is introduced into the channel formation region 27.

  Thereafter, as shown in FIG. 18, the insulating film 24 formed in the high breakdown voltage MISFET formation region K is removed by etching using the resist pattern 25 as a mask. Then, the resist pattern 25 is removed. Thereafter, the gate electrodes of the high breakdown voltage MISFET and the low breakdown voltage MISFET are formed first, and the gate electrode of the MONOS transistor is formed. Since the following steps are the same as those in the first embodiment, a description thereof will be omitted. In this way, the semiconductor device according to the second embodiment can be manufactured.

  According to the second embodiment, as in the first embodiment, by separately forming the p-type wells 26 and 29, the performance of the MONOS transistor and the high breakdown voltage MISFET can be improved, and the p-type well is also formed. By forming the wells 26 and 29 and the channel formation regions 27 and 30 with the same mask, the mask can be reduced and the manufacturing cost can be reduced.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be widely used in the manufacturing industry for manufacturing semiconductor devices.

In Embodiment 1 of this invention, it is the top view which showed the layout structure of each element formed in the chip | tip. FIG. 2 is a block diagram illustrating an example of an internal configuration of the EEPROM illustrated in FIG. 1. FIG. 3 is a cross-sectional view showing a cross section of the semiconductor device in the first embodiment. FIG. 2 is an explanatory diagram showing an example of a memory array structure and operating conditions (1 cell / 1 transistor) of the EEPROM shown in FIG. 1. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device in the first embodiment. FIG. FIG. 6 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 5; FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 6; FIG. 8 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 7; FIG. 9 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 8; FIG. 10 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 9; FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 10; FIG. 12 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 11; FIG. 13 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 12; FIG. 14 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 13; FIG. 15 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 14; It is sectional drawing which shows the manufacturing process of the semiconductor device in Embodiment 2 of this invention. FIG. 17 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 16; FIG. 18 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 17;

Explanation of symbols

1 Semiconductor chip 2 CPU
3 ROM
4 RAM
5 EEPROM
6 Analog Circuits 7a to 7g Electrostatic Protection Circuit 10 Memory Array 11 Direct Peripheral Circuit Unit 12 Indirect Peripheral Circuit Unit 20 Semiconductor Substrate 21 Element Isolation Region 22 N-type Semiconductor Region 23 Well Isolation Region 24 Insulating Film 25 Resist Pattern 26 P-type Well 27 Channel formation region 28 resist pattern 29 p-type well 30 channel formation region 31 gate insulating film 32 charge storage film 33 insulating film 34 gate electrode 35 cap insulating film 36 resist pattern 37 p-type well 38 channel formation region 39 gate insulating film 40 gate insulation Film 41 Gate electrode 42 Cap insulating film 43 Gate electrode 45 Low-concentration n-type impurity diffusion region 46 Low-concentration n-type impurity diffusion region 47 Low-concentration n-type impurity diffusion region 48 Side wall 49 Side wall 50 High-concentration n-type impurity diffusion Area 51 High-concentration n-type impurity diffusion region 52 High-concentration n-type impurity diffusion region 53 P-type semiconductor region 54 Silicon nitride film 55 Silicon oxide film 56 Contact hole 57 Plug 58 Wiring A well power supply region B Well isolation region K High breakdown voltage MISFET formation region M1~M3 memory cell formation region T low breakdown voltage MISFET formation region Q ₁ to Q ₃ MONOS-type transistor Q ₄ high voltage MISFET
Q ₅ low breakdown voltage MISFET
CT1-8 cell transistor DL1-4 data line SL1-4 source line WE1-2 well

Claims (20)

A memory cell formed in the first region of the semiconductor substrate, a high breakdown voltage MISFET formed in the second region of the semiconductor substrate and a relatively high breakdown voltage formed in the third region of the semiconductor substrate. A method of manufacturing a semiconductor device having a low low withstand voltage MISFET,
(A) forming a first well of the first conductivity type of the memory cell;
(B) forming a second well which is the first conductivity type of the high breakdown voltage MISFET,
The method of manufacturing a semiconductor device, wherein the step (a) and the step (b) are performed in separate steps.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity concentration of the first well is different from the impurity concentration of the second well.   3. The method of manufacturing a semiconductor device according to claim 2, wherein the impurity concentration of the first well is larger than the impurity concentration of the second well.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the step (a) is performed after the step (b).   2. The method of manufacturing a semiconductor device according to claim 1, wherein the step (b) is performed after the step (a) is performed.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the second region in which the high breakdown voltage MISFET is formed is a drive circuit formation region. (A) forming a resist pattern on the semiconductor substrate;
(B) forming a well in the semiconductor substrate by ion implantation using the resist pattern as a mask;
(C) forming a channel formation region by ion implantation using the resist pattern used as a mask when forming the well, as a method for manufacturing a semiconductor device.   8. The method of manufacturing a semiconductor device according to claim 7, wherein the film thickness of the resist pattern shared in the steps (b) and (c) is thicker than that used only for forming the channel formation region. .   The method of manufacturing a semiconductor device according to claim 8, wherein the resist pattern has a thickness of 2 μm to 3 μm. A memory cell formed in the first region of the semiconductor substrate, a high breakdown voltage MISFET formed in the second region of the semiconductor substrate and a relatively high breakdown voltage formed in the third region of the semiconductor substrate. A method of manufacturing a semiconductor device having a low low withstand voltage MISFET,
(A) forming an insulating film on the semiconductor substrate;
(B) forming a first resist pattern covering the memory cell formation region and the low breakdown voltage MISFET formation region on the insulating film and exposing the high breakdown voltage MISFET formation region;
(C) forming a second well which is the first conductivity type of the high voltage MISFET in the semiconductor substrate by ion implantation using the first resist pattern as a mask;
(D) forming a channel formation region of the high voltage MISFET in the semiconductor substrate by ion implantation using the first resist pattern used for forming the second well as a mask;
(E) removing the first resist pattern;
(F) exposing the memory cell formation region on the semiconductor substrate and forming a second resist pattern covering the low breakdown voltage MISFET formation region and the high breakdown voltage MISFET formation region;
(G) forming a first well which is the first conductivity type of the memory cell in the semiconductor substrate by ion implantation using the second resist pattern as a mask;
(H) forming a channel formation region of the memory cell in the semiconductor substrate by ion implantation using the second resist pattern used for forming the first well as a mask;
(I) a step of removing the second resist pattern, and a method for manufacturing a semiconductor device.   11. The method of manufacturing a semiconductor device according to claim 10, wherein the impurity concentration of the first well is higher than the impurity concentration of the second well. further,
The step of removing the insulating film existing in the memory cell formation region by etching using the second resist pattern as a mask after the step (h) and before the step (i). Item 11. A method for manufacturing a semiconductor device according to Item 10. further,
(J) After the step (i), a step of stacking and forming a first potential barrier film, a charge storage film, and a second potential barrier film on the semiconductor substrate;
(K) forming a conductor film on the second potential barrier film;
13. The method of manufacturing a semiconductor device according to claim 12, further comprising the step of patterning the conductor film to form a gate electrode of the memory cell in the memory cell formation region. further,
14. The method of manufacturing a semiconductor device according to claim 13, further comprising the step of forming a third well which is the first conductivity type of the low breakdown voltage MISFET after the step (l).   The method of manufacturing a semiconductor device according to claim 10, wherein the memory cell is a nonvolatile memory cell. A memory cell formed in the first region of the semiconductor substrate, a high breakdown voltage MISFET formed in the second region of the semiconductor substrate and a relatively high breakdown voltage formed in the third region of the semiconductor substrate. A method of manufacturing a semiconductor device having a low low withstand voltage MISFET,
(A) forming a second resist pattern on the semiconductor substrate, covering the low breakdown voltage MISFET formation region and the high breakdown voltage MISFET formation region and exposing the memory cell formation region;
(B) forming a first well of the first conductivity type of the memory cell in the semiconductor substrate by ion implantation using the second resist pattern as a mask;
(C) forming a channel formation region of the memory cell by ion implantation using the second resist pattern used for forming the first well as a mask;
(D) removing the second resist pattern;
(E) forming a first resist pattern on the semiconductor substrate, covering the memory cell formation region and the low breakdown voltage MISFET formation region and exposing the high breakdown voltage MISFET formation region;
(F) forming a second well which is the first conductivity type of the high voltage MISFET in the semiconductor substrate by ion implantation using the first resist pattern as a mask;
(G) forming a channel formation region of the high breakdown voltage MISFET by ion implantation using the first resist pattern used for forming the second well as a mask;
(H) removing the first resist pattern. A method for manufacturing a semiconductor device, comprising: A semiconductor device having a memory cell formed in a first region of a semiconductor substrate, a high breakdown voltage MISFET formed in a second region of the semiconductor substrate, and a low breakdown voltage MISFET formed in a third region of the semiconductor substrate,
(A) a first well that is a first conductivity type of the memory cell;
(B) a second well which is the first conductivity type of the high breakdown voltage MISFET,
A semiconductor device, wherein the impurity concentration of the first well and the impurity concentration of the second well are different.   18. The semiconductor device according to claim 17, wherein the impurity concentration of the first well is higher than the impurity concentration of the second well.   The semiconductor device according to claim 17, wherein the memory cell is a nonvolatile memory cell. The memory cell is
(C) a first potential barrier film formed on the semiconductor substrate;
(D) a charge storage film formed on the first potential barrier film;
(E) a second potential barrier film formed on the charge storage film;
20. The semiconductor device according to claim 19, further comprising: a gate electrode formed on the second potential barrier film.

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