JP2009071325A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique to make it possible to increase the capacitance per unit area of a capacitor and to simplify the process of manufacturing thereof. <P>SOLUTION: A method for manufacturing a semiconductor device can increase a surface area of a capacitor to increase the capacitance per unit area of a capacitor by forming at least one or more uneven capacitor formation groove 4a on the surface of a capacitor formation area. It is possible to simplify the process of manufacturing by forming the capacitor formation groove 4a and an element isolation groove 4 formed on the surface of a semiconductor substrate 1 in the same process. A dielectric film 16a of the capacitor in the capacitor formation area and a high breakdown voltage gate insulation film 16 in an MISFET formation area are formed in the same process. Or, a memory-gate interlayer film 11 between a polysilicon layer 10a in a memory cell formation area and a polysilicon layer 17, is formed in the same process with the dielectric film 16a of the capacitor in the capacitor formation area. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing technique and a semiconductor device, and more particularly to a capacitor forming method.

  In recent years, as the miniaturization, lower power consumption, and integration of semiconductor devices have progressed, the operating voltage of semiconductor devices has been lowered and the voltage supplied from an external power source has been lowered. A booster circuit such as a charge pump circuit for generating the operating voltage is mounted on the semiconductor device. This type of booster circuit has a capacitor (capacitor element), and the capacitor is formed of a MIS capacitor element using, for example, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) as a capacitor.

  Japanese Patent Laying-Open No. 2001-85633 (Patent Document 1 (hereinafter referred to as a first example)) describes a first capacitor between a first gate and a second gate as a capacitor of a charge pump circuit in a semiconductor device having a nonvolatile memory. And a technique for reducing the area of the charge pump circuit by forming a capacitor structure in which the first gate and the second capacitor between the well regions are connected in parallel.

Japanese Laid-Open Patent Publication No. 11-251547 (Patent Document 2 (hereinafter referred to as a second example)) discloses a first trench capacitor constituting a DRAM (Dynamic Random Access Memory) memory cell and other regions. A second trench capacitor having substantially the same structure as that of the trench capacitor is formed, and a technique is disclosed in which the second trench capacitor is used as a capacitor in a region other than the DRAM.
JP 2001-85633 A JP 11-251547 A

  In the first example described above, since the boosted voltage value is proportional to the area of the capacitor, the area of the first gate and the second gate becomes smaller when the area is reduced with the miniaturization, and the capacitance obtained Less. Therefore, in order to form a high voltage and stable booster circuit, the area of the capacitor required in the charge pump circuit must be increased.

  In the second example described above, there is a problem in that the number of manufacturing steps is increased in order to form a capacitor having substantially the same structure as a DRAM memory cell.

  An object of the present invention is to provide a technique capable of improving the capacitance of a capacitor per unit area.

  Another object of the present invention is to provide a technique for simplifying the manufacturing process of a semiconductor device having a capacitor.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, according to the present invention, in a semiconductor device having a semiconductor element such as a MISFET and a capacitor (capacitance element) on a semiconductor substrate, the capacitor (capacitance element) includes a plurality of capacitor formation grooves formed in the capacitor formation region. And a capacitor dielectric film and a capacitor electrode formed on the capacitor formation region including the plurality of capacitor formation grooves. Thereby, the surface area of the capacitor can be increased, and the capacitor capacity per unit area can be improved.

  In the method of manufacturing a semiconductor device having a semiconductor element such as a MISFET and a capacitor (capacitance element) on the semiconductor substrate, at least a step of forming an element isolation groove for separating the semiconductor elements in the semiconductor substrate, One or more capacitor formation grooves are formed. As a result, the surface area of the capacitor can be increased to improve the capacitor capacity per unit area, and the manufacturing process can be simplified. The capacitor forming groove is formed in a hole shape or a stripe shape. Even with this formation, it is possible to increase the capacitor surface area by increasing the surface area of the capacitor.

  In the present invention, the capacitor dielectric film formed in the capacitor formation groove is formed in the step of forming the gate oxide film of the MISFET. Thereby, the manufacturing process can be simplified. Here, the MISFET includes a high breakdown voltage MISFET and a low breakdown voltage MISFET, and it is also possible to use a gate insulation film of the high breakdown voltage MISFET or a low breakdown voltage MISFET.

  The present invention also provides a first memory gate insulating film, a first conductive film formed on the first memory gate insulating film, and a second memory gate insulating film formed on the first conductive film. And the capacitor dielectric film is formed on the second memory gate insulating film and the capacitor formation groove in the same process. Thereby, the manufacturing process can be simplified. Further, by using the second memory gate insulating film of the memory cell instead of the gate insulating film of the MISFET as the capacitor dielectric film, the reliability of the capacitor dielectric film can be improved and the manufacturing process can be simplified. .

  Among the inventions disclosed by the present application, effects obtained by typical ones will be briefly described as follows.

  Since the capacitor (capacitance element) is formed by a plurality of capacitor formation grooves formed in the capacitor formation region, and a capacitor dielectric film and a capacitor electrode formed on the capacitor formation region including the inside of the plurality of capacitor formation grooves. The capacitor capacity per unit area can be improved by increasing the surface area of the capacitor.

  Since the element isolation groove and the capacitor formation groove formed in the capacitor are formed in the same process on the semiconductor substrate, the manufacturing process of the semiconductor device can be simplified.

  Further, the manufacturing process of the semiconductor device can be simplified by forming the gate insulating film of the MISFET and the dielectric film of the capacitor on the capacitor forming groove in the same process.

  In addition, since the capacitor dielectric film in the capacitor formation region and the memory gate interlayer film of the memory cell are formed in the same process, the manufacturing process of the semiconductor device can be simplified.

  Further, since the dielectric film of the capacitor is formed using the memory gate interlayer film (NONO film) of the memory cell instead of using the gate insulating film of the MISFET, a highly reliable dielectric film of the capacitor can be formed. .

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 is a plan view of a main part of a semiconductor device having a nonvolatile memory according to an embodiment of the present invention. FIG. 1 shows a plan view of a memory cell of a nonvolatile memory on the left side, a MISFET on the center, and a capacitor (capacitance element) on the right side. 2 shows a cross-sectional view of a memory cell on the left side, a high-voltage MISFET on the center, and a capacitor on the right side, corresponding to FIG. 1, respectively, along the lines AA ′, BB ′ and C— in FIG. This corresponds to a cross-sectional view in the C ′ line direction. The capacitor shown in FIG. 2 uses a gate insulating film of a high voltage MISFET as its dielectric film.

  FIG. 3 is a cross-sectional view of the low breakdown voltage MISFET on the left side and a cross-sectional view of the capacitor on the right side, and is a cross-sectional view in the B-B ′ and C-C ′ directions in FIG. 1. The capacitor shown in FIG. 3 uses a gate insulating film of a low breakdown voltage MISFET as its dielectric film.

  Thus, the right side of FIG. 2 shows a capacitor formation region using a high breakdown voltage gate insulating film of MISFET as a capacitor dielectric film, and the right side of FIG. 3 shows a capacitor formation using a low breakdown voltage gate insulating film as a capacitor dielectric film. Indicates the area. Here, FIG. 3 shows only MISFETs and capacitors having different structures from those in FIG.

  First, the basic structure in the first embodiment will be described with reference to FIGS.

  A memory cell, a MISFET, and a capacitor of a nonvolatile memory are formed on the semiconductor substrate 1. In order to simplify the following description, the MISFET is an N-channel MISFET and the P-channel MISFET is not shown.

  The memory cell mainly includes a memory tunnel insulating film (first memory gate insulating film) 9 formed on a P-type impurity layer (P-type well region) 7 formed on the semiconductor substrate 1 and a floating charge storage layer. Gate electrode 10, control gate electrode (memory gate electrode) 17a formed on floating gate electrode 10, silicon oxide film 18 formed on control gate electrode, and between floating gate electrode 10 and control gate electrode 17a Formed on the memory gate interlayer film (second memory gate insulating film) 11, the side wall 26 formed on the side wall of the memory gate electrode structure 20, and the P-type impurity layer (P-type well region) 7. It consists of an N-type impurity layer 23a serving as a drain region and an N-type impurity layer 23b serving as a source region. The memory gate electrode structure 20 is formed of a memory tunnel insulating film 9, a floating gate electrode 10, a memory gate interlayer film 11, a control gate electrode 17a, and a silicon oxide film 18.

  The memory tunnel insulating film (first memory gate insulating film) 9 is formed of, for example, a thermal oxide film, and the memory gate interlayer film (second memory gate insulating film) 11 is formed of, for example, a silicon nitride film on the oxide film. It is formed of a so-called NONO film in which an oxide film is formed on a silicon nitride film and a silicon nitride film is formed on the oxide film.

  The floating gate electrode 10 serving as a charge storage layer is formed of, for example, a polycrystalline silicon film, and the control gate electrode (memory gate electrode) 17a is formed of, for example, a polycrystalline silicon film and a silicide film such as a cobalt silicide (CoSi) film. It is formed of a laminated film.

  The control gate electrode (memory gate electrode) 17a is electrically connected to the word line.

  The wiring layer 33 forms a bit line and is electrically connected to the N-type impurity layer 23a serving as a drain region. Plug layer 33a forms a source line and is electrically connected to N-type impurity layer 23b serving as a source region. The wiring layer 33 and the plug layer 33a are formed of a metal film such as tungsten (W) or copper (Cu).

  In the memory cell, for example, data is written by applying a ground voltage (0V) to the source region, a voltage of about 5V to the N-type impurity layer 23a, and a voltage of about 10V to the control gate electrode 17a. Electron) is injected and stored in the floating gate electrode 10 which is a charge storage layer.

  At the time of erasing data, for example, the P-type impurity layer (P-type well region) 7 is 10 V, the source / drain region is open, and a high voltage of about −10 V opposite to that at the time of writing is applied to the control gate electrode 17a. The electrons stored in the floating gate electrode 10 serving as the storage layer are extracted into the P-type impurity layer (P-type well region) 7 by electron tunneling through the memory tunnel insulating film (first memory gate insulating film) 9.

  For example, data is read by applying a voltage of about 0 V to the source region, a voltage of about 1 V to the drain region, and a voltage of about 2 to 4 V to the control gate electrode 17a.

  As described above, in the write / erase operation of the nonvolatile memory cell, a high voltage having a high absolute value with respect to the ground voltage (0 V) is required. On the other hand, with the miniaturization and low power consumption, the external power supply voltage Vss supplied from the external power supply is ground voltage (0V), and the external power supply voltage Vcc is about 1.8 to 3.3V. . Therefore, a booster circuit such as a charge pump circuit is provided on the semiconductor substrate, and these high voltages are generated from an external power source. The high voltage indicates a voltage having an absolute value higher than that of the external power supply voltage. In the nonvolatile memory according to the present embodiment, a high voltage of about 10 V or more is required.

  Therefore, the MISFET constituting the peripheral circuit is composed of a high breakdown voltage MISFET having a high breakdown voltage gate insulating film 16 in a gate insulating film and a low breakdown voltage MISFET having a low breakdown voltage gate insulating film 15, and has a gate electrode or a source. A MISFET in which a high voltage is applied to the drain is composed of a high voltage MISFET.

  The capacitor (capacitance element) includes a MIS capacitance element formed using a high breakdown voltage MISFET formation step and a MIS capacitance element formed using a low breakdown voltage MISFET formation step.

  A booster circuit such as a charge pump circuit is constituted by these MISFETs and capacitors. It should be noted that the high breakdown voltage gate insulating film 16 is formed thicker than the low breakdown voltage gate insulating film 15.

  The semiconductor elements such as the low breakdown voltage MISFET, the high breakdown voltage MISFET, and the capacitor are separated by the element isolation trench 4 and an element isolation insulating film embedded in the element isolation trench. That is, element isolation is performed in the element isolation trench 4 in the semiconductor element formation region such as the high breakdown voltage MISFET formation region, the low breakdown voltage MISFET formation region, and the capacitor formation region.

  The N channel type high breakdown voltage MISFET mainly includes a high breakdown voltage gate insulating film 16 as a gate insulating film of the MISFET and a high breakdown voltage on a P type impurity layer (P type well region) 7 formed on the semiconductor substrate 1. MISFET gate electrode 17b formed on the gate insulating film 16 of the MISFET, side wall 26 formed on the side wall of the gate electrode structure 21 composed of the gate electrode 17b and the silicon oxide film 18, and a P-type impurity layer (P N-type impurity layers 24a and 27a to be source / drain regions formed in the type well region 7). N-type impurity layers 24a and 27a are electrically connected to wiring layer 34a.

  The high breakdown voltage gate electrode 17b is formed of a conductive film in the same layer as the control gate electrode (memory gate electrode) 17a of the memory cell.

  A capacitor (MIS capacitor element) C formed by using the high breakdown voltage MISFET forming step is formed on the capacitor forming groove 4 a formed mainly in the N-type impurity layer (N-type well region) 8 formed in the semiconductor substrate 1. The capacitor dielectric film 16a formed in the step of forming the gate insulating film of the high breakdown voltage MISFET and the capacitor electrode 17c formed in the step of forming the gate electrode 17b of the high breakdown voltage MISFET. The upper electrode structure 22 of the capacitor is formed from the capacitor electrode 17c and the silicon oxide film 18.

  That is, the capacitor formation groove 4a is formed using the same process as the process of forming the element isolation groove 4 for separating semiconductor elements such as MISFETs, and the capacitor dielectric film 16a is formed on the side and bottom surfaces of the capacitor formation groove 4a. The capacitor electrode 17c is formed so as to fill the capacitor formation groove 4a via the dielectric film 16a of the capacitor.

  The step of forming the N-type impurity layer (N-type well region) 8 in the capacitor (MIS capacitor element) formation region forms the N-type impurity layer (N-type well region) 8 in the p-channel MISFET formation region (not shown). It is formed in the same process as the process.

  The capacitor electrode 17c formed in the same process as the process of forming the gate electrode 17b of the N channel type high voltage MISFET is an upper electrode of the capacitor, and the N type impurity layer (N type well region) 8 is the lower electrode of the capacitor. It becomes. The N-type impurity layer (N-type well region) 8 is electrically connected to the wiring layer 35a via the N-type impurity layer 28a formed using the source / drain region forming step of the p-channel MISFET, and is connected to the capacitor electrode. 17c is electrically connected to the wiring layer 36a.

  The low breakdown voltage MISFET mainly includes a low breakdown voltage gate insulating film 15 as a gate insulating film of the MISFET and a low breakdown voltage gate insulation on a P-type impurity layer (P-type well region) 7 formed on the semiconductor substrate 1. The gate electrode 17b of the MISFET formed on the film 15, the side wall 26 formed on the side wall of the gate electrode structure 21 composed of the gate electrode 17b and the silicon oxide film 18, and the P-type impurity layer (P-type well region) 7 The n-type impurity layers 24b and 27b are formed as source / drain regions. N-type impurity layers 24b and 27b are electrically connected to wiring layer 34b.

  The low breakdown voltage gate electrode 17b is formed of a conductive film in the same layer as the control gate electrode (memory gate electrode) 17a of the memory cell.

  A capacitor (MIS capacitive element) formed by using the low breakdown voltage MISFET formation step is formed on the capacitor formation groove 4 a formed mainly in the N-type impurity layer (N-type well region) 8 formed in the semiconductor substrate 1. The capacitor dielectric film 15a formed in the step of forming the gate insulating film of the low breakdown voltage MISFET and the capacitor electrode 17c formed in the step of forming the gate electrode 17b of the low breakdown voltage MISFET. The capacitor upper electrode structure 22 is formed of the capacitor electrode 17c and the silicon oxide film 18.

  The capacitor formation groove 4a is formed using the same process as the element isolation groove 4 formation process for separating semiconductor elements such as MISFETs, and a capacitor dielectric film 15a is formed on the side and bottom surfaces of the capacitor formation groove 4a. The electrode 17c is formed so as to fill the capacitor formation groove 4a via the capacitor dielectric film 15a.

  The capacitor electrode 17c formed in the low breakdown voltage MISFET gate electrode 17b forming step constitutes the upper electrode of the capacitor, and the N-type impurity layer (N-type well region) 8 constitutes the lower electrode of the capacitor. The N-type impurity layer (N-type well region) 8 is electrically connected to the wiring layer 35b via the N-type impurity layer 28b formed using the source / drain region forming step of the p-channel MISFET, and is connected to the capacitor electrode. 17c is electrically connected to the wiring layer 36b.

  These capacitors constitute a capacitor element of a boost circuit such as a charge pump circuit. However, in order to improve the capacity of the boost circuit, the capacitance of the capacitor, that is, the area occupied by the MIS capacitor element must be increased. There is a problem that the area occupied by the booster circuit increases. That is, it is necessary to increase the capacitance value of the capacitor per unit area. In the present embodiment, the capacitor formation groove 4a is formed on the surface of the semiconductor substrate 1 using the element isolation groove formation step, and the capacitor (MIS The capacitor electrode 17c of the capacitor element C is embedded and formed, so that the area of the capacitor (MIS capacitor), that is, the capacitor formation groove, compared with the case where the capacitor (MIS capacitor element) is formed on the flat semiconductor substrate 1 surface. Since the side surface and the bottom surface of 4a become MIS capacitance, the capacitor capacitance per unit area can be improved, and the MIS capacitance can be increased.

  The capacitor (capacitance element) includes a plurality of capacitor formation grooves 4a formed in the capacitor formation region, a capacitor dielectric film 15a formed on the capacitor formation region including the inside of the plurality of capacitor formation grooves 4a, and a capacitor electrode. And 17c. Thereby, the surface area of the capacitor can be increased, and the capacitor capacity per unit area can be improved.

  The depth of the capacitor formation groove 4a is substantially equal to the depth of the element isolation groove 4, and the capacitor formation groove 4a is formed using a process of forming the element isolation groove 4. That is, at least one capacitor formation groove 4a is formed on the semiconductor substrate 1 including the capacitor formation region by using a step of forming an element isolation groove 4 for separating each semiconductor element, and silicon oxide which is an element isolation insulating film After the film 5 is buried, the silicon oxide film 5 which is an element isolation insulating film in the capacitor formation region is removed. That is, at least one capacitor forming groove 4 a is formed in the same forming process as the element isolation groove 4.

  The dielectric films 15a and 16a of the capacitor are formed of the same insulating film as the low breakdown voltage gate insulating film 15 and the high breakdown voltage gate insulating film 16 of the MISFET, respectively, and the capacitor electrode 17c is the gate electrode 17b of the MISFET. And a conductive film in the same layer as the control gate electrode 17a. That is, the dielectric films 15a and 16a of the capacitor are insulating films formed in the same formation process as the low breakdown voltage gate insulating film 15 and the high breakdown voltage gate insulating film 16 of the MISFET, respectively, and the capacitor electrode 17c is formed of the MISFET. The conductive film is formed in the same formation process as the gate electrode 17b and the control gate electrode 17a. As a result, the manufacturing process can be simplified and the capacitor capacity per unit area can be improved.

  Next, a method for manufacturing the semiconductor device according to the first embodiment will be described below.

  First, as shown in FIG. 4, a semiconductor substrate 1 made of, for example, P-type single crystal silicon is prepared. Next, the semiconductor substrate 1 is thermally oxidized, for example, to form a silicon oxide film 2 having a thickness of about 8 to 10 nm on the surface thereof.

  Next, a silicon nitride film 3 having a thickness of about 130 to 150 nm is deposited as a protective film on the silicon oxide film 2 by, for example, a CVD (Chemical Vapor Deposition) method, and then a resist pattern is masked as shown in FIG. As a result, the silicon nitride film 3, the silicon oxide film 2 and the semiconductor substrate 1 are sequentially dry-etched to form element isolation grooves 4 in the semiconductor substrate 1. At this time, at least one capacitor forming groove 4a is formed in the capacitor forming region, and the planar shape of the capacitor forming groove 4a at this time is a stripe shape as shown in FIG. 6, or a hole shape as shown in FIG. Alternatively, it is formed in a lattice shape as shown in FIG. That is, the plurality of capacitor formation grooves 4a are formed in a hole shape, a stripe shape, or a lattice shape.

  Thus, the manufacturing process can be simplified by forming the element isolation groove 4 and the capacitor formation groove 4a in the same process. Furthermore, the capacitor capacity per unit area can be improved by forming at least one capacitor forming groove 4a on the surface of the capacitor forming region. The formation pattern of the capacitor formation groove 4a is not limited to a hole shape, a stripe shape, or a lattice shape, and may be other shapes, and can be changed without departing from the gist of the present invention.

  Next, as shown in FIG. 9, a silicon oxide film 5 is deposited on the semiconductor substrate 1 by using, for example, a CVD method as an insulating film. Next, the silicon oxide film 5 is polished by a chemical mechanical polishing (CMP) method, and the silicon oxide film 5 is buried inside the element isolation trench 4 to form an element isolation region. Similarly, the silicon oxide film 5 is buried in the capacitor forming groove 4a.

  Next, after removing the silicon nitride film 3 using, for example, hot phosphoric acid, a P-type impurity, for example, boron (B) is implanted into the memory cell and the N-channel MISFET formation region by an ion implantation method. (P-type well region) 7 is formed. Further, an N-type impurity, for example, phosphorus (P) or arsenic (As) is implanted into the capacitor and a P channel type MISFET formation region (not shown) by ion implantation to form an N-type impurity layer (N-type well region) 8.

  Next, as shown in FIG. 10, for example, the semiconductor substrate 1 is thermally oxidized to form a silicon oxide film having a thickness of about 8 to 12 nm on the surface, thereby forming a memory tunnel insulating film (first memory gate insulating film) of the memory cell. 9 is formed. Subsequently, a polycrystalline silicon layer 10a to be a floating gate electrode (charge storage layer) 10 of the memory cell is deposited on the entire surface of the semiconductor substrate 1 by a CVD method.

  Next, as shown in FIG. 11, a laminated film 11a of a silicon oxide film and a silicon nitride film, which becomes a memory gate interlayer film (second memory gate insulating film) of the memory cell, is formed on the entire surface of the polycrystalline silicon layer 10a. To do. Further, a silicon nitride film 13 is formed on the laminated film 11a as a protective film, and a memory gate interlayer film 11 (hereinafter referred to as a NONO film 11) composed of the laminated film 11a and the silicon nitride film 13 is formed. The NONO film 11 is formed by using, for example, a CVD method, a silicon oxide film having a thickness of about 2 to 6 nm, a silicon nitride film having a thickness of about 5 to 9 nm, and a silicon oxide film having a thickness of about 3 to 7 nm. Then, a silicon nitride film having a thickness of about 5 to 15 nm is sequentially laminated as a protective film.

  Next, as shown in FIG. 12, after covering the entire surface of the memory cell formation region with the resist pattern 121, the NONO film 11 formed on the entire surface of the MISFET formation region and the entire surface of the capacitor formation region, the polycrystalline silicon layer 10a, The memory tunnel insulating film 9 is sequentially removed by dry etching, for example.

  Next, as shown in FIG. 13, the resist pattern 122 formed in the planar pattern shown in FIG. 14 is used as a mask on the entire memory cell formation region and the entire MISFET formation region, and the oxide buried in the capacitor formation groove 4a of the capacitor. The silicon film 5 is selectively removed by dry etching, for example.

  Next, a gate insulating film of the MISFET is formed. Here, the gate insulating film used for the MISFET and the capacitor dielectric film used for the capacitor are formed of the same dielectric film. That is, the gate insulating film used for the MISFET and the capacitor dielectric film used for the capacitor are formed in the same process. In the present embodiment, for an example in which a high breakdown voltage gate insulating film and a low breakdown voltage gate insulating film are separately formed in the same manufacturing process, (a) a step of forming a capacitor dielectric film, The step of forming the gate insulating film for breakdown voltage is the same step, and the step of forming the capacitor dielectric film and the step of forming the gate insulating film for low breakdown voltage are the same step. The case where it does is demonstrated.

  (A) As shown in FIG. 15, for example, by thermally oxidizing the semiconductor substrate 1, a high breakdown voltage gate insulating film of the MISFET and a dielectric film of the capacitor are formed in the capacitor forming region including the MISFET forming region and the capacitor forming groove 4a. A silicon oxide film 14 having a thickness of about 12 to 16 nm is formed.

  (B) Next, as shown in FIGS. 16 and 17, a resist pattern 123 is formed on the entire surface of the memory cell formation region and the entire region of the MISFET formation region and the capacitor formation region where the high voltage gate insulating film is used. To do. That is, the resist pattern 123 is formed so as to expose the entire surface of the MISFET formation region and the capacitor formation region where the low breakdown voltage gate insulating film is used.

  Next, as shown in FIG. 18, the silicon oxide film 14 formed in the region where the MISFET and the low breakdown voltage gate insulating film of the capacitor are used is removed by, for example, dry etching.

  Next, as shown in FIG. 19, after removing the resist pattern 123, the semiconductor substrate 1 is thermally oxidized, for example, to form a low breakdown voltage gate insulating film of the MISFET and the capacitor having a thickness of about 4 to 8 nm. A low breakdown voltage gate insulating film 15 and a dielectric film 15a are formed by forming a silicon oxide film.

  As shown in FIG. 20, by this thermal oxidation, the silicon oxide film 14 in the region where the high breakdown voltage gate insulating film of the MISFET and the capacitor is used is oxidized, and the high breakdown voltage gate insulating film 16 having a thickness of about 15 to 20 nm. And the dielectric film 16a is formed. That is, the high breakdown voltage gate insulating film 16 is formed in a region where the high breakdown voltage gate insulating film is used in the MISFET formation region and the capacitor formation region.

  On the other hand, as shown in FIG. 19, the low breakdown voltage gate insulating film 15 is formed in a region where the low breakdown voltage gate insulating film is used in the MISFET formation region and the capacitor formation region. The silicon oxide film serving as the low breakdown voltage gate insulating film 15 functions as a low breakdown voltage gate insulating film of the MISFET and a capacitor dielectric film of the capacitor.

  In the first embodiment, the subsequent steps are mainly described in which the capacitor dielectric film is made of the same film as (a) the gate insulating film for high breakdown voltage, but (b) the gate for low breakdown voltage. Also in the case of describing the insulating film, since the subsequent manufacturing method is performed in the same procedure, the description thereof is omitted except for a part.

  Next, as shown in FIG. 21, on the NONO film 11 formed in the memory cell and on the low breakdown voltage gate insulating film 15 and the high breakdown voltage gate insulating film 16 formed in the MISFET and the capacitor, for example, a memory A polycrystalline silicon layer 17 to be a control gate electrode (memory gate electrode) 17a (see FIG. 2) of the cell is formed. Subsequently, for example, a silicon oxide film 18 is deposited on the polycrystalline silicon layer 17 as an insulating film serving as a cap layer of the memory cell by a CVD method.

  Next, as shown in FIG. 22, a resist pattern 124 is formed on the silicon oxide film 18, and the silicon oxide film 18, the polycrystalline silicon film 17, the NONO film 11 and the polycrystalline silicon layer 10a are dry-etched. A control gate electrode (memory gate electrode) 17a of the memory cell, a floating gate electrode (charge storage layer) 10, a gate electrode 17b of the high breakdown voltage and low breakdown voltage MISFET, and a capacitor electrode 17c of the capacitor are formed. Through the steps so far, the memory gate electrode structure 20 including the memory tunnel insulating film 9, the floating gate electrode 10, the memory gate interlayer film 11, the control gate electrode 17a, and the silicon oxide film 18 can be formed.

  The control gate electrode (memory gate electrode) 17a of the memory cell may have a polycide structure in which a silicide film such as a cobalt silicide (CoSi) film is formed on a polycrystalline silicon layer.

  Next, as shown in FIG. 23, after covering the entire surface of the MISFET formation region and the capacitor formation region with a resist, in the memory cell formation region, for example, arsenic (As) or the like is self-aligned with the memory gate electrode structure 20. By introducing N-type impurities by an ion implantation method, N-type impurity layers 23a and 23b serving as source / drain regions of the memory cell are formed. Subsequently, after covering the entire surface of the memory cell formation region and the capacitor formation region with a resist, an N-type impurity such as phosphorus (P) is ion-implanted in the MISFET formation region in a self-aligned manner with respect to the gate electrode portion 21, for example. By introducing, an N-type impurity layer 24a to be a source / drain region of the MISFET is formed.

  When the gate insulating film of the MISFET is the low breakdown voltage gate insulating film 15, arsenic (As) ions are introduced by an implantation method to form the N-type impurity layer 24b (see FIG. 3).

  Next, as shown in FIG. 24, a silicon nitride film 25 having a thickness of about 110 to 150 nm is deposited on the main surface, that is, the entire surface of the memory cell formation region, the MISFET formation region, and the capacitor formation region by, eg, CVD. . Subsequently, after covering the entire surface of the memory cell formation region with a resist, the silicon nitride film 25 in the MISFET formation region and the capacitor formation region is subjected to anisotropic dry etching, thereby forming a sidewall on the sidewalls of the gate electrode and the capacitor electrode of the MISFET. 26 is formed.

  Next, an N-type impurity such as arsenic (As) is introduced in a self-aligned manner into the gate electrode portion 21, the capacitor upper electrode portion 22 and the sidewalls 26 of the MISFET by an ion implantation method, so that the source / drain of the MISFET An N-type impurity layer 27a serving as a region and an N-type impurity region 28a serving as a diffusion layer of a lower electrode pull-up portion of the capacitor are formed.

  Next, after depositing, for example, a silicon oxide film (see FIGS. 2 and 3) as an interlayer insulating film 29 on the main surface, that is, the entire memory cell formation region, MISFET, and capacitor formation region by the CVD method, the CMP method is used. The surface is flattened.

  Next, after covering the entire surface of the MISFET formation region and the capacitor formation region with a resist, the interlayer insulating film 29 is patterned, and connection holes reaching the N-type impurity layers 23a and 23b in the memory cell forming region are formed in the interlayer insulating film 29. CONT1 (see FIG. 2) is formed.

  Next, as shown in FIG. 25, after covering the entire surface of the memory cell formation region with a resist cover, the interlayer insulating film 29 is patterned to expose the N-type impurity layers 24a and 27a in the MISFET formation region. CONT2 (see FIGS. 2 and 3), a connection hole CONT3 (see FIGS. 2 and 3) reaching the N-type impurity layer 28a of the lower electrode pull-up portion of the capacitor, and a connection hole CONT4 (see FIG. 2) reaching the capacitor upper electrode structure 22 2 and FIG. 3).

  Next, a TiN film is deposited on the interlayer insulating film 29 including the inside of the connection holes CONT1 to CON4 using, for example, a sputtering method. Subsequently, by depositing a W film on the TiN film using a CVD method, the connection holes CONT1 to CONT4 are filled with the W film. Next, the W film and the TiN film on the interlayer insulating film 29 are removed by CMP to leave the W film and the TiN film in the connection holes CONT1 to CONT4, thereby forming plugs made of the W film and the TiN film.

  Next, an interlayer insulating film 32 (see FIGS. 2 and 3) made of a silicon oxide film is deposited on the interlayer insulating film 29 and the plug layer 33a by using, for example, a CVD method. Subsequently, after forming a lead-out wiring hole 33b (see FIGS. 2 and 3) to the plug layer 33a, for example, a W film is embedded in the lead-out wiring hole 33b by a sputtering method, and the W film is etched back. A wiring layer 33 (see FIG. 2) electrically connected to the N-type impurity layers 23a and 23b formed in the capacitor, and a wiring electrically connected to the N-type impurity layers 24a and 27a formed in the high voltage MISFET Layer 34a (see FIG. 2), wiring layer 34b (see FIG. 3) electrically connected to N-type impurity layers 24b and 27b formed in the low breakdown voltage MISFET, and N-type impurity layer 28a formed in the capacitor. , 28b are electrically connected to wiring layers 35a (see FIG. 2) and 35b (see FIG. 3), and wiring layers 36a (see FIG. 2) are electrically connected to the capacitor upper electrode 17c. ) And forming the wiring layer 36b (see FIG. 3).

  Based on the above embodiment, the structure shown in FIG. 2 can be formed. Further, FIG. 3 shows a drawing in which a low-voltage gate insulating film is used for the gate insulating film of the MISFET and the capacitor dielectric film of the capacitor.

  According to the first embodiment, the element isolation trench 4 and the capacitor formation trench 4a can be formed in the same process. Further, the step of forming the high breakdown voltage gate insulating film 16 or the low breakdown voltage gate insulating film 15 of the MISFET and the dielectric film 16a or the dielectric film 15a of the capacitor can be formed in the same process. That is, the high breakdown voltage gate insulating film 16 or the low breakdown voltage gate insulating film 15 and the insulating film used for forming the capacitor dielectric film 16a or the dielectric film 15a are formed in the same process. Further, the step of forming the gate electrode 17b of the MISFET and the capacitor electrode 17c can be formed in the same step. That is, the conductor film used for forming the gate electrode 17b of the MISFET and the capacitor electrode 17c is formed in the same process. Thus, the manufacturing process of the semiconductor device of the first embodiment can be simplified.

(Embodiment 2)
Next, FIG. 25 shows a structure of a main part of the semiconductor device according to the second embodiment.

  In the first embodiment, as shown in FIG. 9, in the step of removing the silicon oxide film 5 embedded in the capacitor formation groove 4a, the mask as shown in FIG. 14 is used as the resist pattern. In the second embodiment, a part of the element isolation trench 4 may be used as a part of the capacitor formation region by performing patterning using the mask shown in FIGS.

  In addition, in order to make the explanation easy to understand, in the following process, the description of the same part as the first embodiment is omitted.

  First, after the step shown in FIG. 12 in the first embodiment, on the silicon oxide film 5 embedded in the element isolation trench 4 (see FIG. 12) and at least one capacitor formation trench 4a, FIG. A resist pattern 125 shown in FIG. 28 is formed, and dry etching is performed using the resist pattern 125 as a mask, thereby removing the silicon oxide film 5 embedded in the capacitor forming groove 4a and part of the element isolation groove 4.

  Next, similarly to the steps shown in FIG. 15 and subsequent drawings of the first embodiment, a gate insulating film (low-voltage gate insulating film 15 or high-voltage gate insulating film 16) of the MISFET is formed.

  Since the subsequent steps are the same as those in the first embodiment, description thereof is omitted.

  As described above, in the present second embodiment, the capacitance per unit area of the capacitor is increased by using a part of the element isolation trench 4 as a part of the capacitor formation region without adding a manufacturing process. Can do.

  Further, although the second embodiment has been described based on the first embodiment, it can be similarly implemented in the following embodiments.

(Embodiment 3)
FIG. 29 shows the structure of the main part of the semiconductor device according to the third embodiment.

  In the first embodiment, the step of forming the gate insulating film (low-voltage gate insulating film 15 and high-voltage gate insulating film 16) of the MISFET and the step of forming the dielectric films 15a and 16a of the capacitor are the same. In the third embodiment, the NONO film 11 that is the memory gate interlayer film (second memory gate insulating film) of the memory cell and the capacitor dielectric film of the capacitor are formed of the same dielectric film. Formed. That is, the step of forming the NONO film 11 which is the memory gate interlayer film (second memory gate insulating film) of the memory cell is the same as the step of forming the capacitor dielectric film of the capacitor.

  In addition, in order to make the explanation easy to understand, in the following process, the description of the same part as the first embodiment is omitted. In the MISFET, the gate insulating film is separately formed for the high breakdown voltage and the low breakdown voltage as in the first embodiment, but the high breakdown voltage will be mainly described.

  After the step of forming the polycrystalline silicon layer 10a to be the floating gate electrode (electrode charge storage layer) of the memory cell shown in FIG. 10 in the first embodiment, the polycrystalline silicon layer 10a is formed, After covering the entire surface of the memory cell and MISFET formation region with a resist, the polycrystalline silicon layer 10a formed in the capacitor formation region is removed by dry etching.

  Next, as shown in FIG. 30, after covering the entire area of the memory cell formation region and MISFET formation region and the capacitor formation region except the capacitor formation groove 4a with a resist pattern 126, the memory tunnel insulating film 9 in the capacitor formation region is covered. The silicon oxide film 5 embedded in the capacitor formation groove 4a is sequentially removed by dry etching.

  Next, as shown in FIG. 31, a NONO film 11 serving as a gate interlayer film of the memory cell is formed on the entire surface of the memory cell formation region, the MISFET formation region, and the capacitor formation region in the same process as in the first embodiment. To do. That is, the insulating film used for forming the memory gate interlayer film 11 and the dielectric film of the capacitor is formed in the same process.

  Next, as shown in FIG. 32, after covering the entire surface of the memory cell and capacitor formation region with a resist 127, the NONO film 11, the polycrystalline silicon layer 10a, and the memory tunnel insulating film 9 formed in the MISFET formation region are dried. Remove by etching. Further, as shown in FIG. 33, the region where the low breakdown voltage gate insulating film 15 is formed is also removed.

  Subsequently, a high breakdown voltage gate insulating film 16 and a low breakdown voltage gate insulating film 15 are formed in the MISFET formation region. As to the method of forming the high breakdown voltage gate insulating film 16 and the low breakdown voltage gate insulating film 15, as in the first embodiment, (a) a high breakdown voltage gate insulating film, (b) a low breakdown voltage gate insulating film, Since the manufacturing method is the same, the description thereof is omitted (see FIGS. 34 and 35).

  Next, as shown in FIG. 36, the control gate electrode (memory gate electrode) 17a of the memory cell is formed on the NONO film 11 formed in the memory cell and capacitor formation region and on the gate insulating film formed in the MISFET formation region. A polycrystalline silicon film to be formed and a silicon oxide film 18 to be a cap layer are sequentially deposited by a CVD method.

  Next, a resist pattern 128 is formed, and a memory gate electrode structure 20, a MISFET gate electrode structure 21 and a capacitor upper electrode structure 22 are formed by dry etching using the resist pattern 128. That is, the conductor film used for forming the memory gate electrode structure 20, the MISFET gate electrode structure 21 and the capacitor upper electrode structure 22 is formed in the same process.

  In the following, the semiconductor device having the nonvolatile memory shown in FIG. 29 can be formed through the same manufacturing process as in the first embodiment, and the description thereof is omitted.

  As described above, the capacitor dielectric film of the capacitor and the memory gate interlayer film of the memory cell are formed in the same process, whereby the manufacturing process can be simplified. Further, by using the NONO film 11 instead of the low breakdown voltage gate insulating film 15 or the high breakdown voltage gate insulating film 16 of the MISFET as the capacitor dielectric film of the capacitor, a highly reliable capacitor dielectric film can be obtained. it can.

(Embodiment 4)
Next, FIG. 37 shows the structure of the main part of the semiconductor device according to the fourth embodiment.

  In the first embodiment, the polycrystalline silicon layer 10a is formed as the charge storage layer of the memory cell as shown in FIGS. 10 to 22 in the process of forming the memory cell, but the silicon nitride film 41 is used as the charge storage layer. It is formed using. Note that the silicon nitride film 41 accumulates charges by capturing electrons trapped in the silicon nitride film 41.

  In addition, in order to make the explanation easy to understand, in the following process, the description of the same part as the first embodiment is omitted.

  After the process shown in FIG. 10 in the first embodiment, as shown in FIG. 38, a silicon nitride film 41 and a silicon oxide film 42 are sequentially deposited on the memory tunnel insulating film 9 by using, for example, the CVD method. . The silicon nitride film 41 serves to store charges as a substitute for the floating gate electrode of the memory cell.

  Next, as shown in FIG. 39, the entire surface of the memory cell formation region is covered with a resist pattern 129, and the silicon oxide film 42, the silicon nitride film 41, and the memory tunnel insulating film 9 formed in the MISFET formation region and the capacitor formation region are formed. Etch and remove sequentially. Next, the resist pattern 122 shown in FIG. 14 in the first embodiment is formed, and the silicon oxide film 5 embedded in the capacitor formation groove 4a is removed.

  Subsequently, as shown in FIG. 40, the MISFET gate insulating film (the low breakdown voltage gate insulating film 15 and the high breakdown voltage gate insulating film 16) and the dielectric film 16a are applied to the MISFET formation region and the capacitor formation region, respectively. It is formed by the same process as that of Form 1.

  Next, as shown in FIG. 41, the low breakdown voltage gate insulating film 15 or the high breakdown voltage gate insulating film formed on the silicon oxide film 42 formed in the memory cell formation region and in the MISFET formation region and the capacitor formation region. A polycrystalline silicon film 44 and a silicon oxide film 45 are sequentially deposited on the film 16 by CVD.

  Next, as shown in FIG. 42, patterning is performed using the resist pattern 130 as a mask to form a memory gate electrode 44a, a MISFET gate electrode 44b, and a capacitor upper electrode 44c. That is, the memory gate electrode 44a, the gate electrode 44b of the MISFET and the upper electrode 44c of the capacitor are formed of the same conductive film, and the conductive material used for forming the memory gate electrode 44a, the gate electrode 44b of the MISFET and the upper electrode 44c of the capacitor. A body membrane is formed in the same process. Through the steps so far, the memory gate electrode structure 40 including the memory tunnel insulating film 9, the silicon nitride film 41, the silicon oxide film 42, the memory gate electrode 44a, and the silicon oxide film 45 can be formed.

  Thereafter, the semiconductor device having the non-volatile memory shown in FIG. 37 is formed through the same steps as in the first embodiment, and the description thereof is omitted.

  As described above, in the fourth embodiment, the charge storage layer of the memory cell is formed using the silicon nitride film 41 instead of the polycrystalline silicon layer 10a in the first embodiment. Compared with the case where charge is accumulated in a certain polycrystalline silicon layer 10a, the electron traps in the silicon nitride film 41 are discontinuous and discrete, so that a charge leakage path such as a pinhole is formed in a part of the memory tunnel insulating film 9. Even in the case of the occurrence of the occurrence, all the accumulated charges are not lost, and the retention characteristic can be essentially strengthened.

  Further, instead of the silicon nitride film 41, a so-called Si nanodot made of silicon spheres having a diameter of several nm may be used to form the charge storage layer of the memory cell, and in this case as well, the same as in the fourth embodiment described above. An effect is obtained.

(Embodiment 5)
Next, FIG. 43 shows the structure of the main part of the semiconductor device according to the fifth embodiment.

  In the fourth embodiment, as a modification of the first embodiment, the memory gate electrode structure 40 is formed instead of the memory gate electrode structure 20, but in the fifth embodiment, the memory gate electrode structure shown in FIG. 50, it is formed in a so-called split gate type.

  In addition, in order to make the explanation easy to understand, in the following process, the description of the same part as the first embodiment is omitted.

  After the step shown in FIG. 10 of the first embodiment, as shown in FIG. 44, a polycrystalline silicon film 51 and a silicon oxide film 52 are sequentially deposited on the memory tunnel insulating film 9 by, eg, CVD. Note that the silicon oxide film 52 may be formed by thermally oxidizing the surface of the polycrystalline silicon film 51.

  Next, as shown in FIG. 45, after a resist pattern 131 is formed on the silicon oxide film 52 in the memory cell formation region, the silicon oxide film 52, the polycrystalline silicon film 51, and the memory tunnel insulating film 9 are sequentially patterned. Selectively remove. The charge storage layer of the memory cell is formed of a polycrystalline silicon film 51.

  Next, as shown in FIG. 46, a resist pattern 132 is formed using a mask similar to the mask shown in FIG. 14 in the first embodiment, and the silicon oxide film formed in the capacitor formation groove 4a of the capacitor. 5 is selectively removed.

  Next, as shown in FIG. 47, a silicon oxide film to be the gate insulating film 53 of the MISFET is formed by using, for example, a CVD method. Further, the silicon oxide film to be the gate insulating film 53 of the MISFET is a process in which the high breakdown voltage gate insulating film 16 (see FIG. 2) and the low breakdown voltage gate insulating film 15 (see FIG. 3) in the first embodiment are formed. You may make separately by the same process.

  Next, as shown in FIG. 48, a polycrystalline silicon film 54 and a silicon oxide film 55 are sequentially deposited on the gate insulating film 53 by using, for example, a CVD method.

  Next, as shown in FIG. 49, by forming a resist pattern 133 and selectively removing the silicon oxide film 55 and the polycrystalline silicon film 54 by patterning, the memory gate electrode 54a, the gate electrode 54b of the MISFET, and the capacitor The upper electrode 54c can be formed. Through the steps so far, the memory gate electrode structure 50 including the memory tunnel insulating film 9, the polycrystalline silicon film 51, the silicon oxide film 52, the gate insulating film 53, the memory gate electrode 54a, and the silicon oxide film 55 can be formed. .

  Thereafter, the semiconductor device having the non-volatile memory shown in FIG. 43 can be formed through the same manufacturing process as in the first embodiment, and the description thereof is omitted.

  Thus, even when the memory gate electrode portion has a structure as shown in the fifth embodiment, the same effect as in the first embodiment can be obtained.

(Embodiment 6)
Next, FIG. 50 shows the structure of the main part of the semiconductor device of the sixth embodiment.

  In the first embodiment, the polycrystalline silicon layer 17 (see FIG. 21) which is the control gate electrode 17a (see FIG. 2) of the memory cell is used as the gate electrode of the MISFET and the upper electrode of the capacitor. In the sixth embodiment, this is formed by using the polycrystalline silicon layer 10a serving as the floating gate electrode 10 (see FIG. 2) of the memory cell and the polycrystalline silicon layer 17 serving as the control gate electrode 17a. .

  In addition, in order to make the explanation easy to understand, in the following process, the description of the same part as the first embodiment is omitted.

  After the step shown in FIG. 9 of the first embodiment, as shown in FIG. 51, the region other than the capacitor formation groove 4a is covered with a resist pattern 134, and the silicon oxide film 5 embedded in the capacitor formation groove 4a is etched. And remove.

  Next, as shown in FIG. 52, for example, the semiconductor substrate 1 is thermally oxidized to form the gate insulating film 60 in the MISFET formation region, and at the same time, the gate insulating film 60 is also formed on the capacitor forming groove 4a. Here, the gate insulating film 60 is formed by a process similar to the process of forming the high breakdown voltage gate insulating film 16 (see FIG. 2) and the low breakdown voltage gate insulating film 15 (see FIG. 3) in the first embodiment. It may be divided. At this time, an oxide film similar to the gate insulating film 60 is also formed in the memory cell formation region.

  Next, after covering the entire surface of the MISFET formation region and the capacitor formation region with a resist, the oxide film on the surface of the memory cell formation region is removed by etching. Thereafter, the semiconductor substrate 1 is thermally oxidized to form a silicon oxide film 61 serving as a memory tunnel insulating film in the memory cell formation region.

  Next, as shown in FIG. 53, after depositing a polycrystalline silicon film 63 to be a floating gate electrode (charge storage layer) of the memory cell on the entire surface of the semiconductor substrate 1 using the CVD method, The resulting NONO film 64 is formed on the polycrystalline silicon film 63.

  Next, as shown in FIG. 54, after selectively removing a part of the NONO film 64 formed in the MISFET formation region and the capacitor formation region, the CVD is performed on the exposed polycrystalline silicon film 63 and the NONO film 64. Using this method, a polycrystalline silicon film 65 to be a control gate electrode (memory gate electrode) of a memory cell and a silicon oxide film 66 to be a cap layer are sequentially deposited. Thereby, the polycrystalline silicon film 63 and the polycrystalline silicon film 65 formed in the MISFET formation region and the capacitor formation region can be made conductive. Thereafter, the silicon oxide film 66, the polycrystalline silicon film 65, the NONO film 64, the polycrystalline silicon film 63 and the silicon oxide film 61 are selectively removed by patterning by dry etching using a resist pattern, as shown in FIG. Such memory gate electrodes 63a and 65a, MISFET gate electrodes 63b and 65b, and capacitor upper electrodes 63c and 65c can be formed.

  Thereafter, the semiconductor device having the nonvolatile memory of the sixth embodiment shown in FIG. 50 can be formed through the same manufacturing method as that of the first embodiment, and the description thereof is omitted.

  As described above, the floating gate electrode and the memory gate electrode of the memory cell are formed in the same process as the gate electrode of the MISFET and the capacitor upper electrode. That is, the floating gate electrode and the memory gate electrode of the memory cell, the gate electrode of the MISFET and the capacitor upper electrode are formed of the same conductive film, the floating gate electrode and the memory gate electrode of the memory cell, and the gate electrode of the MISFET And the conductor film used for formation with the capacitor upper electrode is formed in the same process. By forming in this way, the manufacturing process can be simplified.

  Thus, instead of forming the gate electrode of the MISFET and the capacitor upper electrode only from the polycrystalline silicon film that becomes the control gate electrode of the memory cell, the polycrystalline silicon film that becomes the floating gate electrode of the memory cell and the control gate electrode, Even when both of the polycrystalline silicon films are used, the same effects as those of the first to fifth embodiments can be obtained.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, each of the first to sixth embodiments may be combined with one or more of the other embodiments.

1 is a main part plan view of a semiconductor device according to a first embodiment of the present invention; It is principal part sectional drawing of the semiconductor device which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor device which is Embodiment 1 of this invention. It is principal part sectional drawing explaining the manufacturing method of the semiconductor device which is Embodiment 1 of this invention. FIG. 5 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4; It is a principal part top view in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. It is a principal part top view in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. It is a principal part top view in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. 6 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5; FIG. FIG. 10 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 9; FIG. 11 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 10; FIG. 12 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11; FIG. 13 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 12; It is a principal part top view in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. FIG. 14 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 13; FIG. 16 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 15; It is principal part sectional drawing in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. FIG. 18 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 17; FIG. 19 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 18; FIG. 17 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 16; FIG. 21 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 20; FIG. 22 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 21; FIG. 23 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 22; FIG. 24 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 23; It is a principal part top view in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor device which is Embodiment 2 of this invention. It is principal part sectional drawing explaining the manufacturing method of the semiconductor device which is Embodiment 2 of this invention. It is a principal part top view in the manufacturing process of the semiconductor device which is Embodiment 2 of this invention. It is principal part sectional drawing of the semiconductor device which is Embodiment 3 of this invention. It is principal part sectional drawing explaining the manufacturing method of the semiconductor device which is Embodiment 3 of this invention. FIG. 31 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 30; FIG. 32 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 31; It is principal part sectional drawing in the manufacturing process of the semiconductor device which is Embodiment 3 of this invention. FIG. 33 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 32; FIG. 34 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 33; FIG. 35 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 34; It is principal part sectional drawing of the semiconductor device which is Embodiment 4 of this invention. It is principal part sectional drawing explaining the manufacturing method of the semiconductor device which is Embodiment 4 of this invention. FIG. 39 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 38; FIG. 40 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 39; FIG. 41 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 40; FIG. 42 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 41; It is principal part sectional drawing of the semiconductor device which is Embodiment 5 of this invention. It is principal part sectional drawing explaining the manufacturing method of the semiconductor device which is Embodiment 5 of this invention. FIG. 45 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 44; FIG. 46 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 45; FIG. 47 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 46; FIG. 48 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 47; FIG. 49 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 48; It is principal part sectional drawing of the semiconductor device which is Embodiment 6 of this invention. It is principal part sectional drawing explaining the manufacturing method of the semiconductor device which is Embodiment 6 of this invention. FIG. 52 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 51; FIG. 53 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 52; FIG. 54 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 53;

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Silicon oxide film 3 Silicon nitride film 4 Element isolation groove 4a Capacitor formation groove 5 Silicon oxide film 7 P-type impurity layer (P-type well region)
8 N-type impurity layer (N-type well region)
9 Memory tunnel insulating film 10 Floating gate electrode 10a Polycrystalline silicon layer 11 Memory gate interlayer film (NONO film)
11a Multilayer film 13 Silicon nitride film 14 Silicon oxide film (high-voltage gate insulating film)
DESCRIPTION OF SYMBOLS 15 Low breakdown voltage gate insulating film 15a Dielectric film 16 High breakdown voltage gate insulating film 16a Dielectric film 17 Polycrystalline silicon layer 17a Control gate electrode 17b Gate electrode 17c Capacitor electrode 18 Silicon oxide film 20 Memory gate electrode structure 21 Gate electrode structure 22 Capacitor upper electrode structure 23a, 23b, 24a, 24b N-type impurity layer 25 Silicon nitride film 26 Side wall 27a, 27b, 28a, 28b N-type impurity layer 29 Interlayer insulating film 32 Interlayer insulating film 33 Wiring layer 33a Plug layer 33b Lead Wiring hole 34a, 34b Wiring layer 35a, 35b Wiring layer 36a, 36b Wiring layer 40 Memory gate electrode structure 41 Silicon nitride film 42 Silicon oxide film 44 Polycrystalline silicon film 44a Memory gate electrode 44b Gate electrode 44c Upper electrode 45 Silicon oxide film 50 Memory gate electrode structure 51 Polycrystalline silicon film 52 Silicon oxide film 53 Gate insulating film 54 Polycrystalline silicon film 54a Memory gate electrode 54b Gate electrode 54c Upper electrode 55 Silicon oxide film 60 Gate insulating film 61 Silicon oxide film 63 Poly Crystal silicon film 63a Memory gate electrode 63b Gate electrode 63c Capacitor upper electrode 64 NONO film 65 Polycrystalline silicon film 65a Memory gate electrode 65b Gate electrode 65c Capacitor upper electrode 66 Silicon oxide films 121-134 Resist pattern

Claims (14)

The semiconductor substrate has a memory cell formation region, a MISFET formation region, and a capacitor formation region.
In a method of manufacturing a semiconductor device having a memory cell formed in the memory cell formation region, a first MISFET formed in the MISFET formation region, and a capacitor formed in the capacitor formation region,
Simultaneously forming, in the semiconductor substrate, an element isolation trench for isolating the memory cell, the first MISFET, and the capacitor, and a plurality of capacitor formation trenches in the capacitor formation region;
Forming a well serving as a lower electrode of the capacitor in the capacitor formation region;
Forming a first gate insulating film of the first MISFET in a formation region of the first MISFET;
Forming a first memory gate insulating film in the memory cell formation region;
Forming a charge storage layer on the first memory gate insulating film;
Simultaneously forming a second memory gate insulating film on the charge storage layer and a capacitor dielectric film on the plurality of capacitor formation grooves;
A first conductive film serving as a memory gate electrode on the second memory gate insulating film; a first conductive film serving as a first gate electrode on the first gate insulating film; and a capacitor formed on the capacitor dielectric film. Simultaneously forming the first conductive film to be an upper electrode;
A method for manufacturing a semiconductor device, comprising: The semiconductor substrate has a memory cell formation region and a capacitor formation region,
In a method of manufacturing a semiconductor device having a memory cell formed in the memory cell formation region and a capacitor formed in the capacitor formation region,
Simultaneously forming, in the semiconductor substrate, element isolation trenches for isolating the memory cells and the capacitors, and a plurality of capacitor formation trenches in the capacitor formation region;
Forming a well serving as a lower electrode of the capacitor in the capacitor formation region;
Forming a first memory gate insulating film in the memory cell formation region;
Forming a charge storage layer on the first memory gate insulating film;
Simultaneously forming a second memory gate insulating film on the charge storage layer and a capacitor dielectric film on the plurality of capacitor formation grooves;
Simultaneously forming a first conductive film to be a memory gate electrode on the second memory gate insulating film and a first conductive film to be an upper electrode of the capacitor on the capacitor dielectric film;
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device of Claim 1 or 2,
The method of manufacturing a semiconductor device, wherein the second memory gate insulating film and the capacitor dielectric film include a laminated film made of a silicon oxide film and a silicon nitride film. In the manufacturing method of the semiconductor device as described in any one of Claims 1-3,
The method of manufacturing a semiconductor device, wherein the charge storage layer includes a polycrystalline silicon film. In the manufacturing method of the semiconductor device according to any one of claims 1 to 4,
The method of manufacturing a semiconductor device, wherein the memory gate electrode includes a polycrystalline silicon film and a silicide. In the manufacturing method of the semiconductor device according to any one of claims 1 to 5,
The method of manufacturing a semiconductor device, wherein the plurality of capacitor forming grooves are formed in a hole shape, a stripe shape, or a lattice shape. In the manufacturing method of the semiconductor device according to any one of claims 1 to 6,
Before forming the capacitor dielectric film on the plurality of capacitor formation grooves,
Burying an insulating film in the element isolation trench and the plurality of capacitor formation trenches simultaneously;
Removing the insulating film buried in the plurality of capacitor formation grooves simultaneously;
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to any one of claims 1 to 7,
Before forming the capacitor dielectric film on the plurality of capacitor formation grooves,
Embedding an insulating film in the element isolation trench and the plurality of capacitor formation trenches;
And a step of simultaneously removing a part of the insulating film embedded in the element isolation trench and the insulating film embedded in the plurality of capacitor forming trenches. The semiconductor substrate has a memory cell formation region, a MISFET formation region, and a capacitor formation region.
A semiconductor device having a memory cell formed in the memory cell formation region, a first MISFET formed in the MISFET formation region, and a capacitor formed in the capacitor formation region,
An element isolation groove formed on the semiconductor substrate and separating the memory cell, the first MISFET, and the capacitor;
A first gate insulating film formed in the MISFET formation region;
A first gate electrode formed on the first gate insulating film;
A charge storage layer formed in the memory cell formation region;
A memory gate insulating film formed on the charge storage layer;
A memory gate electrode formed on the memory gate insulating film;
A plurality of capacitor formation grooves formed in the capacitor formation region;
A well serving as a lower electrode of the capacitor formed in the capacitor formation region;
A capacitor dielectric film formed in the plurality of capacitor formation grooves;
A capacitor electrode formed on the capacitor dielectric film and serving as an upper electrode of the capacitor;
In a semiconductor device having
The element isolation trench and the plurality of capacitor formation trenches are formed with substantially the same depth,
The capacitor dielectric film and the memory gate insulating film are formed of the same dielectric film,
The semiconductor device, wherein the capacitor electrode, the first gate electrode, and the memory gate electrode are formed of the same conductive film. There are a memory cell formation region and a capacitor formation region on the semiconductor substrate,
A semiconductor device having a memory cell formed in the memory cell formation region and a capacitor formed in the capacitor formation region,
An isolation trench separating the memory cell and the capacitor;
A charge storage layer formed in the memory cell formation region;
A memory gate insulating film formed on the charge storage layer;
A memory gate electrode formed on the memory gate insulating film;
A plurality of capacitor formation grooves formed in the capacitor formation region;
A well serving as a lower electrode of the capacitor formed in the capacitor formation region;
A capacitor dielectric film formed in the plurality of capacitor formation grooves;
A capacitor electrode formed on the capacitor dielectric film and serving as an upper electrode of the capacitor;
In a semiconductor device having
The element isolation trench and the plurality of capacitor formation trenches are formed with substantially the same depth,
The capacitor dielectric film and the memory gate insulating film are formed of the same dielectric film,
The semiconductor device, wherein the capacitor electrode and the memory gate electrode are formed of the same conductive film. The semiconductor device according to claim 9 or 10,
The semiconductor device according to claim 1, wherein the memory gate insulating film and the capacitor dielectric film include a laminated film made of a silicon oxide film and a silicon nitride film. The semiconductor device according to any one of claims 9 to 11,
The semiconductor device according to claim 1, wherein the charge storage layer is formed of a polycrystalline silicon film. The semiconductor device according to any one of claims 10 to 12,
The semiconductor device, wherein the memory gate electrode includes a polycrystalline silicon film and a silicide. In the semiconductor device according to any one of claims 10 to 13,
The semiconductor device is characterized in that the plurality of capacitor forming grooves are formed in a hole shape, a stripe shape, or a lattice shape.

Images