JP2010153904A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2010153904A
JP2010153904A JP2010047579A JP2010047579A JP2010153904A JP 2010153904 A JP2010153904 A JP 2010153904A JP 2010047579 A JP2010047579 A JP 2010047579A JP 2010047579 A JP2010047579 A JP 2010047579A JP 2010153904 A JP2010153904 A JP 2010153904A
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formed
region
insulating film
film
control gate
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Japanese (ja)
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Takahiro Onakado
Satoru Shimizu
崇浩 大中道
悟 清水
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Renesas Technology Corp
株式会社ルネサステクノロジ
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can secure the reliability of operation and can obtain a high yield by suppressing the occurrence of a crystal defect in a silicon substrate. <P>SOLUTION: A trench isolation oxide film 3 is formed in a groove formed at the silicon substrate 2. Floating gate electrodes 10a-10d and control gate electrodes 12a-12d are formed on the trench isolation oxide film 3. Openings 3a which expose a surface of the silicon substrate 2 are formed in regions sandwiched by the floating gate electrodes etc. A BPTEOS film 16 is formed so that the openings 3a are embedded and the control gate electrodes are covered. Voids 21 are formed in the openings 3a embedded with the BPTEOS film 16. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly, to a semiconductor device in which crystal defects are suppressed from occurring in a semiconductor substrate in a semiconductor device manufacturing process or a completed semiconductor device.

  In recent years, a flash memory, which is a kind of nonvolatile semiconductor memory device, can be manufactured at a lower cost than a dynamic random access memory (DRAM), and thus is expected as a next-generation memory device. A memory cell of a flash memory is connected to a source region connected to a corresponding source line, a drain region connected to a corresponding bit line, a floating gate electrode for storing information, and a corresponding word line And a control gate electrode.

  Electrons are injected into the floating gate electrode due to the FN (Fowler Nordheim) tunnel phenomenon or the channel hot electron phenomenon of the gate insulating film made of a tunnel oxide film located directly below the floating gate electrode, or the floating gate electrode Information is erased or written by extracting the accumulated electrons. Thus, a binary state of a threshold value corresponding to the state of electrons in the floating gate electrode is created by injecting and extracting electrons from the floating gate electrode, and “0” or “1” is read out depending on the state. It will be.

  In addition to such a flash memory, the most commonly used memory cell configuration in a floating gate type nonvolatile semiconductor memory having a floating gate electrode such as an EEPROM (Electrically Erasable and Programmable Read Only Memory) is NOR. (Not OR) type array.

  In the NOR type array, a contact connected to the drain region of the memory cell in each row is formed. Bit lines are formed in the row direction using a polycide structure wiring of metal silicide and polysilicon, metal wiring, or the like. On the other hand, the gate lines of the memory cells in each column are formed in the column direction, and the bit lines and the gate lines are formed in a matrix.

  An example of the planar structure of such a conventional flash memory is shown in FIG. As shown in FIG. 43, control gate electrodes 112a, 112b, 112c, and 112d are formed at intervals so as to cross a plurality of element formation regions S partitioned by trench isolation oxide film 103. In portions where the control gate electrodes 112a, 112b, 112c, and 112d cross the element formation region S, floating gate electrodes 110a, 110b, 110c, and 110d are further formed immediately below the control gate electrodes, respectively.

  For example, a source region 106a is formed in one element formation region S with a control gate electrode 112b interposed therebetween, and a drain region 104b is formed in the other element formation region S. Each drain region is electrically connected to a bit line (not shown) through a contact hole 117.

  Each source region is electrically connected to each other by, for example, an impurity region of a predetermined conductivity type formed in a silicon substrate located immediately below a region sandwiched between control gate electrodes 112a and 112b. The structure of the source region in such a memory cell is particularly called a self-aligned source structure. In the self-aligned source structure, the source regions of the memory cells are not connected by wiring via contacts, but are connected by diffusion layer wiring. In other words, the diffusion layer wiring includes the source region.

  Next, a method for manufacturing this self-aligned source structure will be described. First, a photoresist pattern (not shown) is formed, leaving a region for forming a source region such as a region sandwiched between the control gate electrode 112a and the control gate electrode 112b shown in FIG.

  Using the photoresist pattern and the control gate electrodes 112a and 112b as a mask, the trench isolation oxide film 103 located in the region sandwiched between the control gate electrodes 112a and 112b is etched and removed to remove the trench isolation oxide film 103. The surface of the silicon substrate located immediately below is exposed.

  Next, each source region is formed by implanting ions of a predetermined conductivity type into the surface of the silicon substrate exposed in the region sandwiched between the control gate electrodes 112a and 112b, and each source region is formed in the column direction. The diffusion layer wiring to be connected is formed in a self-aligning manner.

  Accordingly, the cross-sectional structure taken along the cross-sectional line XLIV-XLIV shown in FIG. 43 is formed on the surface of the silicon substrate 102 including the surface of the groove 102a exposed by removing the trench isolation oxide film 103, as shown in FIG. Diffusion layer wiring 106 including the source region is formed in a self-aligned manner. The diffusion layer wiring 106 becomes a source region in the main surface portion of the silicon substrate 102 (region between the grooves 102a).

  On the other hand, in the cross sectional line XLV-XLV shown in FIG. 43, as shown in FIG. 45, the trench isolation oxide film 103 located in the region sandwiched between the control gate electrodes 112a and 112c and the control gate electrodes 112b and 112d is removed. Thus, an opening 103a exposing the surface of the silicon substrate 102 (the bottom of the groove 102a) is formed. A diffusion layer wiring 106 including a source region is formed on the exposed surface of the silicon substrate 102.

  Thereafter, as shown in FIGS. 44 and 45, sidewall insulating films 114a are formed on the side surfaces of the control gate electrodes 112a to 112d including the side surface of the opening 103a. Further, a TEOS (Tetra Ethyl Ortho Silicate Glass) film 115 is formed so as to cover the control gate electrodes 112a to 112d.

  Next, as shown in FIG. 46 and FIG. 47, a BPTEOS (Boro Phospho Tetra Ethyl Ortho Silicate Glass) film 116 serving as an interlayer insulating film is formed on the TEOS film 115. Next, as shown in FIGS. 48 and 49, the surface of the BPTEOS film 116 is flattened by subjecting the BPTEOS film 116 to heat treatment or polishing treatment. In this way, the main part of the NOR type flash memory is completed.

  According to this flash memory, since the self-aligned source structure is adopted as the source region in the memory cell, it is not necessary to electrically connect each source region via the contact. That is, the source region of the memory cell is formed in a region sandwiched between two adjacent control gate electrodes based on the minimum design rule, so that the memory cell can be miniaturized or highly integrated. it can.

JP-A-8-97379 JP-A-9-186232 JP-A-10-229121

  As described above, according to the flash memory adopting the self-aligned source structure, the source region is formed in a region sandwiched between two adjacent control gate electrodes based on the minimum design rule, so that the memory cell Miniaturization can be achieved.

  Further, as described above, a trench isolation structure using the trench isolation oxide film 103 is employed as an isolation structure for electrically isolating elements. In this trench isolation structure, further miniaturization can be achieved as compared with the conventional LOCOS isolation structure. In the trench isolation structure, as shown in FIG. 44, a trench 102a is formed in a silicon substrate 102 at a relatively steep angle, and an oxide film is buried in the trench 102a to form a trench isolation oxide film 103.

  However, in the flash memory described above, as shown in FIG. 45, when forming the source region of the self-aligned structure, the trench isolation oxide film 103 buried in the trench 102a is sandwiched between two adjacent control gate electrodes. The portion located in the region is removed to form an opening 103a that exposes the surface of the silicon substrate (groove 102a).

  As shown in FIG. 50 or 51, the substantial depth of the opening 103a is a depth obtained by adding the thickness of the control gate electrodes 112a to 112d and the floating gate electrodes 110a to 110d to the depth of the groove 102a. Thus, the opening 103 a is the deepest opening in the pattern formed on the silicon substrate 2.

  FIG. 51 shows a cross-sectional structure in a portion closer to the element formation region along the cross-sectional line LI-LI shown in FIG. 43, and therefore floating under the control gate electrodes 112a to 112d via the ONO film 109. Gate electrodes 110a to 110d are respectively formed.

  When the opening 103a is deepest, the silicon substrate 102 located at the bottom of the opening 103a indicated by the dotted frame B is formed after the BPTEOS film 116 as an interlayer insulating film is formed so as to fill the opening 103a. The stress acting on is increased. This stress may cause crystal defects in the silicon substrate 102 in a later manufacturing process. Even in a completed semiconductor device, crystal stress may occur in the silicon substrate 102 due to the stress.

  As described above, in the memory cell region in the flash memory having the cell-aligned structure, the opening 103a formed in the region sandwiched between two adjacent control gate electrodes is buried with the interlayer insulating film such as the BPTEOS film 116, In particular, a stronger stress acts on the portion of the silicon substrate 102 located at the bottom of the opening 103a, and crystal defects are likely to occur in the silicon substrate 102.

  If crystal defects occur in the silicon substrate 102, for example, a leak current may be generated, and the flash memory may not perform a desired operation. Further, a desired operation cannot be performed as a semiconductor device, and the yield of the semiconductor device may be reduced.

  In the future, as the miniaturization further proceeds in the flash memory, the aspect ratio of the opening is further increased, and it is assumed that the stress acting on the silicon substrate is further increased in this portion. As a result, crystal defects are more likely to occur in the silicon substrate, and there is a concern that the reliability of the operation of the semiconductor device is impaired or the yield is lowered.

  The present invention has been made in order to solve the above-described problems, and provides a semiconductor device that suppresses the generation of crystal defects in a semiconductor substrate, ensures operational reliability, and provides a high yield. The purpose is to do.

  A first semiconductor device according to the present invention includes a semiconductor substrate having a main surface, a groove, a first insulating film, two conductive layers, an opening, a second insulating film, and a void. ing. The groove is formed in the main surface of the semiconductor substrate. The first insulating film is embedded in the trench. The two conductive layers are formed on the first insulating film at an interval. The opening is formed in the first insulating film and exposes the surface of the semiconductor substrate located immediately below the first insulating film sandwiched between the two wirings. The second insulating film is formed so as to fill the opening and cover the two conductive layers. The air gap is formed in the opening in which the second insulating film is embedded.

  According to this structure, in the manufacturing process of the semiconductor device after the second insulating film is formed, the stress acting on the semiconductor substrate is relieved by the gap formed in the opening, particularly at the bottom of the opening. In addition, not only during the manufacturing process but also in a completed semiconductor device, the stress acting on the silicon substrate is relieved by this gap. Thereby, generation of crystal defects in the semiconductor substrate is suppressed, for example, leakage current can be prevented, a desired operation is ensured, and a semiconductor device with a high yield can be obtained.

  Preferably, the gap extends from a position sandwiched between the first insulating films to a position sandwiched between the two conductive layers.

  In this case, the space between the two conductive layers reduces the capacitance between the two conductive layers, and the semiconductor device can operate at high speed.

  Preferably, the other conductive layer is formed on the semiconductor substrate, the two conductive layers cross each other, the element forming region separated by the first insulating film, and the one conductive layer of the two conductive layers sandwiched therebetween. An impurity region on one side of a predetermined conductivity type formed in the element formation region on the side where the first conductive layer is located, and an impurity region on the other side of the predetermined conductivity type formed in the element formation region on the opposite side to the side on which the other conductive layer is located The conductive layer includes a first electrode portion formed on the element formation region and a second electrode portion formed on the first electrode portion.

  In this case, a semiconductor element including the first electrode portion, the second electrode portion, one side and the other side impurity region is obtained in the element formation region.

  More preferably, the semiconductor device includes a conductive region formed on the surface of the semiconductor substrate located in a region sandwiched between two conductive layers, and the conductive region includes a one-side impurity region.

  In this case, the one side impurity region of the semiconductor element is electrically connected to the other part by the conductive region.

  Preferably, the first electrode portion includes a floating gate, the second electrode portion includes a control gate, the one side impurity region includes a source region, and the other side impurity region includes a drain region.

  In this case, a memory cell including a floating gate, a control gate, a source region, and a drain region is formed as a semiconductor element.

  A second semiconductor device according to the present invention includes a semiconductor substrate, a trench, an element isolation insulating film, an element formation region, a first gate wiring, a second gate wiring, a source region, and a drain region. And a conductive region, an opening, an interlayer insulating film, and a gap. The groove is formed in the semiconductor substrate. The element isolation insulating film is embedded in the trench. The element formation region is formed on the semiconductor substrate and is partitioned by an element isolation insulating film. The first gate wiring is formed so as to cross the element isolation insulating film and the element formation region, and includes a floating gate electrode and a control gate electrode. The second gate wiring is formed at a distance from the first gate wiring so as to cross the element isolation insulating film and the element formation region, and includes a floating gate electrode and a control gate electrode. The source region is formed in an element formation region sandwiched between the first gate wiring and the second gate wiring. The drain region is formed in the element formation region opposite to the source region with the first gate wiring interposed therebetween. The conductive region is formed in a semiconductor substrate in a region sandwiched between the first gate wiring and the second gate wiring and includes a source region. The opening is formed in the element isolation insulating film sandwiched between the first gate wiring and the second gate wiring, and exposes the surface of the semiconductor substrate forming the trench. The interlayer insulating film is formed on the semiconductor substrate so as to fill the opening and cover the first gate wiring and the second gate wiring. The air gap is formed in the opening in which the element isolation insulating film is embedded.

  According to this configuration, in the memory cell including the floating gate, the control gate, the source region, and the drain region, the stress acting on the semiconductor substrate located at the bottom portion of the opening during the manufacturing process after forming the interlayer insulating film is increased. It is relieved by the gap formed in the opening. Also in the completed semiconductor device, the stress acting on the semiconductor substrate is relieved by this gap. Thereby, generation of crystal defects in the semiconductor substrate is suppressed, for example, leakage current can be prevented, a desired operation of the memory cell is ensured, and a semiconductor device with a high yield can be obtained.

  Preferably, the air gap extends from a position sandwiched between the element isolation insulating films to a position sandwiched between the first gate wiring and the second gate wiring.

  In this case, the space between the first gate wiring and the second gate wiring reduces the line capacitance between the first gate wiring and the second gate wiring, so that the semiconductor device can operate at high speed. it can.

  A third semiconductor device according to the present invention includes a semiconductor substrate, a first insulating film, two wires, an opening, a second insulating film, and a gap. The first insulating film is formed on the semiconductor substrate. The two wirings are formed on the first insulating film at an interval. The opening is formed in the first insulating film sandwiched between the two wirings and exposes the surface of the semiconductor substrate. The second insulating film is formed on the semiconductor substrate so as to fill the opening and cover the wiring. The air gap is formed in the opening filled with the second insulating film.

  According to this structure, in the manufacturing process of the semiconductor device after the second insulating film is formed, the stress acting on the semiconductor substrate located particularly at the bottom of the opening is relieved by the gap formed in the opening. Also in the completed semiconductor device, the stress acting on the semiconductor substrate is relieved by this gap. Thereby, generation of crystal defects in the semiconductor substrate is suppressed, for example, leakage current can be prevented, a desired operation is ensured, and a semiconductor device with a high yield can be obtained.

  Preferably, the gap extends from a position sandwiched between the first insulating films to a position sandwiched between two wirings.

  In this case, the space between the two wirings reduces the line capacitance between the two wirings, so that the semiconductor device can operate at high speed.

1 is a diagram showing a planar structure of a memory cell region of a flash memory according to a first embodiment of the present invention. 3 is a diagram showing an equivalent circuit of a memory cell in the same embodiment. FIG. FIG. 3 is a cross-sectional view taken along a cross-sectional line III-III shown in FIG. 1 in the same embodiment. FIG. 4 is a cross-sectional view taken along a cross-sectional line IV-IV shown in FIG. 1 in the same embodiment. FIG. 5 is a cross-sectional view taken along a cross-sectional line VV shown in FIG. 1 in the same embodiment. FIG. 6 is a cross-sectional view taken along a cross-sectional line VI-VI shown in FIG. 1 in the same embodiment. FIG. 7 is a cross-sectional view taken along a cross-sectional line VII-VII shown in FIG. 1 in the same embodiment. In the embodiment, it is sectional drawing in sectional line VV which shows 1 process of the manufacturing method of flash memory. In the embodiment, it is sectional drawing in sectional line VII-VII which shows 1 process of the manufacturing method of flash memory. FIG. 9 is a cross-sectional view showing a step performed after the step shown in FIG. 8 in the same embodiment. FIG. 10 is a cross-sectional view showing a step performed after the step shown in FIG. 9 in the same embodiment. FIG. 11 is a cross-sectional view showing a step performed after the step shown in FIG. 10 in the same embodiment. FIG. 12 is a cross-sectional view showing a step performed after the step shown in FIG. 11 in the same embodiment. FIG. 13 is a cross-sectional view showing a step performed after the step shown in FIG. 12 in the same embodiment. FIG. 14 is a cross-sectional view showing a step performed after the step shown in FIG. 13 in the same embodiment. FIG. 15 is a cross-sectional view showing a step performed after the step shown in FIG. 14 in the same embodiment. FIG. 16 is a cross-sectional view showing a step performed after the step shown in FIG. 15 in the same embodiment. FIG. 17 is a cross-sectional view showing a step performed after the step shown in FIG. 16 in the same embodiment. FIG. 18 is a cross-sectional view showing a step performed after the step shown in FIG. 17 in the same embodiment. FIG. 19 is a cross-sectional view showing a step performed after the step shown in FIG. 18 in the same embodiment. FIG. 20 is a cross-sectional view showing a step performed after the step shown in FIG. 19 in the same embodiment. FIG. 21 is a cross-sectional view showing a step performed after the step shown in FIG. 20 in the same embodiment. FIG. 22 is a cross-sectional view showing a step performed after the step shown in FIG. 21 in the same embodiment. FIG. 24 is a plan view showing a step performed after the step shown in FIGS. 22 and 23 in the same embodiment. FIG. 25 is a cross-sectional view taken along XXV-XXV shown in FIG. 24 in the same embodiment. FIG. 26 is a cross sectional view taken along a cross sectional line XXVI-XXVI shown in FIG. 24 showing a step performed after the step shown in FIGS. 24 and 25 in the same embodiment. FIG. 26 is a cross-sectional view showing a step performed after the step shown in FIG. 25 in the same embodiment. FIG. 27 is a cross-sectional view showing a step performed after the step shown in FIG. 26 in the same embodiment. FIG. 28 is a cross-sectional view showing a step performed after the step shown in FIG. 27 in the same embodiment. FIG. 29 is a cross-sectional view showing a step performed after the step shown in FIG. 28 in the same embodiment. FIG. 30 is a cross-sectional view showing a step performed after the step shown in FIG. 29 in the same embodiment. FIG. 31 is a cross-sectional view showing a step performed after the step shown in FIG. 30 in the same embodiment. FIG. 32 is a cross-sectional view showing a step performed after the step shown in FIG. 31 in the same embodiment. FIG. 33 is a cross-sectional view showing a step performed after the step shown in FIG. 32 in the same embodiment. FIG. 34 is a cross-sectional view showing a step performed after the step shown in FIG. 33 in the same embodiment. In the same embodiment, it is a graph which shows the relationship between the impurity concentration in a BPTEOS film | membrane, and the aspect ratio of the opening which can be embedded. FIG. 36 is a cross-sectional view showing a step performed after the step shown in FIG. 35 in the same embodiment. FIG. 46 is a cross sectional view taken along a cross sectional line VI-VI shown in FIG. 1 of a step performed after the step shown in FIG. 35 in the embodiment. FIG. 5 is a cross-sectional view of the flash memory according to the second embodiment of the present invention corresponding to the cross-sectional line VI-VI shown in FIG. FIG. 7 is a cross-sectional view corresponding to a cross-sectional line VII-VII shown in FIG. 1 in the same embodiment. FIG. 6 is a first cross-sectional view for explaining a capacitance between a floating gate electrode and a control gate electrode in the same embodiment. FIG. 10 is a second cross-sectional view for explaining the capacitance between the floating gate electrode and the control gate electrode in the same embodiment. It is a figure which shows the planar structure of the memory cell area | region of the conventional flash memory. FIG. 44 is a cross-sectional view corresponding to a cross-sectional line XLIV-XLIV shown in FIG. 43, showing one process of a conventional flash memory manufacturing method. FIG. 44 is a cross-sectional view corresponding to a cross-sectional line XLV-XLV shown in FIG. 43, showing a process of a conventional flash memory manufacturing method. FIG. 45 is a cross-sectional view showing a step performed after the step shown in FIG. 44. FIG. 46 is a cross-sectional view showing a step performed after the step shown in FIG. 45. FIG. 47 is a cross-sectional view showing a step performed after the step shown in FIG. 46. FIG. 48 is a cross-sectional view showing a step performed after the step shown in FIG. 47. FIG. 44 is a cross-sectional view taken along a cross-sectional line XLV-XLV shown in FIG. 43 for describing problems in the conventional flash memory. FIG. 44 is a cross-sectional view taken along a cross-sectional line LI-LI shown in FIG. 43 for describing problems of the conventional flash memory.

Embodiment 1
A flash memory according to Embodiment 1 of the present invention will be described. First, the planar structure and equivalent circuit of the memory cell in the flash memory are shown in FIGS. 1 and 2, respectively. As shown in FIG. 1, a plurality of element formation regions S are formed on the surface of the silicon substrate partitioned by the trench isolation oxide film 3. For example, floating gate electrodes 10a to 10d are formed across the element formation region S. Control gate electrodes 12a-12d are formed on the floating gate electrodes 10a-10d, respectively.

  A source region 6a is formed in a region sandwiched between the control gate electrodes 12a and 12b. A drain region 4b is formed in the element formation region S opposite to the source region 6a with the control gate electrode 12b interposed therebetween. Floating gate electrode 10b, control gate electrode 12b, source region 6a and drain region 4b constitute one memory cell.

  The drain region 4b in this memory cell is connected to another memory cell as shown in FIG. 2 by wiring (not shown) running in the row direction (direction substantially orthogonal to the direction in which the control gate electrode extends) through the contact hole 17. It is electrically connected to the drain region.

  On the other hand, the source region 6a is formed by diffusion layer wirings 6 extending in the column direction formed in the silicon substrate 2 in the region sandwiched between the control gate electrodes 12a and 12b, as shown in FIG. And are electrically connected. Therefore, the diffusion layer wiring 6 includes the source region.

  Next, a cross-sectional structure of the memory cell will be described. First, the cross-sectional structure (cross-sectional line III-III) of the element formation region along the direction substantially orthogonal to the direction in which the control gate electrode extends will be described. As shown in FIG. 3, floating gate electrodes 10a, 10b, 10c, and 10d are formed on silicon substrate 2 with tunnel oxide film 8 interposed therebetween.

  Control gate electrodes 12a, 12b, 12c, and 12d are formed on floating gate electrodes 10a to 10d with ONO film 9 interposed. Sidewall insulating films 14a are formed on both side surfaces of the floating gate electrodes 10a to 10d and the control gate electrodes 12a to 12d, respectively.

  A source region 6a is formed on the surface of the silicon substrate 2 sandwiched between the control gate electrode 12a and the control gate electrode 12b. A drain region 4b is formed in the silicon substrate 2 sandwiched between the control gate electrode 12b and the control gate electrode 12c.

  A drain region 4a is formed in a region of the silicon substrate 2 opposite to the source region 6a across the control gate electrode 12a. A source region 6b is formed in the silicon substrate 2 sandwiched between the control gate electrode 12c and the control gate electrode 12d.

  TEOS film 15 is formed on silicon substrate 2 so as to cover control gate electrodes 12a-12d and floating gate electrodes 10a-10d. A BPTEOS film 16 as an interlayer insulating film is formed on the TEOS film 15. Contact holes 17 exposing the surfaces of the drain regions 4a and 4b are formed in the BPTEOS film 16, respectively. Plugs 18 are embedded in the contact holes 17, respectively. A metal wiring 19 electrically connected to the plug 18 is formed on the BPTEOS film 16.

  Next, the cross-sectional structure (cross-sectional line IV-IV) of the drain region formed in each element formation region S along the direction in which the control gate electrode extends will be described. As shown in FIG. 4, the silicon substrate 2 has a groove 2a for forming a trench isolation oxide film. A trench isolation oxide film 3 is formed so as to fill the trench 2a.

  For example, drain regions 4d, 4b, and 4c are formed between adjacent trench isolation oxide films 3, respectively. A BPTEOS film 16 as an interlayer insulating film is formed on trench isolation oxide film 3 with TEOS film 15 interposed. Contact holes 17 are formed in the BPTEOS film 16 to expose the surfaces of the drain regions 4d, 4b, and 4c, respectively.

  Plugs 18 are respectively formed in the contact holes 17. A metal wiring 19 electrically connected to the plug 18 is formed on the BPTEOS film 16.

  Next, a cross-sectional structure (cross-sectional line VV) of the source region formed in the element formation region along the direction in which the control gate electrode extends will be described. As shown in FIG. 5, the silicon substrate 2 has a groove 2a for forming a trench isolation oxide film. Diffusion layer wiring 6 is formed on the surface of silicon substrate 2 including the surface of groove 2a.

  Diffusion layer wiring 6 includes, for example, source region 6a. A BPTEOS film 16 as an interlayer insulating film is formed on the silicon substrate 2 with a TEOS film 15 interposed. Thus, in the region where the source region is formed, the trench isolation oxide film 3 embedded in the trench 2a is removed.

  Next, a cross-sectional structure (cross-sectional line VI-VI) of a region where trench isolation oxide film 3 is formed along a direction substantially orthogonal to the direction in which the control gate electrode extends will be described. This cross section is a cross section at a position relatively close to the element formation region. As shown in FIG. 6, trench isolation oxide film 3 is embedded in a groove formed in silicon substrate 2.

  Floating gate electrodes 10a to 10d are formed on trench isolation oxide film 3 with tunnel oxide film 8 interposed. Control gate electrodes 12a-12d are respectively formed on floating gate electrodes 10a-10d with ONO film 9 interposed.

  An opening 3a that exposes the surface of the silicon substrate 2 (groove 2a) is formed in a region sandwiched between the control gate electrodes 12a and 12b. Similarly, an opening 3a that exposes the surface of the silicon substrate 2 (groove) is formed in a region sandwiched between the control gate electrodes 12c and 12d. A diffusion layer wiring 6 including a source region is formed on the surface of the silicon substrate 2 exposed at the bottom of the opening 3a.

  Sidewall insulating films 14a are formed on the side surfaces of the control gate electrodes 12a to 12d and the floating gate electrodes 10a to 10d, including the side surface of the opening 3a. A TEOS film 15 is formed so as to cover the sidewall insulating film 14a. A BPTEOS film 16 as an interlayer insulating film is formed on the TEOS film 15. A void (void) 20 is formed in the opening 3 a in which the TEOS film 15 and the BPTEOS film 16 are embedded.

  Next, the cross-sectional structure (cross-sectional line VII-VII) of the region where the trench isolation oxide film is formed along the direction orthogonal to the direction in which the control gate electrode extends will be described. This cross section is a cross section at a position relatively distant from the element formation region. As shown in FIG. 7, in this cross section, no floating gate electrode exists under the control gate electrodes 12a to 12d. That is, the control gate electrodes 12a to 12d are located on the trench isolation oxide film 3 with the ONO film 9 interposed therebetween.

  Openings 3a that expose the surface of the silicon substrate 2 (groove) are formed in regions sandwiched between the control gate electrodes 12a and 12c and the control gate electrodes 12b and 12d, respectively. A sidewall insulating film 14a is formed on the side surfaces of the control gate electrodes 12a to 12d including the side surface of the opening 3a.

  A BPTEOS film 16 is formed with a TEOS film 15 interposed so as to fill the opening 3a and cover the control gate electrodes 12a to 12d. As described above, the void (void) 20 is formed in the opening 3a in which the TEOS film 15 and the BPTEOS film 16 are embedded.

  Since the control gate electrodes 12a to 12d formed in the portion along the cross-sectional line are formed so as to fill a relatively narrow portion between adjacent floating gate electrodes, the film thickness is shown in FIG. The film thickness is substantially equal to the total thickness of the floating gate electrode and the control gate electrode shown.

  Opening 3a exposing the surface of silicon substrate 2 (groove 2a) formed in a region sandwiched between control gate electrodes 12a-12d shown in FIGS. 6 and 7 is a diffusion including a source region, as will be described later. The layer wiring 6 is provided to form the silicon substrate 2.

  In the manufacturing process after the opening 3a is filled with the TEOS film 15 and the BPTEOS film 16, a strong stress acts on the silicon substrate 2 located at the bottom of the opening 3a. At this time, since the void (void) 20 is formed in the opening 3a, the stress acting on the silicon substrate 2 can be relaxed. Since the stress acting on the silicon substrate 2 is relaxed, the generation of crystal defects in the silicon substrate 2 can be suppressed, and defects based on crystal defects such as generation of leakage current can be eliminated. As a result, operation reliability is ensured and a flash memory with a high yield can be obtained.

  Next, an example of a method for manufacturing the above-described flash memory will be described by showing cross-sectional structures corresponding to the cross-sectional line VV and the cross-sectional line VII-VII shown in FIG. First, as shown in FIGS. 8 and 9, a predetermined region of the silicon substrate 2 is etched to form a trench 2a having a depth of about 300 to 400 nm for forming a trench isolation oxide film. A trench isolation oxide film 3 is formed by burying a silicon oxide film in the groove 2a.

  Next, as shown in FIGS. 10 and 11, a tunnel oxide film 8 to be a gate insulating film is formed on the exposed surface of the silicon substrate 2. Next, as shown in FIGS. 12 and 13, a polysilicon film 10 having a film thickness of about 100 nm and serving as a floating gate electrode is formed on the silicon substrate 2 by, eg, CVD.

  Next, as shown in FIGS. 14 and 15, a predetermined photoresist pattern (not shown) is formed on the polysilicon film 10, and a floating gate electrode is formed on the polysilicon film 10 using the photoresist pattern as a mask. Etching is performed. At the stage where this patterning has been performed, the polysilicon film 10 to be a floating gate electrode is in a state of being formed in a stripe shape in a direction substantially perpendicular to the direction in which the control gate electrode shown in FIG. 1 extends.

  Next, as shown in FIGS. 16 and 17, an ONO film 9 made of a laminated film of a silicon oxide film and a silicon nitride film is formed on the polysilicon film 10 to be a floating gate electrode by, for example, a CVD method. Thereafter, in the peripheral circuit region (not shown) other than the memory cell, the above-described ONO film 9 and the polysilicon film 10 to be the floating gate electrode are removed. Further, a gate oxide film for forming a transistor is formed in the peripheral circuit region.

  Next, as shown in FIGS. 18 and 19, a polycide film 12 serving as a control gate electrode having a polycide structure made of, for example, a tungsten silicide film and a polysilicon film is formed on the ONO film 9. The polycide film 12 has a thickness of about 150 to 200 nm.

  Next, as shown in FIG. 20 and FIG. 21, a predetermined photoresist pattern (not shown) is formed on the polycide film 12, and the polycide film 12 is etched using the photoresist pattern as a mask to control. Gate electrodes 12a to 12d are formed. Next, a predetermined photoresist pattern (not shown) is formed, and the ONO film 9 and the polysilicon film 10 serving as the floating gate electrode are etched using the photoresist pattern as a mask to form a floating gate electrode. .

  At this stage, the floating gate electrodes 10a to 10d and the like shown in FIG. 1 are formed, and in the sectional line V-V, the ONO film and the polysilicon film that becomes the floating gate electrode are removed as shown in FIG. Become. Further, at the sectional line VII-VII, as shown in FIG. 23, the control gate electrodes 12a to 12d are formed on the trench isolation oxide film 3 with the ONO film 9 interposed.

  Next, as shown in FIGS. 24 and 25, a predetermined photoresist pattern 13 is formed on the silicon substrate 2 on which the control gate electrodes 12a to 12d are formed along the direction in which the control gate electrodes 12a to 12d extend. . At this time, for example, a region sandwiched between the control gate electrodes 12 b and 12 c is covered with the photoresist pattern 13. A region sandwiched between the control gate electrodes 12 a and 12 b is not covered with the photoresist pattern 13.

  Next, as shown in FIGS. 26 and 27, the trench isolation oxide film 3 is etched using the photoresist pattern 13 and the control gate electrodes 12a to 12d as a mask to expose the surface of the trench 2a.

  Next, as shown in FIGS. 28 and 29, ions of a predetermined conductivity type are implanted into the surface of the silicon substrate 2 including the exposed surface of the groove 2a by an ion implantation method so that the diffusion layer wiring 6 including the source region is formed. Form. In addition, a drain region is formed in each element formation region opposite to the source region across the control gate electrode.

  Next, as shown in FIGS. 30 and 31, a TEOS film (Tetra Ethyl Ortho Silicate glass) 14 is formed on the silicon substrate 2 by, for example, a CVD method. Next, as shown in FIGS. 32 and 33, anisotropic etching is performed on the entire surface of the TEOS film 14, so that the sidewall insulating film 14a is formed on the side surfaces of the control gate electrodes 12a to 12d including the side surface of the opening 3a. Form. Next, as shown in FIGS. 34 and 35, a TEOS film 15 is further formed on the silicon substrate 2 by, for example, the CVD method so as to cover the control gate electrodes 12a to 12d.

  Next, a BPTEOS film to be an interlayer insulating film is formed on the TEOS film 15. The BPTEOS film is a TEOS film containing boron (B) and phosphorus (P) as impurities. In particular, when an opening is filled using a BPTEOS film, as shown in FIG. 36, it is known that an opening having a higher aspect ratio can be filled as the impurity concentration is higher. In other words, when the impurity concentration is relatively low, it is impossible to fill an opening having a large aspect ratio.

  In this flash memory, by utilizing the relationship between the impurity concentration in the BPTEOS film and the aspect ratio of the embeddable opening, a void is positively formed in the opening 3a formed in the trench isolation oxide film 3. Form.

  Here, the depth of the opening 3a is a depth obtained by adding the thickness of the floating gate electrode and the control gate electrode to the depth of the groove 2a for forming the trench isolation oxide film 3. As described above, the depth of the groove 2a is about 300 to 400 nm, and the total thickness of the floating gate electrode and the control gate electrode is about 250 to 300 nm. Therefore, the depth of the opening 3a is about 550 to 700 nm. This opening 3a is the deepest opening which is about 2 to 3 times deeper than other openings or step portions formed on the silicon substrate 2.

  Therefore, as shown in FIGS. 37 and 38, a BPTEOS film 16 having relatively low concentrations of boron and phosphorus added as impurities is formed on the TEOS film 15 in order to deteriorate the burying characteristics in the opening 3a. Thus, a void (void) 20 is formed inside the opening 3a. Thereafter, the main part of the flash memory is completed by flattening the BPTEOS film.

  In this flash memory, the void 20 is formed in the opening 3a, so that in the step after the formation of the BPTEOS film 16, the silicon substrate 2 located near the bottom of the opening 3a indicated by the dotted line frame A is formed. An escape path for the acting stress is obtained and the stress is relieved. As a result, the occurrence of crystal defects in the silicon substrate is suppressed, and inconveniences such as the occurrence of leakage current due to the occurrence of crystal defects are eliminated, and a flash memory capable of performing a desired operation is obtained. It is done.

  In addition, the yield of flash memory is improved by suppressing crystal defects that occur during the manufacturing process after the formation of the BPTEOS film. Further, in the completed flash memory, for example, stress due to heat can be relaxed, and the operation reliability of the flash memory is improved.

  In addition, by appropriately selecting the boron concentration and the phosphorus concentration in the BPTEOS film, the void 20 is formed only in the deepest opening 3a, and voids are formed in other openings and step portions shallower than the opening 3a. The BPTEOS film 16 can be completely filled without forming it.

Embodiment 2
A flash memory according to Embodiment 2 of the present invention will be described. In the flash memory according to the first embodiment, as shown in FIGS. 37 and 38, the upper end of the void 20 formed in the opening 3a is lower than the lower ends (lower surfaces) of the floating gate electrodes 10a to 10d. Was located at. That is, the void 20 is formed at a position sandwiched between the trench isolation oxide films 3.

  In the flash memory according to the present embodiment, as shown in FIGS. 39 and 40, from the position sandwiched by trench isolation oxide film 3 to the position sandwiched by floating gate electrodes 10a to 10d and control gate electrodes 12a to 12d. A void 21 extending up to is formed. Since other configurations are the same as those of the flash memory described in the first embodiment, the same members are denoted by the same reference numerals, and the description thereof is omitted.

  Next, a method for manufacturing the above-described flash memory will be described. In order to form such a void 21, the void 21 is formed in the opening 3a by forming a BPTEOS film having poorer embedding characteristics after the step shown in FIG. 35 described in the first embodiment. The That is, by forming a BPTEOS film having a lower boron concentration and phosphorus concentration, the embedding characteristic in the opening 3a is deteriorated, and a larger void 21 is formed.

  According to this flash memory, first, as described in the first embodiment, the stress concentrated on the portion indicated by the dotted frame A can be relaxed by the void 21, and crystal defects are generated in the silicon substrate 2. Can be suppressed. In this flash memory, in addition to the effect of relaxing the stress acting on the silicon substrate 2, the effect of reducing the capacitance between the gate wirings can be obtained.

This will be described. First, as shown in FIG. 41, the capacitance Cs between the floating gate electrodes 10a and 10b and the control gate electrodes 12a and 12b includes three capacitances C1 and C2 based on the BPTEOS film 16 and capacitance C3 based on the void 21. It becomes the capacity which connected in series. Here, C1 = ε OX · a / s, C2 = ε GAP · b / s, and C3 = ε OX · c / s. ε gap is the dielectric constant of the void, ε GAP is the dielectric constant of the BPTEOS film, a and c are the film thickness of the BPTEOS film, b is the length of the void, and s is the cross-sectional area.

On the other hand, in the conventional flash memory or the flash memory according to the first embodiment, as shown in FIG. 42, the capacitance Co between the floating gate electrodes 10a and 10b and the control gate electrodes 12a and 12b is Co = ε OX · f / s. It becomes. Here, f = a + b + c. Since the dielectric constant ε OX of the BPTEOS film is sufficiently larger than the dielectric constant ε gap of the void, the capacitance Cs is smaller than the capacitance Co. As a result, the capacitances of the floating gate electrodes 10a and 10b and the control gate electrodes 12a and 12b positioned with the source region interposed therebetween are reduced particularly at the position where the void 21 is interposed.

  By the way, in the flash memory, the control gate electrode is charged with the respective operating voltages at the time of reading and writing operations. The charging time is proportional to the product RC of the capacitance C, which is the sum of the gate capacitance and the parasitic capacitance, and the wiring resistance R of the gate, and the shorter the charging time, the faster the operation is possible.

  Therefore, in the present flash memory, the formation of the void 21 described above reduces the parasitic capacitance Cs between the control gate electrodes located across the source region, thereby reducing the capacitance C without increasing the gate wiring resistance R. Can be reduced. As a result, the dielectric time during reading and writing operations can be reduced, and high-speed performance such as high-speed random reading and high-speed writing can be realized.

  In the flash memory in each of the above embodiments, the BPTEOS film has been described as an example of the interlayer insulating film filling the opening. However, a void is formed only in the opening 3a, and other openings and steps are formed. The portion is not limited to the BPTEOS film as long as it is a film that can be completely filled without forming voids, and may be an insulating film made of another material.

  In each of the above embodiments, the flash memory having the self-line source structure has been described as an example. However, the present invention is also applicable to a nonvolatile semiconductor memory device such as an EEPROM using the self-line source structure. Can do.

  The embodiment disclosed this time is an example, and the present invention is not limited to this. The present invention is defined by the terms of the claims, rather than the scope described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  2 silicon substrate, 2a groove, 3 trench isolation oxide film, 3a opening, 4a, 4b drain region, 6 diffusion layer wiring, 6a, 6b source region, 8 tunnel oxide film, 9 ONO film, 10 polysilicon film, 10a- 10d floating gate electrode, 12 polycide film, 12a-12d control gate electrode, 13 photoresist pattern, 14 TEOS film, 14a sidewall insulating film, 15 TEOS film, 16 BPTEOS film, 17 contact hole, 18 plug, 19 metal wiring, 20, 21 voids.

Claims (7)

  1. A semiconductor substrate having a main surface;
    A groove formed in the main surface of the semiconductor substrate;
    A first insulating film embedded in the trench;
    Two conductive layers formed above the first insulating film at a distance and including a first electrode portion serving as a floating gate and a second electrode portion serving as a control gate;
    A second insulating film formed to cover the two conductive layers;
    A semiconductor device comprising: a gap formed between the two conductive layers buried by the second insulating film.
  2.   The semiconductor device according to claim 1, wherein the gap is formed at a position sandwiched between the two conductive layers including the first electrode portion that is a floating gate and the second electrode portion that is a control gate.
  3. An element forming region formed on the semiconductor substrate, traversed by the two conductive layers and separated by the first insulating film;
    One impurity region of a predetermined conductivity type and the other conductive layer formed in the element formation region on the side where the other conductive layer is located with one conductive layer of the two conductive layers interposed therebetween 3. The semiconductor device according to claim 1, further comprising an impurity region on the other side of a predetermined conductivity type formed in the element formation region opposite to the side.
  4. A conductive region formed on a surface of the semiconductor substrate located in a region sandwiched between the two conductive layers;
    The semiconductor device according to claim 3, wherein the conductive region includes the one-side impurity region.
  5. The one-side impurity region includes a source region;
    The semiconductor device according to claim 3, wherein the other-side impurity region includes a drain region.
  6. A semiconductor substrate;
    A groove formed in the semiconductor substrate;
    An element isolation insulating film embedded in the trench;
    An element formation region formed on the semiconductor substrate and partitioned by the element isolation insulating film;
    A first gate line formed across the element isolation insulating film and the element formation region and including a floating gate electrode and a control gate electrode;
    A second gate wiring formed to be spaced apart from the first gate wiring so as to cross the element isolation insulating film and the element formation region, and including a floating gate electrode and a control gate electrode;
    A source region formed in the element formation region sandwiched between the first gate wiring and the second gate wiring;
    A drain region formed in the element formation region opposite to the source region across the first gate wiring;
    An interlayer insulating film formed on the semiconductor substrate so as to cover the first gate wiring and the second gate wiring;
    A semiconductor device comprising: the first gate wiring buried in the interlayer insulating film; and a gap formed between the second gate wiring.
  7.   The semiconductor device according to claim 6, wherein the gap is formed at a position sandwiched between the first gate wiring and the second gate wiring.
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Cited By (4)

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Publication number Priority date Publication date Assignee Title
JP2013225652A (en) * 2012-04-20 2013-10-31 Sk Hynix Inc Semiconductor element and method of manufacturing the same
JP2014236014A (en) * 2013-05-30 2014-12-15 ローム株式会社 Semiconductor device, and method of manufacturing the same
JP2015170763A (en) * 2014-03-07 2015-09-28 ルネサスエレクトロニクス株式会社 Semiconductor device manufacturing method
US10622443B2 (en) 2013-05-30 2020-04-14 Rohm Co., Ltd. Semiconductor device with different material layers in element separation portion trench and method for manufacturing semiconductor device

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JPH07326670A (en) * 1994-05-31 1995-12-12 Texas Instr Inc <Ti> Semiconductor integrated circuit device
JPH11251428A (en) * 1997-12-31 1999-09-17 Lg Semicon Co Ltd Wiring structure and forming method of semiconductor device
JPH11265994A (en) * 1998-03-17 1999-09-28 Fujitsu Ltd Manufacture of semiconductor device
JP2000100976A (en) * 1998-09-21 2000-04-07 Matsushita Electronics Industry Corp Semiconductor memory device and manufacture thereof

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Publication number Priority date Publication date Assignee Title
JPH07326670A (en) * 1994-05-31 1995-12-12 Texas Instr Inc <Ti> Semiconductor integrated circuit device
JPH11251428A (en) * 1997-12-31 1999-09-17 Lg Semicon Co Ltd Wiring structure and forming method of semiconductor device
JPH11265994A (en) * 1998-03-17 1999-09-28 Fujitsu Ltd Manufacture of semiconductor device
JP2000100976A (en) * 1998-09-21 2000-04-07 Matsushita Electronics Industry Corp Semiconductor memory device and manufacture thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013225652A (en) * 2012-04-20 2013-10-31 Sk Hynix Inc Semiconductor element and method of manufacturing the same
JP2014236014A (en) * 2013-05-30 2014-12-15 ローム株式会社 Semiconductor device, and method of manufacturing the same
US10622443B2 (en) 2013-05-30 2020-04-14 Rohm Co., Ltd. Semiconductor device with different material layers in element separation portion trench and method for manufacturing semiconductor device
JP2015170763A (en) * 2014-03-07 2015-09-28 ルネサスエレクトロニクス株式会社 Semiconductor device manufacturing method

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