JP2000100976A - Semiconductor memory device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory array device and a manufacturing method thereof, where the memory array device is capable of carrying out a read-out operation stably by a method wherein a means that is independent of the state of an adjacent EEPROM cell when the memory array device is kept in a read-out operation is provided. SOLUTION: A memory cell is equipped with a source region 3 and a drain region 4 provided inside a certain conductivity-type semiconductor substrate 1, a gate insulating film 5 formed on the prescribed region of the semiconductor substrate 1, a floating gate electrode 6 provided on the gate insulating film 5, and a control gate electrode 8 provided in the floating gate electrode 6 through the intermediary of an interlayer insulating film 7, and a semiconductor memory array is composed of two or more of the memory cells, where an insulating film 18 having a dielectric constant lower than that of a silicon oxide film is provided between the floating gate electrodes 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a floating gate type semiconductor memory array device and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, as an electrically writable and erasable nonvolatile memory, an EE having a floating gate structure has been known.
PROM (Electrically Erasable)
e and Programmable Read On
ly Memory) is well known.

FIGS. 21 and 22 are a plan view and a sectional view, respectively, of a conventional semiconductor memory array device composed of EEPROM cells having a typical stack type floating gate structure. This conventional example will be described using a semiconductor memory array device composed of four EEPROM cells. FIG. 22A is a sectional view taken along line AA ′ of FIG.
FIG. 22B is a sectional view taken along the line BB ′ of FIG. 21 and 22, 1 is a semiconductor substrate, 2 is an element isolation insulating film, 3 is a source region, 4 is a drain region, 5 is a gate insulating film that can be a tunneling medium, 6 is a floating gate electrode, 7 is an interlayer insulating film. Reference numeral 8 denotes a control gate electrode, and reference numeral 9 denotes an insulating film made of a silicon oxide film covered to protect and insulate the memory cell.

When writing in each of the floating gate type EEPROM cells constituting the semiconductor memory array device as shown in FIGS. 21 and 22, a high voltage is applied to the drain region 4 and a high voltage is applied to the control gate electrode 8 at the same time. A voltage is applied to raise the potential of the floating gate electrode 6 by capacitive coupling, and hot electrons generated in the channel region near the drain region 4 are passed through the gate insulating film 5 from the channel region side, and the floating gate electrode 6 And accumulates electrons in the floating gate electrode 6. In recent years, a method of injecting electrons from the channel region on the semiconductor substrate 1 side to the floating gate electrode 6 using the tunneling phenomenon has been proposed.

On the other hand, when erasing, a high voltage is applied to the drain region 4 and the floating gate electrode 6 is formed by a tunneling phenomenon through the thin gate insulating film 5 at the overlapping portion between the floating gate electrode 6 and the drain region 4. This is performed by extracting the electrons accumulated in 6 to the drain region 4 side. In recent years, a method of extracting electrons from the floating gate electrode 6 to the channel region on the semiconductor substrate 1 side has also been proposed.

The read method is performed between the source region 3 and the drain region 4 and the control gate electrode 8.
An operating voltage is applied to the source region 3 and the drain region 4.
This is performed by detecting the level of the current flowing between the two. Further, in recent years, instead of erasing the electrons accumulated in the floating gate electrode 6 by emitting electrons toward the substrate 1 as described above, the erasing is performed by using an independent erasing gate electrode as shown in FIGS. EEPROM cells having a floating gate structure (see, for example,
No. -340767) has been proposed. 24A is a sectional view taken along the line AA ′ of FIG. 23, and FIG.
It is B 'sectional drawing.

An EEPROM using the erase gate electrode
In the cell structure, a tunneling insulating film 17 is formed between the erase gate electrode 16 and the floating gate electrode 6, and an erase voltage is applied to the erase gate electrode 16 to move electrons from the floating gate electrode 6 to the erase gate electrode 1.
Then, erasing is performed by tunneling to. In addition, 12 to 15 are silicon oxide films.

In recent years, with the increasing integration of semiconductor integrated circuits,
EEPROM of floating gate structure as described above
The demand for miniaturization is also increasing in a semiconductor memory array device composed of cells, and recently, a demand for a semiconductor memory array device having a typical size of 0.5 μm (half micron) or less is increasing. Accordingly, the size of each of the control gate electrode 8 and the floating gate electrode 6 shown in FIGS. 21, 22, 23, and 24 is also reduced, and at the same time, the interval 10 between the adjacent floating gate electrodes 6, The spacing 11 between the electrodes 8 has also been miniaturized and has become smaller than half a micron.

[0009]

However, in a semiconductor memory array device having a floating gate structure having a size of half a micron or less, a space 10 between adjacent floating gate electrodes 6 and a space 11 between adjacent control gate electrodes 8 are set. Is less than half a micron, there occurs a problem that adjacent EEPROM cells cause capacitive coupling via the silicon oxide film 9 and the read margin is reduced.

That is, considering mainly the read operation of a selected EEPROM cell, the state of the EEPROM cell adjacent thereto (whether the state where electrons are stored,
Or the state in which electrons have been emitted), the charge of the selected EEPROM cell will be apparently different. Therefore, the read margin is equal to that of the adjacent EEPROM.
It depends on the amount of charge stored in the M cell, and the read margin is reduced.

According to the study of the present inventor, when the interval 10 between the adjacent floating gate electrodes 6 and the interval 11 between the adjacent control gate electrodes 8 become 0.3 μm or less, the read margin sharply decreases. In particular, it has been found that it becomes difficult to perform a multi-level operation that requires storing two or more bits of state. 23 and 24.
In an EEPROM cell having a floating gate structure provided with an erase gate electrode 16 as shown in FIG. 3, a tunneling insulating film 17 is formed between the erase gate electrode 16 and the floating gate electrode 6 so that the space between adjacent floating gate electrodes 6 is reduced. 10 has a structure that is narrower than the interval 11 between the adjacent control gate electrodes 8, and is liable to be affected by the above-described adjacent EEPROM cell, and is smaller than the EEPROM cell of the floating gate structure 6 without the erase gate electrode 16. In addition, there is a problem that miniaturization is difficult.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and is directed to a semiconductor memory array device having a floating gate structure having a size of half a micron or less.
It is an object of the present invention to provide a semiconductor memory array device which realizes a stable read operation by taking measures not depending on the state of an adjacent EEPROM cell at the time of a read operation, and a method of manufacturing the same.

[0013]

According to a first aspect of the present invention, there is provided a semiconductor memory array device having a source region and a drain region in a semiconductor substrate of one conductivity type, and a first insulating film in a predetermined region on the semiconductor substrate. A semiconductor having at least two memory cells having a floating gate electrode on the first insulating film and having at least a control gate electrode on the floating gate electrode via a second insulating film A memory array device, wherein an insulating film having a dielectric constant lower than that of a silicon oxide film is provided between each floating gate electrode of the semiconductor memory array device.

According to the semiconductor memory array device of the first aspect, since the insulating film having a dielectric constant lower than that of the silicon oxide film is provided between the adjacent floating gate electrodes, the space between the adjacent floating gate electrodes and between the adjacent control electrodes is reduced. Even if the capacitive coupling is weakened and the interval becomes, for example, submicron or less, it is possible to suppress the influence of the state of the charge of the adjacent EEPROM cell at the time of reading, thereby achieving high integration of a floating gate structure semiconductor memory array device. It can greatly contribute to high performance.

According to a second aspect of the present invention, there is provided a semiconductor memory array device having a source region and a drain region in a semiconductor substrate of one conductivity type and a first insulating film in a predetermined region on the semiconductor substrate. A semiconductor memory array device comprising at least two memory cells having a floating gate electrode on one insulating film, and having at least a control gate electrode on the floating gate electrode via a second insulating film. An insulating film having a dielectric constant lower than that of a silicon oxide film is provided between each control gate electrode of the semiconductor memory array device.

According to the semiconductor memory array device of the second aspect, the same effect as that of the first aspect is obtained. 4. The semiconductor memory array device according to claim 3, wherein a source region and a drain region are provided in a semiconductor substrate of one conductivity type, and a first insulating film is provided in a predetermined region on the semiconductor substrate. A semiconductor memory array device comprising at least two memory cells having a floating gate electrode on a film and having at least a control gate electrode on the floating gate electrode with a second insulating film interposed therebetween, comprising: An insulating film having a dielectric constant lower than that of a silicon oxide film is provided between each floating gate electrode and between each control gate electrode of the array device.

According to the semiconductor memory array device of the third aspect, the same effect as that of the first aspect is obtained. 5. The semiconductor memory array device according to claim 4, further comprising: a source region and a drain region in a semiconductor substrate of one conductivity type; and a first insulating film in a predetermined region on the semiconductor substrate. A semiconductor memory array device comprising at least two memory cells having a floating gate electrode on a film and having at least a control gate electrode on the floating gate electrode with a second insulating film interposed therebetween, A cavity is provided between each floating gate electrode of the memory array device.

According to the semiconductor memory array device of the fourth aspect, the same effect as that of the first aspect is obtained. 6. The semiconductor memory array device according to claim 5, further comprising: a source region and a drain region in a semiconductor substrate of one conductivity type; a first insulating film in a predetermined region on the semiconductor substrate; A semiconductor memory array device comprising at least two memory cells having a floating gate electrode on a film and having at least a control gate electrode on the floating gate electrode with a second insulating film interposed therebetween, comprising: A cavity is provided between each control gate electrode of the array device.

According to the semiconductor memory array device of the fifth aspect, the same effect as that of the first aspect is obtained. 7. The semiconductor memory array device according to claim 6, further comprising: a source region and a drain region in a semiconductor substrate of one conductivity type; and a first insulating film in a predetermined region on the semiconductor substrate. A semiconductor memory array device comprising at least two memory cells having a floating gate electrode on a film and having at least a control gate electrode on the floating gate electrode with a second insulating film interposed therebetween, comprising: A cavity is provided between each floating gate electrode and between each control gate electrode of the array device.

According to the semiconductor memory array device of the sixth aspect, the same effect as that of the first aspect is obtained. 8. The semiconductor memory array device according to claim 7, further comprising: a source region and a drain region in a semiconductor substrate of one conductivity type; and a first insulating film in a predetermined region on the semiconductor substrate. A floating gate electrode on the film, a control gate electrode on the floating gate electrode via a second insulating film, and a contact with the floating gate electrode via an insulating film that can be a tunneling medium; A semiconductor memory array device having at least three or more memory cells having at least three erase gate electrodes in contact with each other with a third insulating film interposed therebetween, wherein oxidation is performed between floating gate electrodes of the semiconductor memory array device that do not have an erase gate electrode. An insulating film having a dielectric constant lower than that of the silicon film is provided.

According to the semiconductor memory array device of the seventh aspect, the same effect as that of the first aspect is obtained. 9. The semiconductor memory array device according to claim 8, further comprising: a source region and a drain region in a semiconductor substrate of one conductivity type; and a first insulating film in a predetermined region on the semiconductor substrate. A floating gate electrode on the film, a control gate electrode on the floating gate electrode via a second insulating film, and a contact with the floating gate electrode via an insulating film that can be a tunneling medium; 3. A semiconductor memory array device provided with at least three or more memory cells having at least three erase gate electrodes in contact with each other through an insulating film, wherein a cavity is provided between floating gate electrodes of the semiconductor memory array device that do not have an erase gate electrode. It is characterized by having.

According to the semiconductor memory array device of the eighth aspect, the same effect as that of the first aspect is obtained. 10. The method of manufacturing a semiconductor memory array device according to claim 9, wherein a source region and a drain region of a conductivity type opposite to the semiconductor substrate are formed in a semiconductor substrate of one conductivity type, and an element isolation insulating film is formed on the semiconductor substrate. Forming an active region separated by, and forming a gate insulating film on the active region,
Forming a first conductive film, an interlayer insulating film, and a second conductive film on the surfaces of the gate insulating film and the element isolation insulating film in sequence, and forming predetermined portions of the interlayer insulating film and the second conductive film; To form a control gate electrode by etching and removing the first conductive film using the control gate electrode as a mask to form a floating gate electrode. A step of forming an insulating film having a dielectric constant lower than that of the silicon oxide film in a portion formed when the floating gate electrode is formed and where the first conductive film is removed by etching.

According to the method of manufacturing a semiconductor memory array device of the ninth aspect, the same effect as that of the first aspect can be obtained. 11. The method for manufacturing a semiconductor memory array device according to claim 10, wherein a source region and a drain region of a conductivity type opposite to the semiconductor substrate are formed in a semiconductor substrate of one conductivity type, and an element isolation insulating film is formed on the semiconductor substrate. Forming an active region isolated by the above, forming a gate insulating film on the active region, forming a first conductive film, an interlayer insulating film, and a second conductive film on the surfaces of the gate insulating film and the element isolation insulating film. Forming a control gate electrode by etching and removing predetermined portions of the interlayer insulating film and the second conductive film; and forming the first conductive film by using the control gate electrode as a mask. A method of manufacturing a semiconductor memory array device comprising at least a step of forming a floating gate electrode by removing a film by etching, wherein a control gate electrode is formed. The formed and a portion of the second conductive film is removed by etching during that and is characterized in that it comprises a step of forming an insulating film of less than a silicon oxide film dielectric constant.

According to the method of manufacturing a semiconductor memory array device of the tenth aspect, the same effect as that of the first aspect is obtained. A method for manufacturing a semiconductor memory array device according to claim 11,
Forming a source region and a drain region of a conductivity type opposite to the semiconductor substrate in a semiconductor substrate of one conductivity type; forming an active region separated by an element isolation insulating film on the semiconductor substrate; Forming a first conductive film, an interlayer insulating film, and a second conductive film on the surfaces of the gate insulating film and the element isolation insulating film sequentially; And forming a control gate electrode by etching and removing a predetermined portion of the second conductive film; and forming a floating gate electrode by etching and removing the first conductive film using the control gate electrode as a mask. A method of manufacturing a semiconductor memory array device, comprising: forming a floating gate electrode and removing a first conductive film by etching; And forming an insulating film having a dielectric constant lower than that of the silicon oxide film in a portion formed when forming the control gate electrode and removing the second conductive film by etching. .

According to the method of manufacturing a semiconductor memory array device of the eleventh aspect, the same effect as that of the first aspect can be obtained. The method of manufacturing a semiconductor memory array device according to claim 12 is:
Forming a source region and a drain region of a conductivity type opposite to the semiconductor substrate in a semiconductor substrate of one conductivity type;
Forming an active region separated by a device isolation insulating film on a semiconductor substrate, forming a gate insulating film on the active region, and forming a first conductive film on a surface of the gate insulating film and the device isolation insulating film Forming a control gate electrode by etching and removing predetermined portions of the interlayer insulating film and the second conductive film; forming a control gate electrode by etching and removing predetermined portions of the interlayer insulating film and the second conductive film; Forming a floating gate electrode by etching and removing the first conductive film using the mask as a mask, wherein the first conductive film is formed when the floating gate electrode is formed and the first conductive film is formed. A method for manufacturing a semiconductor memory array device, comprising a step of forming a cavity in a portion where a film is removed by etching.

According to the method of manufacturing a semiconductor memory array device of the twelfth aspect, the same effect as that of the first aspect can be obtained. The method for manufacturing a semiconductor memory array device according to claim 13 is:
Forming a source region and a drain region of a conductivity type opposite to the semiconductor substrate in a semiconductor substrate of one conductivity type;
Forming an active region separated by a device isolation insulating film on a semiconductor substrate, forming a gate insulating film on the active region, and forming a first conductive film on a surface of the gate insulating film and the device isolation insulating film Forming a control gate electrode by etching and removing predetermined portions of the interlayer insulating film and the second conductive film; forming a control gate electrode by etching and removing predetermined portions of the interlayer insulating film and the second conductive film; Forming a floating gate electrode by etching and removing the first conductive film using the mask as a mask, wherein the second conductive film is formed when the control gate electrode is formed and the second conductive film is formed. The method includes a step of forming a cavity in a portion where the film is removed by etching.

According to the method of manufacturing a semiconductor memory array device according to the thirteenth aspect, the same effect as that of the first aspect can be obtained. A method for manufacturing a semiconductor memory array device according to claim 14,
Forming a source region and a drain region of a conductivity type opposite to the semiconductor substrate in a semiconductor substrate of one conductivity type;
Forming an active region separated by a device isolation insulating film on a semiconductor substrate, forming a gate insulating film on the active region, and forming a first conductive film on a surface of the gate insulating film and the device isolation insulating film Forming a control gate electrode by etching and removing predetermined portions of the interlayer insulating film and the second conductive film; forming a control gate electrode by etching and removing predetermined portions of the interlayer insulating film and the second conductive film; Forming a floating gate electrode by etching and removing the first conductive film using the mask as a mask, wherein the first conductive film is formed when the floating gate electrode is formed and the first conductive film is formed. A portion where the film is removed by etching and a portion where the control gate electrode is formed and the second conductive film is removed by etching, It is characterized in that it comprises the step of forming a sinus.

According to the method of manufacturing a semiconductor memory array device of the fourteenth aspect, the same effect as that of the first aspect can be obtained. A method for manufacturing a semiconductor memory array device according to claim 15,
Forming a source region and a drain region of a conductivity type opposite to the semiconductor substrate in a semiconductor substrate of one conductivity type;
Forming an active region separated by a device isolation insulating film on a semiconductor substrate, forming a gate insulating film on the active region, and forming a first conductive film on a surface of the gate insulating film and the device isolation insulating film Forming a first insulating film, a second conductive film, and a second insulating film by sequentially laminating the first insulating film, the second conductive film, and a predetermined portion of the second insulating film. Remove the insulating film on the control gate electrode by etching,
Forming a control gate electrode and an interlayer insulating film, forming an insulating film on the control gate electrode, a sidewall insulating film on the side wall surface of the control gate electrode and the interlayer insulating film, and using the sidewall insulating film as a mask. Forming a floating gate electrode by etching and removing the first conductive film; forming a tunneling insulating film that can serve as a tunneling medium on a side wall surface of the floating gate electrode;
A method of manufacturing a semiconductor memory array, comprising at least a step of forming an erase gate electrode made of a third conductive film so as to cover an insulating film on a sidewall insulating film and a control gate electrode. The method is characterized by including a step of forming an insulating film having a lower dielectric constant than the silicon oxide film in a portion formed when the first conductive film is removed by etching.

According to the method of manufacturing a semiconductor memory array device according to the fifteenth aspect, the same effect as that of the first aspect can be obtained. The method of manufacturing a semiconductor memory array device according to claim 16,
Forming a source region and a drain region of a conductivity type opposite to the semiconductor substrate in a semiconductor substrate of one conductivity type;
Forming an active region separated by a device isolation insulating film on a semiconductor substrate, forming a gate insulating film on the active region, and forming a first conductive film on a surface of the gate insulating film and the device isolation insulating film Forming a first insulating film, a second conductive film, and a second insulating film by sequentially laminating the first insulating film, the second conductive film, and a predetermined portion of the second insulating film. Remove the insulating film on the control gate electrode by etching,
Forming a control gate electrode and an interlayer insulating film, forming an insulating film on the control gate electrode, a sidewall insulating film on the side wall surface of the control gate electrode and the interlayer insulating film, and using the sidewall insulating film as a mask. Forming a floating gate electrode by etching and removing the first conductive film; forming a tunneling insulating film that can serve as a tunneling medium on a side wall surface of the floating gate electrode;
A method of manufacturing a semiconductor memory array, comprising at least a step of forming an erase gate electrode made of a third conductive film so as to cover a surface of an insulating film on a sidewall insulating film and a control gate electrode, wherein the floating gate electrode is A method for manufacturing a semiconductor memory array device, comprising a step of forming a cavity in a portion formed at the time of forming and removing a first conductive film by etching.

According to the method of manufacturing a semiconductor memory array device of the sixteenth aspect, the same effect as that of the first aspect can be obtained.

[0031]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIGS. 1 and 2 show a first embodiment of the present invention.
Of Floating Gate Structure According to Embodiment
3A and 3B are a plan view and a cross-sectional view of a semiconductor memory array device including ROM cells. 2A is a sectional view taken along the line AA ′ of FIG. 1, and FIG. 2B is a sectional view taken along the line BB ′ of FIG.

As shown in FIG. 2, a source region 3, a drain region 4 composed of an N-type diffusion layer and an element isolation insulating film 2 composed of a silicon oxide film are formed on the surface of a semiconductor substrate 1 using a P-type silicon substrate. Are formed. Source area 3
A gate insulating film 5 made of a thin silicon oxide film and a floating gate electrode 6 made of a polysilicon film are formed on a channel region sandwiched between the drain region 4 and the drain region 4. On the floating gate electrode 6, an interlayer insulating film 7 composed of a silicon oxide film-silicon nitride film-silicon oxide film of about 30 nm is formed, and a control gate electrode 8 composed of a polysilicon film of about 400 nm is formed thereon. Have been. Further, a fluorine-doped polyimide film (a relative dielectric constant of about 2.7), which is an insulating film 18 having a low dielectric constant, is formed in a gap having a spacing of 10 between the floating gate electrodes 6 and a gap having a spacing of 11 between the control gate electrodes 8. ing.

As described above, according to the semiconductor memory array device of the present embodiment, the space 10 between the adjacent floating gate electrodes 6 and the space 11 between the adjacent control gate electrodes 8 correspond to the low dielectric constant insulating film 18. , The capacitive coupling between the adjacent floating gate electrodes 6 and between the adjacent control gate electrodes 8 is weakened, and the influence of the state of the charge of the adjacent EEPROM cell at the time of reading even if the miniaturization is further promoted. Can be suppressed. Next, a method of manufacturing the semiconductor memory array device according to the present embodiment will be described with reference to FIGS. FIG. 3A is a cross-sectional view at the AA ′ cutting position in FIG. 1, and FIG. 3B is a cross-sectional view at the BB ′ cutting position in FIG. 4 (a) and 4 (b), and FIGS. 5 (a) and 5 (b).

First, as shown in FIGS. 3A and 3B, a source region 3 composed of an N-type diffusion layer is formed on a semiconductor substrate 1 of a P-type silicon substrate by a known selective diffusion technique.
The drain region 4 is formed. Thereafter, an element isolation insulating film 2 of a silicon oxide film of about 500 nm for separating an active region is formed by a known selective oxidation method, and then a gate insulating film 5 of a silicon oxide film of about 10 nm is formed on the active region by a thermal oxidation method. Is formed. A polysilicon film 6 having a thickness of 350 nm is formed on the entire surface by a reduced pressure vapor deposition method. Next, an interlayer insulating film 7 of about 30 nm made of a silicon oxide film is formed on the entire surface by a reduced pressure vapor deposition method using TOES, and is subjected to a heat treatment at 900 ° C. to perform densification. Next, a polysilicon film 8 having a thickness of about 400 nm is sequentially formed by a known reduced pressure vapor deposition method.

Next, as shown in FIGS. 4A and 4B, the polysilicon film 8 is etched by a known photo-etching technique so as to leave a portion that can be a control gate electrode. A control gate electrode 8 made of a film is formed. Next, using the control gate electrode 8 as a mask, the interlayer insulating film 7 and the polysilicon film 6 are etched to form a floating gate electrode 6 made of a polysilicon film. Then TEOS and C
By high-density plasma CVD technique using ₂ F ₆ gas,
A silicon oxide film containing fluorine (a relative dielectric constant of about 3) is deposited on the entire surface as the low dielectric constant insulating film 18.

Next, as shown in FIGS. 5A and 5B, a silicon oxide film containing fluorine, which is a low dielectric insulating film 18, is flattened by a known CMP (chemical mechanical polishing) method. Then, an insulating film 9 of a silicon oxide film is covered over the entire surface by a known vapor deposition method. Note that the subsequent metal wiring step, protective film forming step, and bonding pad forming step are omitted.

Through the above manufacturing steps, a semiconductor memory array device as shown in FIGS. 1 and 2 can be formed. In the first embodiment, an example of the structure in which the low dielectric constant insulating film 18 is provided between both the adjacent floating gate electrodes 6 and between the adjacent control gate electrodes 8 has been described. It goes without saying that the same effect is obtained only between the gate electrodes 6 and only between the adjacent control gate electrodes 8.

Further, in the first embodiment, the example in which the fluorine-doped polyimide film and the fluorine-doped silicon oxide film are used as the low dielectric constant insulating film 18 has been described. Needless to say, any film and any manufacturing method may be used as long as the film is an insulating film having a lower dielectric constant than the silicon oxide film, such as an organic SOG film. Furthermore, the first
In the embodiment, the example of the stacked gate structure in which the gate insulating film 5 and the floating gate electrode 6 are formed on the entire surface of the channel region sandwiched between the source region 3 and the drain region 4 has been described. Needless to say, the same applies to a split gate structure in which a gate insulating film and a floating gate electrode are formed in a part of a channel region sandwiched between the gate insulating film and the floating gate electrode. The same applies to a structure including a tunneling region in which only a part of the gate insulating film over the channel region is thinned.

(Second Embodiment) FIG. 6 and FIG.
It is a plan view and a sectional view of a semiconductor memory array device including EEPROM cells having a floating gate structure according to a second embodiment of the present invention. FIG.
FIG. 7B is a cross-sectional view taken along the line BB ′ of FIG. 6.

As shown in FIGS. 6 and 7, on the surface of a semiconductor substrate 1 using a P-type silicon substrate, a source region 3 composed of an N-type diffusion layer, a drain region 4 and a device isolation composed of a silicon oxide film are formed. An insulating film 2 is formed. On a channel region sandwiched between the source region 3 and the drain region 4, a gate insulating film 5 made of a thin silicon oxide film and a floating gate electrode 6 made of a polysilicon film, which can be a tunneling medium of about 10 nm, are formed.
On the floating gate electrode 6, an interlayer insulating film 7 composed of a silicon oxide film-silicon nitride film-silicon oxide film of about 30 nm is formed, and a control gate electrode 8 composed of a polysilicon film of about 400 nm is formed thereon. Have been. Further, a cavity 20 surrounded by an insulating film 19 of a silicon oxide film is provided in a gap with a space 10 between the floating gate electrodes 6 and a gap with a space 11 between the control gate electrodes 8.

As described above, according to the semiconductor memory array device of the second embodiment, cavities are provided at intervals 10 between adjacent floating gate electrodes 6 and intervals 11 between adjacent control gate electrodes 8. As a result, the capacitive coupling between the adjacent floating gate electrodes 6 and between the adjacent control gate electrodes 8 is weakened.
It is possible to suppress the influence of the state of charge of the ROM cell.

Next, a method for manufacturing the semiconductor memory array device according to the second embodiment will be described with reference to FIGS. 8A is a cross-sectional view taken along the line AA ′ in FIG. 6, and FIG. 8B is a cross-sectional view taken along the line BB ′ in FIG. 9 (a) and 9 (b) are the same. First, as shown in FIGS. 8 (a) and 8 (b), a source region 3 composed of an N type diffusion layer and a drain are formed on a semiconductor substrate 1 using a P type silicon substrate by a known selective diffusion technique. Region 4 is formed. Thereafter, an element isolation insulating film 2 of a silicon oxide film having a thickness of about 500 nm for isolating the active region is formed by a known selective oxidation method.
A gate insulating film 5 of a 0 nm silicon oxide film is formed by a thermal oxidation method. A polysilicon film 6 having a thickness of 350 nm is formed on the entire surface by a reduced pressure vapor deposition method. Next, an interlayer insulating film 7 of about 30 nm made of a silicon oxide film is formed on the entire surface by a reduced pressure vapor deposition method using TOES, and is subjected to a heat treatment at 900 ° C. to perform densification. Next, a polysilicon film 8 having a thickness of about 400 nm is sequentially formed by a known reduced pressure vapor deposition method.

Next, as shown in FIGS. 9A and 9B, the polysilicon film 8 is etched by a known photo-etching technique so as to leave a portion that can be a control gate electrode. A control gate electrode 8 made of a film is formed. Next, using the control gate electrode 8 as a mask, the interlayer insulating film 7 and the polysilicon film 6 are etched to form a floating gate electrode 6 made of a polysilicon film. Next, an insulating film 19 of a silicon oxide film is deposited on the entire surface by a normal pressure vapor phase growth method using silane gas and oxygen. At this time, if deposited at normal pressure, the silicon oxide film 19 is not completely buried between the narrow trenches, that is, between the control gate electrodes 8 and between the floating gate electrodes 6, but overhangs to form a cavity 20. Next, an insulating film 9 of a silicon oxide film is entirely covered thereon by a known vapor deposition method.

The subsequent metal wiring step, protective film forming step and bonding pad forming step are omitted. Through the above manufacturing steps, a semiconductor memory array device as shown in FIGS. 6 and 7 can be formed. Second
In the embodiment, the adjacent floating gate electrode 6
Although an example of the structure having a cavity between both electrodes between adjacent control gate electrodes 8 and between adjacent control gate electrodes 8 has been described, the same effect can be obtained only between floating gate electrodes 6 and only between adjacent control gate electrodes 8. Needless to say, there is.

In the second embodiment, as an example of the method of forming the cavity 20, a method using an overhang of a normal pressure vapor phase growth method is used.
Needless to say, any manufacturing method may be used as long as the method can be used. In addition, although a vacuum state is preferable in the cavity 20, even if a gas such as an atmospheric gas is contained, the same effect is obtained.

Further, in the second embodiment, an example of a stacked gate structure in which the gate insulating film 5 and the floating gate electrode 6 are formed on the entire surface of the channel region sandwiched between the source region 3 and the drain region 4 has been described. Needless to say, the same applies to a split gate structure in which a gate insulating film and a floating gate electrode are formed in a part of a channel region sandwiched between the source region 3 and the drain region 4. The same applies to a structure including a tunneling region in which only a part of the gate insulating film over the channel region is thinned.

(Third Embodiment) FIGS. 10 and 11
FIG. 9 is a plan view and a cross-sectional view of a semiconductor memory array device including EEPROM cells having a floating gate structure provided with an erase gate according to a third embodiment of the present invention. FIG. 11A is a sectional view taken along line AA ′ of FIG.
FIG. 11B is a sectional view taken along the line BB ′ of FIG. 10.

As shown in FIGS. 10 and 11, on the surface of the semiconductor substrate 1 of a P-type silicon substrate, an element comprising a source region 3, a drain region 4 composed of an N-type diffusion layer and silicon oxide films 12, 13 is formed. An isolation insulating film is formed.
A gate insulating film 5 made of a silicon oxide film of about 30 nm and a floating gate electrode 6 made of a polysilicon film are formed on a part of the channel region sandwiched between the source region 3 and the drain region 4. On the floating gate electrode 6 and on the silicon substrate other than the floating gate electrode 6 region, an interlayer insulating film 7 of a silicon oxide film of about 30 nm is formed, and a control gate electrode 8 of a polysilicon film of about 400 nm is formed thereon. Have been. A tunneling insulating film 17 of a silicon oxide film of about 35 nm is formed on the side wall surface of the floating gate electrode 6. Furthermore, about 400 nm
The erase gate electrode 16 made of a polysilicon film is formed by the tunneling insulating film 17 and the silicon oxide film 15 (about 200 n).
m) and the silicon oxide film 14 (about 300 nm). Further, a fluorine-added polyimide film (a relative dielectric constant of about 2.7), which is a low-dielectric-constant insulating film 18, is formed in the gap of the interval 10 between the floating gate electrodes 6.

As described above, according to the semiconductor memory array device of the third embodiment, the tunneling insulating film 1 is provided between the erase gate electrode 16 and the floating gate electrode 6.
7, the adjacent floating gate electrode 6 is formed.
The interval 10 between the adjacent control gate electrodes 8 is smaller than the interval 11 between the adjacent control gate electrodes 8. As a result, the capacitive coupling between adjacent floating gate electrodes 6 is weakened.
It is possible to suppress the influence of the charge state of the EPROM cell.

Next, a method of manufacturing the semiconductor memory array device according to the third embodiment will be described with reference to FIGS. FIG.
FIG. 12B is a cross-sectional view of the A ′ cutting position, and FIG.
It is sectional drawing of B 'cutting position. FIG. 13 (a), FIG.
The same applies to FIGS. 15 (a) and 15 (b) from (b). First, as shown in FIGS. 12A and 12B,
A source region 3 and a drain region 4 made of an N-type diffusion layer are formed on a semiconductor substrate 1 of a P-type silicon substrate by a known selective diffusion technique. After that, a silicon oxide film 12 is formed to a thickness of 500 nm by a reduced pressure vapor phase epitaxy method using TEOS, and then densified by processing in a 900 ° C. thermal oxidation atmosphere. Next, a predetermined portion of the silicon oxide film 12 is opened by a known photo-etching technique. Thereafter, a silicon oxide film 13 having a thickness of about 200 nm is grown on the entire surface by a low pressure vapor deposition method using TEOS, and subsequently, a silicon oxide film 13 is formed on the side wall surface of the opening by using a known anisotropic dry etching technique. 13 is formed. The element isolation insulating film 1 made of a silicon oxide film is formed by the sidewall insulating film.
Step 2 is alleviated. Next, a silicon oxide film 5 having a thickness of about 30 nm is formed by oxidizing the surface of the P-type silicon substrate by a thermal oxidation method at about 900 ° C. 35
It is formed with a thickness of 0 nm. Next, predetermined portions of the polysilicon film 6 and the silicon oxide film 5 are selectively etched away by a known photoetching technique. Next, an interlayer insulating film 7 of about 30 nm made of a silicon oxide film is formed on the entire surface by a reduced pressure vapor deposition method using TOES, and is subjected to a heat treatment at 900 ° C. to perform densification. Next, a polysilicon film 8 having a thickness of about 400 nm is formed by a known low pressure vapor deposition method, and a silicon oxide film 14 having a thickness of about 300 nm is formed by a low pressure vapor deposition method using TOES.

Next, as shown in FIGS. 13 (a) and 13 (b), the silicon oxide film 14 is etched by a known photo-etching technique so as to leave a portion which can be a control gate electrode. Polysilicon film 8 and interlayer insulating film 7 using silicon oxide film 14 as a mask.
Is etched to form a control gate electrode 8 made of a polysilicon film. Next, a silicon oxide film having a thickness of about 250 nm is grown on the entire surface by a reduced pressure vapor deposition method using TOES, and subsequently, the control gate electrode 8 and the silicon oxide on the control gate electrode 8 are formed using a known anisotropic dry etching technique. A sidewall insulating film made of a silicon oxide film 15 is formed on the side wall surface of the film 14.

Next, as shown in FIGS. 14A and 14B, the polysilicon film 6 is etched by using the side wall insulating film made of the silicon oxide film 15 as a mask to form a floating gate made of the polysilicon film. An electrode 6 is formed. At this time, only the side wall surface of the floating gate electrode 6 is exposed. Next, the exposed portion of the side wall surface of the floating gate electrode 6 is thermally oxidized in a steam atmosphere at 900 ° C. to form a tunneling insulating film 17 of about 30 nm made of a polysilicon oxide film. Next, a polysilicon film of about 400 nm is formed on the entire surface by a known reduced pressure vapor deposition method, and an erase gate electrode 16 made of a polysilicon film is formed by a known photo etching technique so as to cover the tunneling insulating film 17. I do. At this time, the erase gate electrode 16 is formed not every gap between the floating gate electrodes 6 but every other gap. Next, a silicon oxide film containing fluorine (a relative dielectric constant of about 3) is deposited on the entire surface as a low dielectric constant insulating film 18 by a high-density plasma CVD technique using TEOS and C ₂ F ₆ gas.

Next, as shown in FIGS. 15A and 15B, a silicon oxide film containing fluorine, which is a low dielectric insulating film 18, is flattened by a known CMP (chemical mechanical polishing) method. Then, the entire surface is covered with a silicon oxide film 9 by a known vapor deposition method. Note that the subsequent metal wiring step, protective film forming step, and bonding pad forming step are omitted.

By the above manufacturing steps, FIGS.
A semiconductor memory array device as shown in FIG. Further, in the third embodiment, the example in which the fluorine-doped polyimide film and the fluorine-doped silicon oxide film are used as the low dielectric constant insulating film 18 has been described.
It goes without saying that any film and any manufacturing method may be used as long as the insulating film has a lower dielectric constant than the silicon oxide film, such as an OG film and an organic SOG film.

Further, in the third embodiment, an example of the split structure in which the gate insulating film 5 and the floating gate electrode 6 are formed in a part of the channel region sandwiched between the source region 3 and the drain region 4 has been described. Needless to say, the same applies to a stacked gate structure in which a gate insulating film and a floating gate electrode are formed on the entire channel region sandwiched between the source region 3 and the drain region 4. Also,
The same applies to a structure including a tunneling region in which only a part of the gate insulating film on the channel region is thinned.

(Fourth Embodiment) FIGS. 16 and 17
FIG. 11 is a plan view and a cross-sectional view of a semiconductor memory array device including EEPROM cells having a floating gate structure provided with an erase gate according to a fourth embodiment of the present invention. FIG. 17A is a sectional view taken along line AA ′ of FIG.
FIG. 17B is a sectional view taken along line BB ′ of FIG.

As shown in FIGS. 16 and 17, on the surface of the semiconductor substrate 1 of a P-type silicon substrate, an element composed of a source region 3, a drain region 4 composed of an N-type diffusion layer and silicon oxide films 12, 13 is formed. An isolation insulating film is formed.
A floating gate electrode in which a gate insulating film 5 made of a silicon oxide film of about 30 nm and a floating gate electrode 6 made of a polysilicon film are formed on a part of the channel region sandwiched between the source region 3 and the drain region 4. 6, an interlayer insulating film 7 of a silicon oxide film of about 30 nm is formed on the silicon substrate other than the region of the floating gate electrode 6, and a control gate electrode 8 of a polysilicon film of about 400 nm is formed thereon. . A tunneling insulating film 17 of a silicon oxide film of about 35 nm is formed on the side wall surface of the floating gate electrode 6. Further, the erase gate electrode 16 made of a polysilicon film of about 400 nm is formed by the tunneling insulating film 17 and the silicon oxide film 15 (about 200 n).
m) and the silicon oxide film 14 (about 300 nm). Further, a cavity 20 surrounded by a silicon oxide film 19 is provided in a gap at an interval 10 between the floating gate electrodes 6.

As described above, according to the semiconductor memory array device of the fourth embodiment, the tunneling insulating film 1 is provided between the erase gate electrode 16 and the floating gate electrode 6.
7, the space 10 between the adjacent floating gate electrodes is smaller than the space 11 between the adjacent control gate electrodes 6. Is provided with a cavity 20, the capacitive coupling between adjacent floating gate electrodes 6 is weakened, and the influence of the state of charge of the adjacent EEPROM cell at the time of reading can be suppressed even if the miniaturization is further promoted. Become.

Next, a method of manufacturing the semiconductor memory array device according to the fourth embodiment will be described with reference to FIGS.
This will be described with reference to FIG. FIG.
FIG. 18B is a cross-sectional view of the cutting position of A ′, and FIG.
It is sectional drawing of the cutting position of B '. FIG. 19 (a), FIG.
The same applies to FIGS. 20 (a) and 20 (b) from (b).

First, as shown in FIGS. 18A and 18B, a source region 3 made of an N-type diffusion layer is formed on a P-type silicon substrate 1 by a known selective diffusion technique. The drain region 4 is formed. After that, the silicon oxide film 12 is formed into a 500
After forming with a thickness of nm, it is densified by processing in a thermal oxidation atmosphere at 900 ° C. Next, a predetermined portion of the silicon oxide film 12 is opened by a known photo-etching technique. Thereafter, a silicon oxide film 13 having a thickness of about 200 nm is grown on the entire surface by a low-pressure vapor deposition method using TEOS, and then a silicon oxide film 13 is formed on the side wall surface of the opening by using a known anisotropic dry etching technique. 13 is formed. The sidewall insulating film is used to reduce a step in the element isolation insulating film 12 made of a silicon oxide film. Next, a silicon oxide film 5 of about 30 nm is formed by oxidizing the surface on the P-type silicon substrate 1 by a thermal oxidation method at 900 ° C., and a polysilicon film 6 is entirely formed on the silicon oxide film 5 by a reduced pressure vapor deposition method. It is formed with a thickness of 350 nm. Next, predetermined portions of the polysilicon film 6 and the silicon oxide film 5 are selectively etched away by a known photoetching technique.
Next, an interlayer insulating film 7 of about 30 nm made of a silicon oxide film is formed on the entire surface by a reduced pressure vapor deposition method using TOES, and is subjected to a heat treatment at 900 ° C. to perform densification. Next, a polysilicon film 8 having a thickness of about 400 nm is formed by a known low pressure vapor deposition method, and a silicon oxide film 14 having a thickness of about 300 nm is formed by a low pressure vapor deposition method using TOES.

Next, as shown in FIGS. 19A and 19B, the silicon oxide film 14 is etched by a known photo-etching technique so as to leave a portion that can be a control gate electrode. Using the silicon oxide film 14 as a mask, the polysilicon film 8 and the interlayer insulating film 7 are etched to form a control gate electrode 8 made of a polysilicon film. Next, a silicon oxide film having a thickness of about 250 nm is grown on the entire surface by a reduced pressure vapor deposition method using TOES, and subsequently, the control gate electrode 8 and the silicon oxide A sidewall insulating film made of a silicon oxide film 15 is formed on the side wall surface of the film 14.

Next, as shown in FIGS. 20A and 20B, the polysilicon film 6 is etched using the side wall insulating film made of the silicon oxide film 15 as a mask to form a floating gate made of the polysilicon film. An electrode 6 is formed. At this time, only the side wall surface of the floating gate electrode 6 is exposed. Next, the exposed portion of the side wall surface of the floating gate electrode 6 is thermally oxidized in a steam atmosphere at 900 ° C. to form a tunneling insulating film 17 of about 30 nm made of a polysilicon oxide film. Next, a polysilicon film of about 400 nm is formed on the entire surface by a known reduced pressure vapor deposition method, and an erase gate electrode 16 made of a polysilicon film is formed by a known photo etching technique so as to cover the tunneling insulating film 17. I do. At this time, the erase gate electrodes 16 are not formed in all the gaps between the floating gate electrodes 6 but are formed in every other gap.
6 is formed. Next, a silicon oxide film 19 is deposited on the entire surface by a normal pressure vapor phase growth method using silane gas and oxygen. At this time, if deposited at normal pressure, the silicon oxide film 19 is not completely buried between the narrow trenches, that is, between the control gate electrodes 8 and between the floating gate electrodes 6, but overhangs to form a cavity 20. Next, the silicon oxide film 9 is entirely covered thereon by a known vapor deposition method.

By the above manufacturing steps, FIGS.
A semiconductor memory array device as shown in FIG. In the fourth embodiment, as an example of the method of forming the cavity 20, a method using an overhang of a normal pressure vapor deposition method has been described. It goes without saying that a manufacturing method may be used. The interior of the cavity is preferably in a vacuum state, but the same effect is obtained even when a gas such as atmospheric gas is contained.

Further, in the fourth embodiment, the example of the split structure in which the gate insulating film 5 and the floating gate electrode 6 are formed in a part of the channel region sandwiched between the source region 3 and the drain region 4 has been described. Needless to say, the same applies to a stacked gate structure in which a gate insulating film and a floating gate electrode are formed on the entire channel region sandwiched between the source region 3 and the drain region 4. Also,
The same applies to a structure including a tunneling region in which only a part of the gate insulating film on the channel region is thinned.

[0065]

According to the semiconductor memory array device of the present invention, since an insulating film having a dielectric constant lower than that of the silicon oxide film is provided between the adjacent floating gate electrodes, the space between the adjacent floating gate electrodes and the adjacent control electrode are provided. Even if the capacitive coupling between them becomes weaker and the spacing becomes smaller than, for example, submicron, it becomes possible to suppress the influence of the state of charge of the adjacent EEPROM cell at the time of reading, and to achieve high integration of the semiconductor memory array device having a floating gate structure. It can greatly contribute to higher performance and higher performance.

According to the semiconductor memory array device of the second aspect, the same effect as that of the first aspect is obtained. According to the semiconductor memory array device of the third aspect, the same effect as that of the first aspect is obtained. According to the semiconductor memory array device of the fourth aspect, the same effect as that of the first aspect is obtained.

According to the semiconductor memory array device of the fifth aspect, the same effect as that of the first aspect is obtained. According to the semiconductor memory array device of the sixth aspect, the same effect as that of the first aspect is obtained. According to the semiconductor memory array device of the seventh aspect, the same effect as that of the first aspect is obtained.

According to the semiconductor memory array device of the eighth aspect, the same effect as that of the first aspect is obtained. According to the method of manufacturing a semiconductor memory array device according to the ninth aspect, a first aspect is provided.
Has the same effect as. According to the method of manufacturing a semiconductor memory array device of the tenth aspect, the same effect as that of the first aspect can be obtained.

According to the method of manufacturing a semiconductor memory array device of the eleventh aspect, the same effect as that of the first aspect can be obtained. According to the method of manufacturing a semiconductor memory array device of the twelfth aspect, the same effect as that of the first aspect can be obtained. According to the method of manufacturing a semiconductor memory array device according to claim 13, claim 1 is provided.
Has the same effect as.

According to the method of manufacturing a semiconductor memory array device of the fourteenth aspect, the same effect as that of the first aspect can be obtained. According to the method of manufacturing a semiconductor memory array device according to the fifteenth aspect, the same effect as that of the first aspect can be obtained. According to the method of manufacturing a semiconductor memory array device according to claim 16, claim 1 is provided.
Has the same effect as.

[Brief description of the drawings]

FIG. 1 is a plan view for explaining a semiconductor memory array device according to a first embodiment of the present invention.

FIGS. 2A and 2B are cross-sectional views illustrating a semiconductor memory array device according to a first embodiment. FIG.
FIG. 2B is a sectional view taken along the line A ′, and FIG.

FIG. 3 is a sectional view of a manufacturing process for describing an initial process in manufacturing the semiconductor memory array device of FIGS. 1 and 2;

FIG. 4 is a cross-sectional view of a manufacturing step for explaining a step that follows the step of FIG. 3;

FIG. 5 is a cross-sectional view of a manufacturing step for explaining a step that follows the step of FIG. 4;

FIG. 6 is a plan view illustrating a semiconductor memory array device according to a second embodiment.

FIGS. 7A and 7B are cross-sectional views illustrating a semiconductor memory array device according to a second embodiment. FIG.
FIG. 7B is a sectional view taken along line A ′, and FIG. 7B is a sectional view taken along line BB ′ in FIG.

8 is a cross-sectional view of a manufacturing process for describing an initial process in manufacturing the semiconductor memory array device of FIGS. 6 and 7. FIG.

FIG. 9 is a cross-sectional view of the manufacturing process for describing a step that follows the step of FIG. 8;

FIG. 10 is a plan view illustrating a semiconductor memory array device according to a third embodiment.

FIGS. 11A and 11B are cross-sectional views illustrating a semiconductor memory array device according to a third embodiment; FIG. 11A is a cross-sectional view taken along line AA ′ of FIG. 10; It is B 'line sectional drawing.

FIG. 12 is a cross-sectional view of a manufacturing step for describing an initial step in manufacturing the semiconductor memory array device of FIGS. 10 and 11;

13 is a cross-sectional view of a manufacturing process for describing a step that follows the step of FIG.

14 is a cross-sectional view of a manufacturing process for describing a step that follows the step of FIG.

FIG. 15 is a cross-sectional view of the manufacturing process for describing a step that follows the step of FIG. 14;

FIG. 16 is a plan view illustrating a semiconductor memory array device according to a fourth embodiment.

FIGS. 17A and 17B are cross-sectional views illustrating a semiconductor memory array device according to a fourth embodiment; FIG. 17A is a cross-sectional view taken along line AA ′ of FIG. 16; It is B 'line sectional drawing.

FIG. 18 is a cross-sectional view of a manufacturing step for describing the first step in manufacturing the semiconductor memory array device of FIGS. 16 and 17.

FIG. 19 is a cross-sectional view of the manufacturing process for describing a step that follows the step of FIG. 18;

20 is a cross-sectional view of a manufacturing step for illustrating a step that follows the step of FIG.

FIG. 21 is a plan view illustrating a conventional semiconductor memory array device having a floating gate structure.

FIG. 22 is a sectional view illustrating a conventional semiconductor memory array device having a floating gate structure.
(A) is a sectional view taken along line AA 'of FIG. 21, and (b) is a sectional view taken along line BB' of FIG.

FIG. 23 is a plan view illustrating a conventional semiconductor memory array device having a floating gate structure provided with an erase gate electrode.

24A and 24B are cross-sectional views illustrating a conventional semiconductor memory array device having a floating gate structure provided with an erase gate electrode, wherein FIG. 24A is a cross-sectional view taken along line AA ′ of FIG. 23, and FIG. FIG. 24 is a sectional view taken along line BB ′ of FIG. 23.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate (P-type silicon substrate) 2 silicon oxide film (element isolation insulating film) 3 source region (N-type diffusion layer) 4 drain region (N-type diffusion layer) 5 silicon oxide film (gate insulating film) 6 polysilicon film (Floating gate electrode) 7 Silicon oxide film (interlayer insulating film) 8 Polysilicon film (control gate electrode) 9 Silicon oxide film 10 Interval between floating gate electrodes 11 Interval between control gate electrodes 12 Silicon oxide film (element isolation insulating film) 13) silicon oxide film (element isolation insulating film) 14 silicon oxide film 15 silicon oxide film (spacer film) 16 polysilicon film (erasing gate electrode) 17 tunneling insulating film 18 low dielectric constant insulating film 19 silicon oxide film 20 cavity

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) JA02 JA04 JA32 JA60 KA01 NA02 PR03 PR12 PR21 PR33 PR40

Claims (16)

[Claims] 1. A semiconductor device having a source region and a drain region in a semiconductor substrate of one conductivity type, a first insulating film in a predetermined region on the semiconductor substrate, and a floating gate on the first insulating film. A semiconductor memory array device having at least two or more memory cells having electrodes and at least a control gate electrode on said floating gate electrode via a second insulating film, wherein each of said semiconductor memory array devices A semiconductor memory array device comprising an insulating film having a dielectric constant lower than that of a silicon oxide film between the floating gate electrodes. 2. A semiconductor device having a source region and a drain region in a semiconductor substrate of one conductivity type, a first insulating film in a predetermined region on the semiconductor substrate, and a floating gate on the first insulating film. A semiconductor memory array device having at least two or more memory cells having electrodes and at least a control gate electrode on said floating gate electrode via a second insulating film, wherein each of said semiconductor memory array devices And an insulating film having a lower dielectric constant than the silicon oxide film between the control gate electrodes. 3. A semiconductor device having a source region and a drain region in a semiconductor substrate of one conductivity type, a first insulating film in a predetermined region on the semiconductor substrate, and a floating gate on the first insulating film. A semiconductor memory array device having at least two or more memory cells having electrodes and at least a control gate electrode on said floating gate electrode via a second insulating film, wherein each of said semiconductor memory array devices A semiconductor memory array device comprising an insulating film having a lower dielectric constant than a silicon oxide film between the floating gate electrodes and between the control gate electrodes. 4. A semiconductor device having a source region and a drain region in a semiconductor substrate of one conductivity type, a first insulating film in a predetermined region on the semiconductor substrate, and a floating gate on the first insulating film. A semiconductor memory array device having at least two or more memory cells having electrodes and at least a control gate electrode on the floating gate electrode via a second insulating film, wherein each of the semiconductor memory array devices A cavity between the floating gate electrodes. 5. A semiconductor substrate of one conductivity type having a source region and a drain region, a first insulating film in a predetermined region on the semiconductor substrate, and a floating gate on the first insulating film. A semiconductor memory array device having at least two or more memory cells having electrodes and at least a control gate electrode on said floating gate electrode via a second insulating film, wherein each of said semiconductor memory array devices Wherein a cavity is provided between the control gate electrodes. 6. A semiconductor substrate having a source region and a drain region in a semiconductor substrate of one conductivity type, a first insulating film in a predetermined region on the semiconductor substrate, and a floating gate on the first insulating film. A semiconductor memory array device having at least two or more memory cells having electrodes and at least a control gate electrode on said floating gate electrode via a second insulating film, wherein each of said semiconductor memory array devices And a cavity between the floating gate electrodes and between the control gate electrodes. 7. A semiconductor substrate of one conductivity type having a source region and a drain region, a first insulating film in a predetermined region on the semiconductor substrate, and a floating gate on the first insulating film. An electrode, and a control gate electrode on the floating gate electrode via a second insulating film. The control gate electrode is in contact with the floating gate electrode via an insulating film which can be a tunneling medium, and the control gate electrode is connected to the third gate electrode. A semiconductor memory array device comprising at least three or more memory cells having at least three erase gate electrodes in contact with each other via an insulating film, wherein oxidation is performed between the floating gate electrodes of the semiconductor memory array device that do not have the erase gate electrode. A semiconductor memory array device comprising an insulating film having a lower dielectric constant than a silicon film. 8. A semiconductor substrate of one conductivity type having a source region and a drain region, a first insulating film in a predetermined region on the semiconductor substrate, and a floating gate on the first insulating film. An electrode, and a control gate electrode on the floating gate electrode via a second insulating film. The control gate electrode is in contact with the floating gate electrode via an insulating film that can be a tunneling medium. A semiconductor memory array device provided with at least three or more memory cells having at least an erase gate electrode in contact with an insulating film interposed therebetween, wherein the semiconductor memory array device is provided between the floating gate electrodes without the erase gate electrode. A semiconductor memory array device comprising a cavity. 9. A step of forming a source region and a drain region of a conductivity type opposite to the semiconductor substrate in a semiconductor substrate of one conductivity type, and forming an active region separated by an element isolation insulating film on the semiconductor substrate. Forming a gate insulating film on the active region; and forming a first conductive film on a surface of the gate insulating film and the element isolation insulating film.
Forming a control gate electrode by etching and removing predetermined portions of the interlayer insulating film and the second conductive film; forming the control gate electrode by etching and removing predetermined portions of the interlayer insulating film and the second conductive film; Using the gate electrode as a mask,
A method of manufacturing a semiconductor memory array device, comprising at least a step of forming a floating gate electrode by etching and removing said first conductive film, wherein said first conductive film is formed when said floating gate electrode is formed. Forming an insulating film having a dielectric constant lower than that of a silicon oxide film in a portion where the silicon oxide film is removed by etching. 10. A step of forming a source region and a drain region of a conductivity type opposite to the semiconductor substrate in a semiconductor substrate of one conductivity type, and forming an active region separated by an element isolation insulating film on the semiconductor substrate. Performing a step of forming a gate insulating film on the active region; and sequentially stacking a first conductive film, an interlayer insulating film, and a second conductive film on surfaces of the gate insulating film and the element isolation insulating film. Forming a control gate electrode by etching and removing predetermined portions of the interlayer insulating film and the second conductive film; and forming the first conductive film using the control gate electrode as a mask. Forming a floating gate electrode by etching the semiconductor device, wherein the method comprises forming the control gate electrode. Forming an insulating film having a dielectric constant lower than that of a silicon oxide film on a portion formed when the second conductive film is removed by etching. 11. A step of forming a source region and a drain region of a conductivity type opposite to the semiconductor substrate in a semiconductor substrate of one conductivity type, and forming an active region separated by an element isolation insulating film on the semiconductor substrate. Performing a step of forming a gate insulating film on the active region; and sequentially stacking a first conductive film, an interlayer insulating film, and a second conductive film on surfaces of the gate insulating film and the element isolation insulating film. Forming a control gate electrode by etching and removing predetermined portions of the interlayer insulating film and the second conductive film; and forming the first conductive film using the control gate electrode as a mask. A method of manufacturing a semiconductor memory array device, comprising at least a step of forming a floating gate electrode by removing a floating gate electrode by etching. A portion formed when the first conductive film is removed by etching and a portion formed when forming the control gate electrode and removed by etching the second conductive film, A method for manufacturing a semiconductor memory array device, comprising a step of forming an insulating film having a dielectric constant. 12. A step of forming a source region and a drain region of a conductivity type opposite to the semiconductor substrate in a semiconductor substrate of one conductivity type, and forming an active region separated by an element isolation insulating film on the semiconductor substrate. Performing a step of forming a gate insulating film on the active region; and sequentially stacking a first conductive film, an interlayer insulating film, and a second conductive film on surfaces of the gate insulating film and the element isolation insulating film. Forming a control gate electrode by etching and removing predetermined portions of the interlayer insulating film and the second conductive film; and forming the first conductive film using the control gate electrode as a mask. A method of manufacturing a semiconductor memory array device, comprising at least a step of forming a floating gate electrode by removing a floating gate electrode by etching. Forming a cavity in a portion formed at the time of etching and removing the first conductive film by etching. 13. A step of forming a source region and a drain region of a conductivity type opposite to the semiconductor substrate in a semiconductor substrate of one conductivity type, and forming an active region separated by an element isolation insulating film on the semiconductor substrate. Performing a step of forming a gate insulating film on the active region; and sequentially stacking a first conductive film, an interlayer insulating film, and a second conductive film on surfaces of the gate insulating film and the element isolation insulating film. Forming a control gate electrode by etching and removing predetermined portions of the interlayer insulating film and the second conductive film; and forming the first conductive film using the control gate electrode as a mask. Forming a floating gate electrode by etching the semiconductor device, wherein the method comprises forming the control gate electrode. Forming a cavity in a portion formed at the time of etching and removing the second conductive film by etching. 14. A step of forming a source region and a drain region of a conductivity type opposite to the semiconductor substrate in a semiconductor substrate of one conductivity type, and forming an active region separated by an element isolation insulating film on the semiconductor substrate. Performing a step of forming a gate insulating film on the active region; and sequentially stacking a first conductive film, an interlayer insulating film, and a second conductive film on surfaces of the gate insulating film and the element isolation insulating film. Forming a control gate electrode by etching and removing predetermined portions of the interlayer insulating film and the second conductive film; and forming the first conductive film using the control gate electrode as a mask. Forming a floating gate electrode by etching the semiconductor device, wherein the floating gate electrode is formed. Forming cavities in a portion formed when forming and removing the first conductive film and a portion formed when forming the control gate electrode and removing the second conductive film by etching. A method for manufacturing a semiconductor memory array device, comprising: 15. A step of forming a source region and a drain region of a conductivity type opposite to the semiconductor substrate in a semiconductor substrate of one conductivity type, and forming an active region separated by an element isolation insulating film on the semiconductor substrate. Forming a gate insulating film on the active region; forming a first conductive film, a first insulating film, a second conductive film on the surfaces of the gate insulating film and the element isolation insulating film; Forming a second insulating film by sequentially laminating the first insulating film and the second insulating film;
Forming an insulating film on the control gate electrode by etching and removing predetermined portions of the conductive film and the second insulating film to form the control gate electrode and the interlayer insulating film; and an insulating film on the control gate electrode. Forming a sidewall insulating film on a side wall surface of the control gate electrode and the interlayer insulating film; and forming a floating gate electrode by etching and removing the first conductive film using the sidewall insulating film as a mask. Forming a tunneling insulating film that can serve as a tunneling medium on a side wall surface of the floating gate electrode; and covering a surface of the insulating film on the tunneling insulating film, the sidewall insulating film, and the control gate electrode. Forming erase gate electrode made of third conductive film A method of manufacturing a semiconductor memory array including at least a step of forming an insulating film having a dielectric constant lower than that of a silicon oxide film in a portion formed when forming the floating gate electrode and removing the first conductive film by etching. A method for manufacturing a semiconductor memory array device, comprising: 16. A step of forming a source region and a drain region of a conductivity type opposite to the semiconductor substrate in a semiconductor substrate of one conductivity type, and forming an active region separated by an element isolation insulating film on the semiconductor substrate. Performing a step of forming a gate insulating film on the active region; and forming a first conductive film on the surface of the gate insulating film and the element isolation insulating film.
Forming a first insulating film, a second conductive film, and a second insulating film by sequentially laminating the first insulating film, the second conductive film, and a second insulating film; Forming an insulating film on the control gate electrode, the control gate electrode and the interlayer insulating film by etching away a portion; and forming the insulating film on the control gate electrode, the side wall surface of the control gate electrode and the interlayer insulating film on the control gate electrode. Forming a side wall insulating film, forming the floating gate electrode by etching and removing the first conductive film using the side wall insulating film as a mask, and forming a tunneling medium on a side wall surface of the floating gate electrode. Forming a tunneling insulating film that can be used as the tunneling insulating film, the sidewall insulating film, and the control. A method of manufacturing a semiconductor memory array including at least a step of forming an erase gate electrode made of a third conductive film so as to cover a surface of the insulating film on the gate electrode. A method for manufacturing a semiconductor memory array device, comprising: forming a cavity in a portion formed and where the first conductive film is removed by etching.