JPS6418249A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6418249A
JPS6418249A JP62175131A JP17513187A JPS6418249A JP S6418249 A JPS6418249 A JP S6418249A JP 62175131 A JP62175131 A JP 62175131A JP 17513187 A JP17513187 A JP 17513187A JP S6418249 A JPS6418249 A JP S6418249A
Authority
JP
Japan
Prior art keywords
capacitance
electrode
groove
substrate
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62175131A
Other languages
Japanese (ja)
Inventor
Yutaka Maruo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP62175131A priority Critical patent/JPS6418249A/en
Publication of JPS6418249A publication Critical patent/JPS6418249A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0214Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0218Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of field effect structures

Abstract

PURPOSE:To reduce an area on a wafer required to obtain a capacitance value identical to the conventional capacitance by a method wherein a groove is made in a silicon substrate, the substrate is used as a first electrode for the capacitance, an insulating film is formed on side walls and a bottom face of the groove made in the substrate, the groove is filled with a conductor and the conductor is used as a second electrode for the capacitance. CONSTITUTION:A groove is made in a silicon substrate 1; the substrate 1 is used as a first electrode 6 for the capacitance; an insulating film 7 is formed on side walls and a bottom face of the groove made in the substrate 1; the groove is filled with a conductor; this conductor is used as a second electrode 8 for the capacitance. Although an area for the formed capacitance by piling up the first electrode 6 and the second electrode 8 is large, a plane area on the wafer 1 is small. By this setup, it is possible to obtain a high-capacitance value even with a small area on the wafer required to form the capacitance in the boosting circuit of a semiconductor nonvolatile memory.
JP62175131A 1987-07-14 1987-07-14 Semiconductor device Pending JPS6418249A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62175131A JPS6418249A (en) 1987-07-14 1987-07-14 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62175131A JPS6418249A (en) 1987-07-14 1987-07-14 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6418249A true JPS6418249A (en) 1989-01-23

Family

ID=15990828

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62175131A Pending JPS6418249A (en) 1987-07-14 1987-07-14 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6418249A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003309182A (en) * 2002-04-17 2003-10-31 Hitachi Ltd Method of manufacturing semiconductor device and semiconductor device
JP2009071325A (en) * 2008-11-25 2009-04-02 Renesas Technology Corp Semiconductor device and method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003309182A (en) * 2002-04-17 2003-10-31 Hitachi Ltd Method of manufacturing semiconductor device and semiconductor device
JP2009071325A (en) * 2008-11-25 2009-04-02 Renesas Technology Corp Semiconductor device and method for manufacturing the same

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