JPS57103349A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS57103349A
JPS57103349A JP55180892A JP18089280A JPS57103349A JP S57103349 A JPS57103349 A JP S57103349A JP 55180892 A JP55180892 A JP 55180892A JP 18089280 A JP18089280 A JP 18089280A JP S57103349 A JPS57103349 A JP S57103349A
Authority
JP
Japan
Prior art keywords
capacity
projection
substrate
forming
cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55180892A
Other languages
Japanese (ja)
Inventor
Junichi Mihashi
Takeshi Yamano
Takayuki Matsukawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP55180892A priority Critical patent/JPS57103349A/en
Publication of JPS57103349A publication Critical patent/JPS57103349A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To improve the integration density of a semiconductor memory by forming a convex projection or concave recess on a substrate and forming a conductor layer via an insulating film on the surface as a cell capacity, thereby increasing the charge storage capacity without increasing the cell area. CONSTITUTION:In a dynamic MOS memory, a P type substrate 1 is etched (or epitaxially grown) to selectively form a projection 1a (or recess 1b) in the substrate 1. This projection 1a is used as a cell capacity forming part, and a capacity gate electrode 5 is formed by an ordinary process via an oxidized film 4. When the height of the projection 1a is, for example, H, the capacity can be increased in the amount corresponding to 2H(L+W) with the same cell area, where W represents the width of the capacity, and L represents the length. Thus, the charge storage capacity can be increased with small occupying area, thereby enabling the increase in the density.
JP55180892A 1980-12-18 1980-12-18 Semiconductor memory device Pending JPS57103349A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55180892A JPS57103349A (en) 1980-12-18 1980-12-18 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55180892A JPS57103349A (en) 1980-12-18 1980-12-18 Semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS57103349A true JPS57103349A (en) 1982-06-26

Family

ID=16091147

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55180892A Pending JPS57103349A (en) 1980-12-18 1980-12-18 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS57103349A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60214559A (en) * 1984-04-10 1985-10-26 Nec Corp Mos type memory device
JPS61222255A (en) * 1985-03-28 1986-10-02 Fujitsu Ltd Manufacture of semiconductor memory device
US6897932B2 (en) * 1997-12-19 2005-05-24 Seiko Epson Corporation Electro-optical device having a concave recess formed above a substrate in correspondence with a plurality of wirings and an electro-optical apparatus having same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60214559A (en) * 1984-04-10 1985-10-26 Nec Corp Mos type memory device
JPH0370905B2 (en) * 1984-04-10 1991-11-11 Nippon Electric Co
JPS61222255A (en) * 1985-03-28 1986-10-02 Fujitsu Ltd Manufacture of semiconductor memory device
US6897932B2 (en) * 1997-12-19 2005-05-24 Seiko Epson Corporation Electro-optical device having a concave recess formed above a substrate in correspondence with a plurality of wirings and an electro-optical apparatus having same

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