JPS57133668A - Semiconductor memory storage - Google Patents

Semiconductor memory storage

Info

Publication number
JPS57133668A
JPS57133668A JP56019216A JP1921681A JPS57133668A JP S57133668 A JPS57133668 A JP S57133668A JP 56019216 A JP56019216 A JP 56019216A JP 1921681 A JP1921681 A JP 1921681A JP S57133668 A JPS57133668 A JP S57133668A
Authority
JP
Japan
Prior art keywords
well
cell
fet
another
capacity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56019216A
Other languages
Japanese (ja)
Other versions
JPH0150114B2 (en
Inventor
Zensuke Matsuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56019216A priority Critical patent/JPS57133668A/en
Publication of JPS57133668A publication Critical patent/JPS57133668A/en
Publication of JPH0150114B2 publication Critical patent/JPH0150114B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To enable the coexistence of the increase of speed and density by each forming one element type memory cell and another FET into separate reverse conduction type well and making reverse bias given to another well larger than the well used for the cell. CONSTITUTION:A CMOS type memory storage is formed in such a manner that a memory cell with two layer poly Si structure is prepared into a P well 2a formed to a substrate such as an N type substrate 1, and the N channel FET is prepared into another P well 2b and a P channel FET in a substrate region. The well 2a of the storage is given base potential (OV) by an electrode 10a while the well 2b is given more negative potential. Accordingly, since the reverse bias of the cell section is not deepened, the decrease of cell capacity (particularly, the capacity of a depletion layer) can be prevented, and a holding characteristic can be improved and density can be increased. On the other hand, since the well 2b encasing a peripheral FET is reversely biased deeply, parasitic capacity can be reduced, and speed can be increased.
JP56019216A 1981-02-12 1981-02-12 Semiconductor memory storage Granted JPS57133668A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56019216A JPS57133668A (en) 1981-02-12 1981-02-12 Semiconductor memory storage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56019216A JPS57133668A (en) 1981-02-12 1981-02-12 Semiconductor memory storage

Publications (2)

Publication Number Publication Date
JPS57133668A true JPS57133668A (en) 1982-08-18
JPH0150114B2 JPH0150114B2 (en) 1989-10-27

Family

ID=11993173

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56019216A Granted JPS57133668A (en) 1981-02-12 1981-02-12 Semiconductor memory storage

Country Status (1)

Country Link
JP (1) JPS57133668A (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60136253A (en) * 1983-12-24 1985-07-19 Toshiba Corp C-mos semiconductor memory
JPS61229352A (en) * 1985-02-12 1986-10-13 エスジェーエス―トムソン　ミクロエレクトロニクス　ソシエテ　アノニム Ic type dynamic memory and manufacture thereof
US4646425A (en) * 1984-12-10 1987-03-03 Solid State Scientific, Inc. Method for making a self-aligned CMOS EPROM wherein the EPROM floating gate and CMOS gates are made from one polysilicon layer
JPS6251252A (en) * 1985-08-30 1987-03-05 Toshiba Corp Random access memory
JPS6251251A (en) * 1985-08-30 1987-03-05 Toshiba Corp Static type random access memory
JPH01109762A (en) * 1987-10-22 1989-04-26 Oki Electric Ind Co Ltd Semiconductor memory
JPH01253264A (en) * 1988-03-31 1989-10-09 Sharp Corp Semiconductor integrated circuit
JPH0267759A (en) * 1988-09-01 1990-03-07 Nec Corp Semiconductor memory device
JPH03232272A (en) * 1990-02-07 1991-10-16 Mitsubishi Electric Corp Semiconductor memory device
US6208010B1 (en) 1985-09-25 2001-03-27 Hitachi, Ltd. Semiconductor memory device
US6740958B2 (en) 1985-09-25 2004-05-25 Renesas Technology Corp. Semiconductor memory device
JP2011210362A (en) * 1995-05-05 2011-10-20 Texas Instruments Inc <Ti> Row decoder with level translator

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995011492A1 (en) * 1993-10-21 1995-04-27 Omron Corporation Character input system capable of inputting characters in two ways and ocr used therefor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5354987A (en) * 1976-10-29 1978-05-18 Hitachi Ltd Complementary type mos semiconductor memory
JPS54127291A (en) * 1978-03-27 1979-10-03 Cho Lsi Gijutsu Kenkyu Kumiai Mos semiconductor ic device
JPS5554958U (en) * 1978-10-09 1980-04-14

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5354987A (en) * 1976-10-29 1978-05-18 Hitachi Ltd Complementary type mos semiconductor memory
JPS54127291A (en) * 1978-03-27 1979-10-03 Cho Lsi Gijutsu Kenkyu Kumiai Mos semiconductor ic device
JPS5554958U (en) * 1978-10-09 1980-04-14

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60136253A (en) * 1983-12-24 1985-07-19 Toshiba Corp C-mos semiconductor memory
US4646425A (en) * 1984-12-10 1987-03-03 Solid State Scientific, Inc. Method for making a self-aligned CMOS EPROM wherein the EPROM floating gate and CMOS gates are made from one polysilicon layer
JP2754487B2 (en) * 1985-02-12 1998-05-20 エスジェーエス―トムソン ミクロエレクトロニクス ソシエテ アノニム Integrated circuit type dynamic memory
JPS61229352A (en) * 1985-02-12 1986-10-13 エスジェーエス―トムソン　ミクロエレクトロニクス　ソシエテ　アノニム Ic type dynamic memory and manufacture thereof
JPS6251252A (en) * 1985-08-30 1987-03-05 Toshiba Corp Random access memory
JPS6251251A (en) * 1985-08-30 1987-03-05 Toshiba Corp Static type random access memory
US6208010B1 (en) 1985-09-25 2001-03-27 Hitachi, Ltd. Semiconductor memory device
US6740958B2 (en) 1985-09-25 2004-05-25 Renesas Technology Corp. Semiconductor memory device
US6864559B2 (en) 1985-09-25 2005-03-08 Renesas Technology Corp. Semiconductor memory device
JPH01109762A (en) * 1987-10-22 1989-04-26 Oki Electric Ind Co Ltd Semiconductor memory
JPH01253264A (en) * 1988-03-31 1989-10-09 Sharp Corp Semiconductor integrated circuit
JPH0267759A (en) * 1988-09-01 1990-03-07 Nec Corp Semiconductor memory device
JPH03232272A (en) * 1990-02-07 1991-10-16 Mitsubishi Electric Corp Semiconductor memory device
JP2011210362A (en) * 1995-05-05 2011-10-20 Texas Instruments Inc <Ti> Row decoder with level translator

Also Published As

Publication number Publication date
JPH0150114B2 (en) 1989-10-27

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