JPS5658255A - Mos type semiconductor memory device - Google Patents

Mos type semiconductor memory device

Info

Publication number
JPS5658255A
JPS5658255A JP13280979A JP13280979A JPS5658255A JP S5658255 A JPS5658255 A JP S5658255A JP 13280979 A JP13280979 A JP 13280979A JP 13280979 A JP13280979 A JP 13280979A JP S5658255 A JPS5658255 A JP S5658255A
Authority
JP
Japan
Prior art keywords
film
memory capacity
substrate
impurities
regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13280979A
Other versions
JPS6410948B2 (en
Inventor
Masayoshi Ino
Original Assignee
Oki Electric Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Ind Co Ltd filed Critical Oki Electric Ind Co Ltd
Priority to JP54132809A priority Critical patent/JPS6410948B2/ja
Publication of JPS5658255A publication Critical patent/JPS5658255A/en
Publication of JPS6410948B2 publication Critical patent/JPS6410948B2/ja
Application status is Expired legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10805Dynamic random access memory structures with one-transistor one-capacitor memory cells

Abstract

PURPOSE:To obtain a larger memory capacity along with smaller dimensions as a whole by shaping the memory capacity section formed on a semiconductor substrate three dimensional in the construction. CONSTITUTION:A thin dielectric insulator film 3 is applied on an active layer of the semiconductor substrate 1 and an opening is etched in the center thereof to form an impurities diffused region 8 within the substrate 1 exposed. An opening is provided through a dielectric insulator film 3' extended into one of the film 3 to form impurities diffused regions 5 and 5' and both regions are entirely wrapped with a thick oxide film 2. The first impurities containing polycrystal line Si body 6 composing a memory capacity section is so constructed to have a pillarlike part on the undersurface thereof and is fixed with the bottom of the pillarlike body bearing on the region 8 while the outside thereof is wrapped with the film 3. In this manner, the polycrystal Si body is integrated with the film 3 on the substrate 1. Subsequently, the Si body 6 is surrounded by a memory capacity section comprising the second polycrystal line Si 7 containing impurities similarly and a polycrystal line Si gate electrode 7' is applied on the substrate 1 between the regions 5 and 5' through a transmission gate insulator film 3' comprising the film 3' previously provided.
JP54132809A 1979-10-17 1979-10-17 Expired JPS6410948B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54132809A JPS6410948B2 (en) 1979-10-17 1979-10-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54132809A JPS6410948B2 (en) 1979-10-17 1979-10-17

Publications (2)

Publication Number Publication Date
JPS5658255A true JPS5658255A (en) 1981-05-21
JPS6410948B2 JPS6410948B2 (en) 1989-02-22

Family

ID=15090079

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54132809A Expired JPS6410948B2 (en) 1979-10-17 1979-10-17

Country Status (1)

Country Link
JP (1) JPS6410948B2 (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61208255A (en) * 1985-03-13 1986-09-16 Toshiba Corp Semiconductor memory device
EP0194682A2 (en) * 1985-03-13 1986-09-17 Kabushiki Kaisha Toshiba Semiconductor memory device
JPS63208263A (en) * 1987-02-25 1988-08-29 Toshiba Corp Semiconductor device
US4974040A (en) * 1987-06-17 1990-11-27 Fujitsu Limited Dynamic random access memory device and method of producing same
JPH03270162A (en) * 1990-03-20 1991-12-02 Toshiba Corp Semiconductor device and its manufacture
US5071783A (en) * 1987-06-17 1991-12-10 Fujitsu Limited Method of producing a dynamic random access memory device
US5650647A (en) * 1987-06-17 1997-07-22 Fujitsu Limited Dynamic random access memory device and method of producing same
US5939746A (en) * 1995-12-14 1999-08-17 Nec Corporation Semiconductor memory device and manufacturing method of the same
US6046468A (en) * 1987-11-25 2000-04-04 Fujitsu Limited Dynamic random access memory device and method for producing the same
US6617205B1 (en) 1995-11-20 2003-09-09 Hitachi, Ltd. Semiconductor storage device and process for manufacturing the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52104088A (en) * 1976-02-27 1977-09-01 Hitachi Ltd Mis capacitor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52104088A (en) * 1976-02-27 1977-09-01 Hitachi Ltd Mis capacitor

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0194682A2 (en) * 1985-03-13 1986-09-17 Kabushiki Kaisha Toshiba Semiconductor memory device
JPS61208255A (en) * 1985-03-13 1986-09-16 Toshiba Corp Semiconductor memory device
JPS63208263A (en) * 1987-02-25 1988-08-29 Toshiba Corp Semiconductor device
US5071783A (en) * 1987-06-17 1991-12-10 Fujitsu Limited Method of producing a dynamic random access memory device
US4974040A (en) * 1987-06-17 1990-11-27 Fujitsu Limited Dynamic random access memory device and method of producing same
US5021357A (en) * 1987-06-17 1991-06-04 Fujitsu Limited Method of making a dram cell with stacked capacitor
US5650647A (en) * 1987-06-17 1997-07-22 Fujitsu Limited Dynamic random access memory device and method of producing same
US6046468A (en) * 1987-11-25 2000-04-04 Fujitsu Limited Dynamic random access memory device and method for producing the same
US6114721A (en) * 1987-11-25 2000-09-05 Fujitsu Limited Dynamic random access memory device and method for producing the same
JPH03270162A (en) * 1990-03-20 1991-12-02 Toshiba Corp Semiconductor device and its manufacture
US7196368B2 (en) 1995-11-20 2007-03-27 Renesas Technology Corp. Semiconductor memory arrangements with crown shaped capacitor arrangements trenched in interlayer dielectric film
US6798005B2 (en) 1995-11-20 2004-09-28 Hitachi, Ltd. Semiconductor memory device having large storage capacity and minimal step height between memory cell and peripheral circuits
US6617205B1 (en) 1995-11-20 2003-09-09 Hitachi, Ltd. Semiconductor storage device and process for manufacturing the same
US6791134B2 (en) 1995-11-20 2004-09-14 Hitachi, Ltd. Semiconductor memory device and manufacturing method thereof
US5953609A (en) * 1995-12-14 1999-09-14 Nec Corporation Method of manufacturing a semiconductor memory device
US5939746A (en) * 1995-12-14 1999-08-17 Nec Corporation Semiconductor memory device and manufacturing method of the same

Also Published As

Publication number Publication date
JPS6410948B2 (en) 1989-02-22

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