JPS6410948B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a MOS type semiconductor memory device having a memory cell having a small area and a large capacitance.

A conventional MOS type semiconductor memory device is shown in FIGS. 1a to 1c, taking a 1Tr/1C cell type memory cell section as an example. FIG. 1a is a plan view thereof, and FIG. 1b is a sectional view taken along line A-A' in FIG. 1a. FIG. 1c is a memory cell circuit diagram, which will be explained here using a one-layer polysilicon structure.

In FIG. 1a, the hatched area S ₁ is the two-dimensional area of the storage capacitor part of the memory cell, and 1
2 is the substrate (semiconductor substrate), 2 is a thick oxide film on the non-active region, 3 and 3' are thin dielectric insulating films in the storage capacitor section and the transfer gate section, 4 is the storage capacitor section connected to the power supply potential V _DD and the The polysilicon layer 4' serves as two electrodes, and the polysilicon layer 4' is the transfer gate portion connected to the word line W (FIG. 1c).

Further, 5 is an impurity diffusion layer connected to the bit line B (FIG. 1c), and 5' is an impurity diffusion layer connected to the first electrode of the capacitor section. Note that the final structure resulting from subsequent processes is the same as before, and will therefore be omitted.

By the way, in the structure of the 1Tr/1C cell type memory cell portion of such a conventional MOS type semiconductor memory device, _C =
S ₁ ε/t (ε is the dielectric constant, t is the thickness of the film). The storage capacitance between the impurity diffusion layer 5' and the polysilicon 4 is determined.

Therefore, when achieving high-density VLSI, the two-dimensional area _S1 of the storage capacity section inevitably decreases, that is, the storage capacity decreases. Furthermore, even if the dielectric insulating films 3, 3' are intended to be made thinner, the reduction in dielectric strength voltage of the dielectric insulating films 3, 3' is a limitation, resulting in a decrease in yield.

As described above, in the conventional structure, since the increase in density and the reduction in memory cell capacity are integrated, there is a drawback that the electric signal level decreases and the structure becomes susceptible to α-ray damage.

The present invention was made in order to eliminate the above-mentioned conventional drawbacks, and provides a MOS type semiconductor memory device in which a structure capable of obtaining a large capacitance even in a two-dimensional small area can be applied to the storage capacitance portion of a memory cell. The purpose is to provide.

Embodiments of the MOS type semiconductor memory device of the present invention will be described below with reference to the drawings. Figure 2 a~
FIG. 2c shows an example of the second embodiment.
Figure a is a plan view, Figure 2 b is B- in Figure 2 a.
FIG. 2c, a sectional view taken along line B', shows a memory cell circuit. This figure 2 a to figure 2 c
The same parts in FIGS. 1a to 1c will be described with the same reference numerals.

A thick oxide film 2 is formed on the non-active area of the substrate 1, and a thick oxide film 2 is formed on the active area of the substrate 1.
A thin dielectric insulating film 3 of the memory cell storage capacitor portion is formed, and this dielectric insulating film 3 also continuously covers the entire surface of the first polycrystalline silicon body 6.
The first polycrystalline silicon body 6 is located on the active region of the substrate 1, partially in contact with the substrate 1, and extends above the substrate 1 in the form of a flat plate with a two-dimensional area _S3 . It has a shaped region and a columnar region extending from approximately the center of this flat region to which the substrate 1 is connected. Further, this first polycrystalline silicon body 6 contains impurities.

A shallow impurity diffusion layer 8 is formed in the substrate 1 from this first polycrystalline silicon body 6 at its connection portion. Then, the entire surface of the first polycrystalline silicon body 6 is covered with the dielectric insulating film 3 described above so as to leave a gap below the eaves, and then the dielectric insulating film 3 is formed on the entire surface of the dielectric insulating film 3. An integral second polycrystalline silicon body 7 covers the polycrystalline silicon body 6 and the surface of the substrate 1 so as to cover the first polycrystalline silicon body 6 continuously from above and below. This second polycrystalline silicon body 7 fills the gap between the bottom surface and the substrate 1 at the bottom surface of the flat plate-like region of the first polycrystalline silicon body 6 . Further, this second polycrystalline silicon body 7 contains impurities and corresponds to the polysilicon 4 in FIGS. 1a to 1c.

Furthermore, simultaneously with the formation of the dielectric insulating film 3, a thin dielectric insulating film 3' is formed at the transfer gate, and on this dielectric insulating film 3', the second polycrystalline silicon body 7 is formed. At the same time, a second polycrystalline silicon body 7' is formed. This second polycrystalline silicon body 7' serves as a gate electrode of a transfer transistor, and corresponds to polysilicon 4' in FIGS. 1a to 1c.

The two-dimensional area S ₂ of the memory cell storage capacitor section is the first
Two-dimensional area S ₁ of the memory cell storage capacitor in figure a
This corresponds to Note that S ₃ in FIG. 2a is the upper extension area of the first polycrystalline silicon body 6, and R indicates the contact area between the substrate 1 and the first polycrystalline silicon body 6.

As is clear from FIGS. 2a to 2c, in this embodiment, the area corresponding to the two-dimensional area S ₁ of the conventional memory cell storage capacitor section is (S ₂ +2S ₃ ).
Since it is S ₃ S ₂ S ₁ , there is an advantage that nearly three times the storage capacity can be obtained with the same two-dimensional area.

Figures 3a to 3c show a second embodiment of the invention, with Figure 3a being a plan view and Figure 3b being a top view.
3 is a sectional view taken along the line CC' of FIG. 3a, and FIG. 3c is a memory cell circuit diagram. The second embodiment shown in FIGS. 3a to 3c is the conventional 2nd embodiment.
The cell structure of the present invention is applied to a layered polysilicon structure cell.

In this Fig. 3 a to Fig. 3 c, Fig. 2 a to Fig. 3 c
The same parts as in FIG. 2c will be given the same reference numerals and their explanation will be omitted, and the parts different from those in FIGS. 2a to 2c will be mainly described. The second polycrystalline silicon body 7 contains impurities that are formed only in the storage capacitance portion of the memory cell, and the third polycrystalline silicon body 9 contains impurities and serves as a transfer transistor gate. This corresponds to the second polycrystalline silicon body 7' in FIGS. 2a and 2b. Other parts are the same as in FIGS. 2a to 2c.

In this case, the gate electrode of the peripheral transistor can be made of either the second or third polycrystalline silicon body. And 10 is the first capacity
This electrode corresponds to the impurity diffusion layer 5'.

Further, the dielectric insulating film 3' is an insulating film between the second polycrystalline silicon body 7 and the third polycrystalline silicon body 9, and the third polycrystalline silicon body 9 forming the transfer transistor and the substrate 1. A gate insulating film between the two is simultaneously formed.

As described above, if the present invention is applied to a memory cell having a conventional two-layer polysilicon structure, the two-dimensional area of the memory cell storage capacitor portion can be further reduced.

As described above, according to the MOS type semiconductor memory device of the present invention, a so-called mushroom-shaped first polycrystalline silicon region consisting of a flat plate region and a columnar region is provided on a semiconductor substrate, and the first polycrystalline silicon region is provided on a semiconductor substrate. After continuously covering the entire surface of the region and the surface of the substrate with a dielectric insulating film, the gap between the flat region of the first polycrystalline silicon region and the substrate is filled with the second polycrystalline silicon region. Since the capacitance is configured such that the second polycrystalline silicon region continuously covers the first polycrystalline silicon region from above and below, the surface portion of the substrate and the side surface of the columnar region of the first polycrystalline silicon region are formed. a capacitance can be formed at a lower surface portion of the flat region of the first polycrystalline silicon region, and a side surface portion and an upper surface portion of the flat region of the first polycrystalline silicon region;
It has the advantage of being able to construct a memory cell with approximately three times the larger storage capacity in the same area as the conventional one, and can be effectively used in future VLSI-level 64K-bit, 256K-bit memories or higher. Moreover, according to the present invention, the above-mentioned large capacity can be easily obtained without stacking the same configuration or connecting in parallel. Further, according to the present invention, by actively utilizing a continuous insulating film made of the same material that is easily formed on the first polycrystalline silicon region and the surface of the substrate by thermal oxidation etc. as the dielectric of the capacitor. Even though the capacitor has a large three-dimensional structure, the dielectric of the capacitor can be easily formed, and there is no need to repeatedly manufacture the dielectric.

[Brief explanation of drawings]

Figure 1a shows a conventional MOS semiconductor memory device.
A plan view of a 1Tr/1C cell type memory cell section, FIG. 1b is a cross-sectional view taken along line A-A' in FIG. 1a, and FIG. 1c is a plan view of the memory cell in FIG. 1a. FIG. 2a is a plan view of a 1Tr/1C cell type memory cell circuit according to an embodiment of the semiconductor memory device of the present invention, and FIG. 2b is a diagram of the memory cell circuit shown in FIG.
A sectional view taken along line B', FIG. 2c is a memory cell circuit diagram of the memory cell portion of FIG. 2a, and FIG. 3a is a second embodiment of the MOS type semiconductor memory device of the present invention. A plan view of the memory cell part of the 1Tr/1C cell type in the example, FIG. 3b is a cross-sectional view taken along the line C-C' in FIG. 3a, and FIG. FIG. 3 is a memory cell circuit diagram of a memory cell section. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Oxide film, 3, 3'... Dielectric insulating film, 5, 5'... Impurity diffusion layer, 6... First polycrystalline silicon body, 7, 7'... Second polycrystalline silicon body ,
8... Diffusion layer, 9... Third polycrystalline silicon body, S ₂ ...
Secondary area of memory cell storage capacitor section, S ₃ ...spread area, R... contact area.

Claims (1)

[Claims] 1. Having a gate electrode coupled to a word line, and a drain electrode and a source electrode coupled to a bit line.
A MOS semiconductor memory formed on a single semiconductor substrate, which is formed on a single semiconductor substrate, and includes a MOS transistor and a capacitor having a first electrode coupled to the source electrode of the MOS transistor and a second electrode coupled to a power supply potential. In the device, the capacitor includes the first electrode, which includes a flat region disposed above the semiconductor substrate and a columnar region extending from approximately the center of the flat region and in contact with a diffusion layer of the semiconductor substrate. a first polycrystalline silicon region containing an impurity that acts as a polycrystalline silicon region; and a thin dielectric insulating film made of the same material that continuously covers the entire surface of the planar region and the columnar region and a selected surface of the semiconductor substrate. and a second polycrystalline silicon region containing an impurity as the second electrode, which fills the gap between the lower surface and the semiconductor substrate and covers almost the entire surface of the dielectric insulating film on the lower surface of the flat plate-shaped region. A MOS type semiconductor memory device comprising: