JPS6065559A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To obtain the desired capacitor capacity by burying the electrodes of the capacitor via an interval at an insulating film in a groove bored on an Si substrate, thereby increasing the area of the electrodes without increasing the area of the surface. CONSTITUTION:A lower resistance layer 8 of the same conductive type as an Si substrate is formed on the side wall of a groove 17 digged on the substrate 10, the electrodes 19 of the capacitor are buried in the groove, a plate 22 is further buried through an insulating film 15 to form a memory cell. The capacity is formed on a capacity insulating film 18, which is interposed between a capacitor electrode 19 and a plate 8, and a capacitor insulating film 15 interposed between the capacitor electrode 19 and the plate 22. When N type is used for the substrate and a P type epitaxial layer 21 is formed on the surface, the isolated plates 8 are all connected to the substrate 10 of N type. Since this Si substrate can be disposed at the ground potential, the influence of the remaining sound voltage is small.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor memory, and particularly to a one-transistor type dynamic MOS memory that achieves a large capacity without increasing the planar area and is suitable for large scale.

[Background of the invention]

Since 1Kb dynamic random access memory (hereinafter abbreviated as dRAM) was released in the early 1970s, MOS dynamic memory has quadrupled in size in three years. However, since the package into which this memory chip is placed has a limit on the size of the cavity into which the chip can be placed, even if the size of the memory chip becomes four times larger, it will only increase by about 1.4 times at most. . (
Furthermore, since dRAM is used in large quantities, it is necessary to suppress the increase in chip size in terms of cost. ) Therefore, the memory cell area for one pit, which corresponds to one storage capacity, has been greatly reduced, and as the scale has increased four times, it has become smaller to about 1/3. Capacitor capacitance C is expressed as C=εA/T+ (where ε: dielectric constant of insulating film, A: capacitor area, Tl: insulating film thickness), so if area A becomes 1/3, then 6
As long as and T are the same, C is also 1/3. The signal amount S as the storage capacity is proportional to the stored charge amount Q, and since Q is the product of C and the storage voltage ■8,
As N decreases, Qa decreases in proportion, and the signal S decreases accordingly.

If the noise voltage is N, the signal-to-noise ratio (S/N ratio) decreases as S decreases, which poses a serious problem in circuit operation. Therefore, normally, the decrease in A is compensated for by the decrease in TI.As dRAM becomes larger in size from 4Kb to 16Kb to 64Kb, the standard thickness TI of a 5ioz film as an insulating film becomes 1000m* It has become smaller to 75Ωm and 50Ωm.

Furthermore, heavy metals (U, T) contained in packaging, etc.
It has been confirmed that the α particles emitted from the Si substrate generate a charge of about 200 fC in the Si substrate, and this becomes noise.
It has become difficult to reduce the temperature to below 0 fC.

Therefore, attempts have been made to further accelerate the thinning of the insulating film, and in this case, dielectric breakdown of the insulating film has become a problem. The dielectric strength electric field of 5102 film is maximum 107V/c
Therefore, the 5jCh film of lQnm is almost permanently destroyed or deteriorated by the application of IOV. Further, even if permanent damage does not occur, using it near the maximum electric field is a big problem in terms of long-term reliability.

[Purpose of the invention]

The purpose of the present invention is to deal with the problems of disturbance caused by α particles, deterioration of the S/N ratio, and dielectric breakdown voltage that occur with the miniaturization of memory cells, and to maintain the capacitor area A even when the memory cells are miniaturized. Or, to provide a method that can increase it.

[Summary of the invention]

The gist of the present invention is to use the side wall portion of a groove dug in the Sl substrate as a first plate, to use an electrode buried in this groove with an insulating film flattened as a capacitor electrode, and to further form an insulating film on the capacitor electrode. By forming the second plate embedded through the electrode, the electrode area can be increased without increasing the planar area. With this, a desired capacitor capacity can be obtained.

[Embodiments of the invention]

FIG. 1 shows a cross-sectional view of a conventional memory cell.

Hereinafter, for convenience of explanation, an example using an n-channel type transistor will be shown. In order to make an n-channel type, generally the conductivity types of the Si substrate and the diffusion layer should be reversed to those for the n-channel type.

The conventional memory cell shown in FIG.
Field S io of about thickness, film 11 S i s N
The so-called 1,0CO8 using 4 as a thermal oxidation mask
selectively deposited by method. After this, a plate 8 typified by polycrystalline Si (hereinafter abbreviated as polySi) doped with phosphorus or As is selectively deposited, and (D polyS
The first interlayer oxide film 13 is formed by oxidizing the plate 8 of i. After that, the word line 4, which is typically made of polysi, Mo silicide, or a factory metal (MO-?W, etc.), is deposited, and phosphorus or As is ion-implanted. An Nl diffusion layer 15 is formed in the active region where the active region is not present, and becomes the source and drain of the switch transistor 2. After this, P'SG (phosoho
-silicate glass) from 200 to 1100
A second interlayer insulating film 14 is deposited to a thickness of 0n, and a contact hole 9 is formed in a portion where the bit line 3, represented by the A7 electrode, is connected to the diffusion layer 15, thereby selectively connecting the bit line 3. to adhere to.

In the above explanation, for convenience, the insulating film under the plate 8 and the word line 4 (that is, the gate of the switch transistor 2) is the same 5i02 film 12, but the main purpose is to increase the capacitor value CI+ of the memory cell. The insulating film under 8 may be an insulating film having a one-layer to three-layer structure using either or both of 5jOz and 5isN4.

The present invention aims to compensate for the drawbacks of the above conventional structure and increase Cs without increasing the planar area.

The present invention will be described in detail below using Examples.

First, FIG. 2 shows a sectional view of one embodiment of the present invention. There are 8 differences compared to the conventional memory cell shown in Figure 1.
A low resistance layer of the same conductivity type as the Si substrate is provided on the side wall of the groove 17 dug into the i-substrate 10, and this is used as the first plate 8.
The electrode embedded in this groove is used as a capacitor electrode 19, and the electrode embedded in this via an insulating film 25 is used as a second plate 22.

The manufacturing process of the semiconductor memory according to the present invention will be described in detail below. 1. As shown in FIG. 3, after forming a field oxide film 11 on a p-type, 1-20Ω Si substrate 10 by the LOCO8 method described above, a gas containing F or Ct, such as SF6 or C
Grooves 17 of a predetermined size are formed by parallel plate plasma etching using Ct4 or the like as a main component. Usually 1-5μm
Since a deep etching groove is to be formed, the pattern of the groove is first transferred to the CVD 5iOz film using an ordinary photoresist, and the groove 17 is formed using this CVD SiOz film as a mask. Thereafter, by a well-known diffusion method or the like, an n+ layer 8 having a conductivity of 1 Ω-m or less and having a conductivity type different from that of the Si substrate is formed on the side walls and the lower part of the groove to form the first plate 8. Thereafter, as shown in FIG. 4, a capacitor insulating film 18 typified by a single layer of 5iOz or 5jsN or a composite film thereof, or Tag's is deposited. This capacitor insulating film 1
A capacitor electrode connection hole 20 reaching the 81 substrate 10 is formed in a predetermined portion of the 81 substrate, and the pol
A y Si LD capacitor z pole 19 is attached to a predetermined portion so as to be connected to the Si substrate 1°.

In order to make the polysilicon 19 conductive, P and AS are added to it, and as a result, an n+ diffusion layer 15 is formed in the Si substrate lo. Further, a second capacitor insulating film 25 of the same type as the insulating film 18 is deposited, and a second plate 22 of polysI is further deposited.

Thereafter, as shown in FIG. 5, a part of the polySi 19 and 22 are oxidized by a dry or wet oxidation method at 800 to 1100 tl' to form a first interlayer insulating film 13 with a thickness of 100 to 200 nm, and a switch transistor is formed. A gate oxide film 12 with a thickness of 10 to 5 Qnm is formed on the portion where the gate 2 is to be formed, and a gate (word line 4) made of poly si, Mo silicide, Mo i W, etc. is deposited thereon. After that, AS etc. are implanted using the ion implantation method, and n
+ Form the diffusion layer 15.

Furthermore, a second interlayer insulating film 14 typified by CVDPSG is deposited to form a contact hole 9 to the n+ diffusion layer 15.
A bit line 3 represented by A and 7 is deposited.

By doing so, the capacitor consists of the capacitor insulating film 18 and the two electrodes sandwiching it, that is, the capacitor electrode 19, and the plate 8 and the second capacitor insulating film 25, that is, the two electrodes that are sandwiched therebetween, that is, the capacitor electrode 1.
9 and the second plate 22.

The plate 8 is an n+ layer 1, and the n+ layer is provided at a distance around the groove 17, so it is necessary to connect these layers.
As shown in FIG. 6, if an n-type Si substrate is used and a p-type epitaxial layer 21t is formed on the surface thereof, all of the separated plates 8 are connected to the n-type Si substrate 10. Since this Si substrate can be set to ground potential, the influence of noise voltage is also small. As for the manufacturing method, a Si substrate 10 on which an epitaxial layer 21 is laminated may be used instead of the S1 substrate of the previous embodiment described in FIGS. 3 to 5.

In the embodiments of the present invention described above, a switch transistor is formed on the Si substrate 10 or the epitaxial layer 21. FIG. 7 shows another embodiment of the present invention.

As already explained in the above embodiment, the capacitor insulating film 1
After depositing 8, a single crystal film 84 is formed, including a portion that will become the capacitor electrode 19 and the diffusion layer portion 15 in a later step.
0 I (abbreviation for Silicon QnJsulator) structure is formed. This is done by depositing a polycrystalline or amorphous (amo-rphous) Si film on the entire surface or a part of the surface, heating the entire surface or a part of the surface with a laser beam or a thermal heater, and melting it once. A single crystal layer 23 is grown on the insulating film while remaining in the same phase.

(Although not shown in FIG. 7, the SOI structure has a great advantage because it can easily be made into a single crystal by keeping a part of the film in contact with the 81 substrate 10.) Furthermore, the second capacitor insulator A film 25 is deposited, and a second layer of poly F9 i is deposited on top of the film 25.
Plate 22 is applied. This poly-Si is thermally oxidized to form a first interlayer insulating film 13.

Thereafter, an oxide film 12 and a gate 4 are deposited on the upper part of the SOI part 2, and an n1 layer is formed, one of which is used as a capacitor electrode 19, and the other is made into a diffusion layer 15 connected to the bit line 3. The subsequent steps are similar to those in the previous example. In this embodiment, since the switch transistor 2 is not on the 84 substrate 11, the substrate 11 can be of any conductive type. That is, if the Si substrate 10 is made of n-type, the Si substrate 10 itself becomes a plate even if the first plate 8 is not particularly provided.

Generally, in this dynamic memory, peripheral circuits with various functions are formed around the memory cells, so it is difficult to make the entire Si substrate 10 n-type, but in this case, it is sufficient to provide the first plate 8, It is sufficient to make only the memory cell portion n-type.

In the above embodiment, the present invention has been described in which the word ff54 is a continuous gate within the memory cell array, but the polysi transfer gate 4 of the switching transistor 2 within the memory cell may be formed continuously between memory cells. It is also possible to form them separately and connect them with the At word line 4 through a new contact hole. In this way, due to the reliability of the polycrystalline Si gate, which has a long track record, and the low resistance of the transistor, the switching time of the high-speed memory can be reduced.

Furthermore, as stated at the beginning, the present invention also provides an n-channel type M
Although the explanation has been made using an OS transistor, a p-channel type can be achieved by using impurities that reverse the conductivity types of all impurities. Phosphorus and As become B and At, B beam7. It may be replaced with AS, 8b, etc.

Grooves Although the grooves of the present invention are straight, the surface area becomes the capacitor surface, so the capacitance will be larger if there are corrugations. Although the upper surface pattern of the grooves is not shown, it is possible to increase the surface area by using a concave, convex, or ring-shaped tile rather than a simple one.

〔Effect of the invention〕

The present invention has been described above with reference to detailed embodiments, but in the case of a switch transistor formed on the substrate surface, the capacitor capacitance C11 is 5 to 10 times that of a conventional memory cell with the same plane area, and it is formed in the SOI layer. can increase Cs by 10 to 20 times. In some cases, the shape of the groove is not completely straight, but is somewhat rounded, and even if the designed shape is square, it will become circular because the resolution of phosphorography decreases in minute parts. In some cases,
Even in this case, the decrease in Cs remains at 10 to 20%.

Malfunction of dynamic memory due to alpha rays is caused by C6 being 10
Even if it increases by %, there are many places where it is changed by more than 1 digit, so %C8
An increase of more than 2 times does not necessarily increase the reliability of a memory of that size, but also makes it possible to realize an even larger memory.

Furthermore, due to the structure of the present invention, a large amount of electron-hole pairs generated in the Si substrate by α rays rarely flows directly into the capacitor electrode 19, and in particular, in the case of using SOI, they do not flow at all. It has the feature of being strong against alpha rays.

Furthermore, the memory cell of the present invention also has the effect of increasing memory capacity without requiring a reduction in insulating film thickness even when miniaturized.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view explaining a conventional memory cell, FIG. 2 is a lli side view of an embodiment of the present invention, and FIGS. 3 to 5 are cross-sectional views showing the manufacturing process of an embodiment of the present invention in order of process. , FIG. 6 is a cross-sectional view showing the first step of another embodiment of the present invention, and FIG. 7 is a cross-sectional view of another embodiment of the plane of the present invention. 3...Bit line, 4...Word line, 5...Sense amplifier, 6...Survival capacitance, 7...Active area, 8...
・First plate, 9... contact hole, 10...S
i-substrate, 11... field oxide film, 12... gate oxide film, 13... first interlayer insulating film, 14... second
Interlayer insulating film, 15... Diffusion layer, 16... Capacitor region, 17... Binding, 18... Capacitor insulating film, 1
9... Capacitor electrode, 20... Capacitor electrode connection hole, 21... Epitaxial layer, 22... Second plate, 23... SOI part, 24... Transistor channel part, 25... 2nd capacitor disconnected Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 5 Figure Z Figure 7

Claims (1)

[Claims] An insulated gate field effect transistor is operated with a capacitor having an information storage part. A capacitor electrode formed through the capacitor electrode and electrically connected to the source or drain of the field effect transistor, and a second V-platform further deposited on the capacitor electrode with an insulating film interposed therebetween. A semiconductor memory characterized by having a capacity.