JPH0320906B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor devices, and more particularly to integrated circuits and the formation of transistors and electrical capacitors in semiconductor devices.

2. Description of the Related Art Integrated circuits formed on semiconductor substrates, particularly silicon semiconductor substrates, are becoming more highly integrated and larger in capacity, and various microfabrication techniques for semiconductor surfaces using photolithography have been developed. Under these circumstances, various efforts are being made to reduce the size of a semiconductor pellet on which an IC memory is mounted and to increase the capacity of the IC memory. In order to achieve these objectives, research is progressing on the development of information storage methods from the circuit side and various information storage methods from manufacturing materials.Currently, in IC memories such as Dynamic RAN, information storage (hereinafter referred to as cell)
It is considered that the most suitable configuration for the above purpose is to configure the circuit with one transistor and one information storage capacitor section. In the information storage system of this method, the area of the information storage capacitor portion of the cell section occupies most of the semiconductor pellet. For this reason, in order to reduce the pellet area of the dynamic RAN or increase the capacity of the RAN using this method, reducing the area of the information storage capacity section is the most effective means. However, reducing the area of this information storage capacitor and reducing the value of the equivalent capacitance will reduce the amount of small information signals stored in this capacitor. Sensing on the circuit becomes difficult.

The present invention improves this point and enables the area occupied by the cell section to be reduced without reducing the capacity of the cell section, and is suitable for increasing the capacity of information storage and reducing pellet size. The present invention aims to provide a semiconductor device for use in

The present invention is characterized in that a single-crystal semiconductor layer is provided on an insulating film provided on one main surface of a semiconductor substrate, a source, a drain, and a channel portion of an insulated gate field effect transistor are provided on this semiconductor layer, and the insulated gate One of the source and drain regions of the field effect transistor is electrically connected to a first region of one main surface of the semiconductor substrate, and the other region and a second region of one main surface of the semiconductor substrate are connected to this region. There is provided a semiconductor device in which a capacitive portion is formed by an electrode that is connected and provided on the other region via an insulating film.
Preferably, at least a portion of the source or drain region used as the electrode of the capacitor portion is formed of a polycrystalline semiconductor layer or an amorphous semiconductor layer. For this purpose, in the present invention, one transistor of the cell section and a storage region of the information storage section are formed on a single crystal semiconductor thin film formed on the surface of an insulating material on a semiconductor substrate, and a polycrystalline semiconductor thin film formed on the surface of an insulating material on a semiconductor substrate, respectively. Alternatively, it is formed on a single crystal semiconductor thin film. In this way, the information storage capacity section can be formed into a vertical structure in which the two halves are stacked one on top of the other, and the area of the information storage capacity section can be effectively utilized.

An embodiment of the invention below will be described in detail with reference to the drawings. In the following, only the case where an N-channel type MOS field effect transistor is formed on a P-type semiconductor substrate to form a cell part will be explained.
It should be mentioned before that the method is exactly the same when forming a MOS field effect transistor.

FIG. 1 is a sectional view of a cell portion showing one embodiment of the present invention. In the drawing, for example, the specific resistance is
A thick silicon oxide film 1 is formed on the surface of a P-type silicon substrate 101 with a resistance of 0.1 to 100 Ω・cm by high-temperature thermal oxidation.
02 is selectively formed. In this way, next, the MOS field effect transistor in the cell section uses the single crystal silicon films 103 and 104 containing effective impurities formed on the silicon oxide film as the source side and drain side, respectively, and similarly the single crystal silicon film 105 as the source side and the drain side, respectively. A part of the surface of
06 (for example, a silicon oxide film) and polycrystalline or amorphous silicon containing effective impurities, or a pure metal 107 such as aluminum, are formed to serve as a gate film and a gate electrode of a MOS field effect transistor, respectively. Next, the information storage capacitor section includes a first thin insulating film 108 formed on the surface of the silicon substrate other than the thick silicon oxide film 102;
Drain region 10 of MOS field effect transistor
A second thin insulating material 10 formed on the surface of 4
9 (for example, a silicon nitride film) are both dielectric materials, a capacitor electrode 110 formed on the surface of the silicon substrate 101 and the surface of the second thin insulating material 109 is used as one electrode, and a drain formed of the single crystal silicon film is used as one electrode. The side electrode 104 is formed as a counter electrode. In the above structure, the gate electrode 107 of the MOS field effect transistor is formed to partially cover the thick silicon-coated oxide film 111 formed on the source side region 103 and the capacitor electrode 110. In this way, the main cell structure is completed. In the structure of this embodiment, the silicon substrate 10
The thick silicon oxide film 102 formed on the first insulating film 108 and the single crystal silicon film on the first thin insulating film 108 are initially formed by forming a polysilicon or amorphous silicon film on the thick silicon oxide film and the first thin insulating film. After forming the silicon film, the silicon film is laser annealed using a laser beam with a wavelength of 0.4 to 2 μm emitted from argon, YAG, ruby, or the like.
Crystal growth of the polysilicon or amorphous silicon film by laser annealing proceeds laterally using the exposed portion 112 on the surface of the silicon substrate 101 as a crystal seed, and grows the polysilicon film or amorphous silicon film over a width of about 50 to 100 μm in the lateral direction. is converted into a single crystal silicon film. Further, in the embodiment of the present invention, the same effect can be obtained even if a portion of the drain side 104, that is, a region remote from the channel region of the MOS field effect transistor, is a polysilicon film or an amorphous silicon film.

In the embodiment of the present invention, a case has been described in which the gate electrode 107 of the MOS field effect transistor covers a part of the capacitor electrode 110 with a thick silicon oxide film interposed therebetween.
07. When the capacitor electrodes 110 are formed of the same metal layer and are electrically isolated from each other, and when the capacitor electrodes 110 cover a part of the gate electrode 107 with a thick silicon oxide film, A similar effect can be obtained even when the film is formed in a state where it is interposed and covered.

As described above, in the present invention, since the information storage capacitor section of the cell section is formed in a vertically folded configuration, it is possible to form a capacity approximately twice as large as that of the conventional device within a unit plane. As a result, the area of the information storage capacity can be reduced to the level of the conventional one.

[Brief explanation of the drawing]

FIG. 1 shows a cross-sectional structural diagram of an embodiment of the present invention. In the figure, 101...silicon substrate, 1
02...Thick silicon oxide film, 103...MOS
Source side region of field transistor, 104...
Drain side region of MOS field effect transistor,
105... Single crystal silicon film, 106... Gate film, 107... Gate electrode, 108... First thin insulating film, 109... Second thin insulating film, 110
. . . capacitor electrode, 111 . . . silicon-covered oxide film, 112 . . . exposed portion of silicon substrate surface.

Claims (1)

[Claims] 1. A single crystal semiconductor layer is provided on an insulating film having an opening provided on one main surface of a semiconductor substrate, and the semiconductor layer is in contact with the semiconductor substrate through the opening. In addition, the semiconductor layer above the opening includes a source of an insulated gate field effect transistor;
One of the drains is provided, the other of the channel part and the source or drain of the insulated gate field effect transistor is provided in the semiconductor layer above the insulating film, and the other of the source or drain region is provided as a capacitor part. A semiconductor device characterized by having an electrode. 2. Claim 1, characterized in that at least a part of the source or drain region used as the electrode of the capacitive part is composed of a polycrystalline semiconductor layer.
1. Semiconductor device described in Section 1. 3. Claim 1, characterized in that at least a part of the source or drain region used as the electrode of the capacitive part is composed of an amorphous semiconductor layer.
1. Semiconductor device described in Section 1.