JPS63226955A - Manufacture of capacitive element - Google Patents

Abstract

PURPOSE:To obtain a manufacturing method of a capacitive element suitable for a highly integrated semiconductor device by a method wherein a thermal oxide film of a single-crystal semiconductor grown by a selective epitaxial growth method is used for a capacitive insulating film so that the breakdown strength of the capacitive insulating film can be enhanced. CONSTITUTION:An insulating film 15 is formed on a single-crystal semiconductor substrate 11; a hole, for a seed, which reaches the single-crystal semiconductor substrate 11 is made at a part of the insulating film 15p a single-crystal semiconductor 16 is epitaxially grown selectively in such a way that it covers the inside of the hole for the seed and the circumference of the hole for the seed on the insulating film 15. The grown single-crystal semiconductor layer 16 is used as an electrode, on one side, of a capacitive element; a capacitive insulating film 17 is formed on the electrode; an electrode 18; on the other side, of the capacitive element is formed on the capacitive insulating film 17. During this process, charge-storage single-crystal silicon 16 is oxidized thermally and the capacitive insulating film 17 is formed. After that, e.g., a second interlayer insulating film 19 is grown; after that, a contact hole is made at a part of a diffusion layer 12 by a photoresist process; a bit line 20 is wired; a memory cell is formed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a capacitive element formed on a single crystal semiconductor substrate,
In particular, the present invention relates to a method of manufacturing a capacitive element suitable for highly integrated semiconductor devices.

[Conventional technology]

Semiconductor memory cells that store binary information in the form of electrical charges are
Because the cell area is small, it is excellent as a memory cell for highly integrated, large-capacity memories. In particular, a memory cell consisting of one transistor and one capacitive element (
The ITIC cell (hereinafter referred to as an ITIC cell) has a small number of components and a small cell area, so it has become the mainstream today as a memory cell for highly integrated and large capacity memories.

By the way, as the size of memory cells decreases due to higher integration of memories, the area occupied by capacitive elements on the substrate in the ITIC cell structure is decreasing. Therefore, there are problems in that the storage charge capacity is reduced, the resistance to alpha rays is deteriorated, and the sensitivity of the sense amplifier is also deteriorated.

As a method to solve this problem and reduce the area occupied on the substrate of the capacitive element without reducing the storage charge capacity, we have developed a polycrystalline semiconductor electrode that is electrically connected to the source or drain region of the switching transistor. A polycrystalline semiconductor (
A method of forming a capacitive element (stack capacitor) between the cell plate electrode and the cell plate electrode is conventionally known. For example, the Proceedings of the International Solid State Circuit Conference (InternationalSol
id 5tate C1rcuits Conference
nce) J, 1985, pp. 250-251.
AM with 3-Dimensional Stac
There is a paper published under the title ked Capacitor Cells) J.

This paper shows a cross-sectional view of a stacked capacitor type ITIC cell, as shown in FIG. In this cell, a diffusion layer 12.12' and an element isolation oxide film 14 are formed on a silicon substrate 11, a word line 13 is provided on these through a first interlayer insulating film 15, and a diffusion layer 12' is formed on the insulating film 15. A charge storage polysilicon electrode 26 is provided by opening up to the hole, and a capacitor insulating film 17, a cell plate electrode 18 . A second interlayer insulating film 19 is laminated, and a hole is further opened up to the diffusion layer 12 to provide a bit line 2°.

In FIG. 2, charge storage polysilicon electrode 26 is electrically connected to diffusion layer 12. In FIG.

This charge storage polysilicon electrode 26 is thermally oxidized to form a capacitor insulating film 17. This capacitive element is formed between the cell plate electrode 18 and the charge storage polysilicon electrode 26.

[Problem that the invention seeks to solve]

Particularly, in the stack capacitor according to the prior art, as shown in FIG.
was a thermally oxidized film of the charge storage polysilicon electrode 26.

The surface smoothness of polysilicon is inferior to that of single crystal silicon, and the surface orientation is not constant. As a result, the withstand voltage of the capacitive insulating film 17 is low, making it difficult to make the film thin, and it is difficult to maintain a large capacitance.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a capacitor element that can eliminate such drawbacks and increase the withstand voltage of a capacitor insulating film, and is suitable for highly integrated semiconductor devices.

[Means for solving problems]

The structure of the capacitive element manufacturing method of the present invention is to form an insulating film on a single-crystal semiconductor substrate, form a sheet hole in a part of this insulating film reaching the single-crystal semiconductor, and selectively epitaxially growing the single crystal semiconductor so as to cover the periphery of the sheet hole on the insulating film, using the grown single crystal semiconductor layer as one electrode of a capacitive element, and forming a capacitive insulating film on this electrode; The method is characterized in that the other electrode of the capacitive element is formed on this capacitive insulating film.

[Effect]

According to the configuration of the present invention, it becomes possible to use a thermally oxidized film of a single crystal semiconductor grown by selective epitaxial growth as a capacitive insulating film, so that the surface is smooth and the plane orientation is constant, and the capacitive insulating film is A capacitive element with increased breakdown voltage can be obtained.

〔Example〕

FIGS. 1(a) to 1(d) are schematic cross-sectional views of an ITIC cell film using a capacitive element formed according to an embodiment of the present invention.

First, in FIG. 1(a), a diffusion layer 12, a word line 13, and an element isolation oxide film 14 are formed on a silicon substrate 11 by a normal MO3FET manufacturing process, and a first interlayer insulation [
form 15. After patterning the photoresist, a part of the first interlayer insulating film 15 is etched to form the diffusion layer 1.
Expose part of 2.

Next, in FIG. 1(b), a charge storage single crystal silicon 16 is grown by selective epitaxial growth using a portion of the exposed diffusion layer 12 as a sheet. This f& photoresist is patterned, and using this resist as a mask, the charge storage single crystal silicon 16 is etched to obtain the desired shape. Next, in FIG. 1(C), the charge storage single crystal silicon 16 is thermally oxidized. Then, a capacitor insulating film 17 is formed, and a cell plate electrode [18] is grown. This cell plate electrode 18
Polysilicon is fine.

Cell plate electrode 1 is formed again by photoresist process.
8 to obtain a capacitive element of a desired shape.

Finally, in FIG. 1(d), after growing one second interlayer insulating film, a contact hole is opened in a part of the diffusion layer 12 by a photoresist process, a bit line 20 is wired, and a memory cell is formed. It is formed. In this case, the capacitive element is formed between the cell plate electrode 18 and the charge storage single crystal silicon electrode 16.

〔Effect of the invention〕

As explained above, according to the method of the present invention, a single crystal semiconductor with a smooth surface and a constant plane orientation can be used as one electrode of a capacitive element, so that the capacitive insulating film is uniform and has a high A thermal oxide film of a single crystal semiconductor that has a breakdown voltage can be used. Therefore, the capacitive insulating film can be easily made thinner, and even if the cell area is reduced and the area occupied by the capacitive element on the substrate is reduced, a capacitive element that can have a large capacity can be obtained.

[Brief explanation of drawings]

FIGS. 1(a) to (d) are schematic cross-sectional views showing an ITIC cell for explaining one embodiment of the present invention in the order of steps, and FIG. 2 is an ITIC cell using a capacitive element manufactured by a conventional manufacturing method.
FIG. 2 is a schematic cross-sectional view showing an IC cell. 11... Silicon substrate, 12... Diffusion layer, 13...
・Word line, 14... Element isolation oxide film, 15... First interlayer insulating film, 16... Charge storage single crystal silicon electrode, 26... Charge storage polysilicon electrode, 17... Capacitive insulation film, 18... cell plate electrode, 19... second interlayer insulating film, 20... bit line; Kaya /I! r Hua! Prisoner 2 ■

Claims (1)

[Claims] forming an insulating film on a single crystal semiconductor substrate, forming a sheet hole reaching the single crystal semiconductor in a part of the insulating film;
The single crystal semiconductor is selectively epitaxially grown so as to cover the inside of the sheet hole and the periphery of the sheet hole on the insulating film, and this grown single crystal semiconductor layer is used as one electrode of a capacitive element and is placed on this electrode. 1. A method for manufacturing a capacitive element, comprising forming a capacitive insulating film, and forming the other electrode of the capacitive element on the capacitive insulating film.