JPS5827669B2 - semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device, and more particularly to a so-called one-transistor memory cell structure configured with one transistor per one bit memory cell.

A RAM (random access memory) device using a one-transistor memory cell with a small number of constituent elements per bit is used as a highly integrated, large-capacity semiconductor memory.

The memory cell is composed of a capacitive element as an information storage section and a gate transistor that controls writing to or reading from the capacitive element, but since these elements are manufactured in a so-called planar structure, the area efficiency is good. Not, but
Therefore, the memory capacity that can be integrated on a fixed chip area is limited.

Accordingly, it is an object of the present invention to provide a one-transistor memory cell structure that can further improve integration density and increase memory capacity.

The present invention will be explained in detail below with reference to the drawings.

FIG. 1 is a sectional view showing the order of manufacturing steps for manufacturing a device according to an embodiment of the present invention.

A P-type semiconductor substrate 1 is prepared, and an N-type low-resistance impurity region 2 is selectively diffused over the entire surface of the substrate as shown in A.

This diffusion region 2 is used as a bit line of a memory circuit.

Next, as shown in B, an N-type semiconductor layer is formed on the upper surface of the substrate 1 by, for example, epitaxial growth, and a silicon oxide film is formed on the upper surface at a predetermined portion facing the impurity region 2 as a bit line provided previously. 4 and silicon nitride film 5 are selectively deposited in this order.

The thickness of the epitaxial layer 3 in this case is 1 to 1.5μ,
About 500 people for silicon oxide film 4, about 1 person for silicon nitride film
It is preferable to set the number to 500 people.

Then, the epitaxial layer 3 is selectively etched using the silicon nitride film 5 as an etching mask to obtain the structure shown in C.

In this state, as shown in D, in order to convert the portion of the epitaxial layer 3 thinned by etching into an oxide film 6 to obtain a mesa-shaped region 3a, the epitaxial layer is oxidized using the nitride film 5 as an oxidation-resistant mask. The film 6 is made to be approximately equal to the upper surface of the mesa-shaped region 3a, and so-called LOCO8 technology is used.

After removing the uppermost nitride film 5, a P-type doped region 7 is formed in the mesa-shaped region 3a by ionizing, for example, boron under predetermined conditions and using a so-called ion implantation technique. The area is upper layer 8 and lower layer 9
The structure shown in E is such that the two are separated from each other.

After that, as shown in F, for example, aluminum 10 is coated on the entire surface.
The aluminum film 10 is used as an etching mask to etch the oxide film 6 as shown in G.

In this case, etching is performed by taking advantage of the fact that there is no aluminum film directly under the overhang portion of the oxide film 4 caused by the oxidation step in E.

Then, the oxide film 4 and the aluminum film 10 are removed, and a silicon oxide film 11 as a gate film is formed on the entire surface of the mesa-shaped region by a well-known method.

For example, polysilicon 12 is selectively deposited on the upper surface of the mesa-shaped region via this silicon oxide film as shown in H.

Finally, a wiring layer 14 of aluminum or the like is deposited on the entire surface via an insulating film 13 and patterned to obtain the memory cell structure of the present invention as shown in FIG.

In this case, the aluminum layer 14 becomes the control electrode and also the word line of the memory.

In such a configuration, the portion of the P-type doped isolation region 7 in contact with the gate film 11 operates as a channel region, and the upper layer portion 8 of the mesa-shaped region separated by this isolation region 7 and the gate on the upper surface thereof operate as a channel region. An information storage capacitor section is constituted by the silicon oxide film provided at the time of forming the oxide film and the polysilicon layer 12 further formed on this oxide film.

If this polysilicon layer 12 is connected to, for example, the reference potential VSS and used as one electrode of the capacitor part, the equinodal circuit of FIG.
As shown in the figure, it can be seen that a one-transistor memory cell consisting of a gate transistor T1 and a capacitor C1 is obtained.

Therefore, by selectively applying a write or read control signal to the word line, an inversion layer is formed in the channel of the isolation region 7, and the gate transistor T1 is turned on.

As a result, information corresponding to the bit line is written into the storage capacitor C1 via this transistor, and information written into the capacitor C1 is read out to the bit line via the transistor.

Although the conductivity type of the semiconductor is specified above, it is needless to say that other conductivity types may be used and the semiconductor may be manufactured by other manufacturing methods.

According to the present invention, since the upper part of the mesa-shaped area is a capacitor part and the vertical direction of the mesa-shaped area is a transistor part, the area is significantly reduced compared to a conventional planar structure, and thus a large-capacity memory device can be used. becomes possible.

In particular, by using the above-mentioned LOCO8 technology, it is possible to flatten the surface of the device, and high speed can be expected due to the reduction in parasitic capacitance.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the order of manufacturing steps for obtaining the device of the present invention, FIG. 2 is a cross-sectional view showing one embodiment of the present invention, and FIG. 3 is an equivalent circuit diagram of FIG. 2. Explanation of symbols of main parts, 1...Semiconductor substrate, 3
a... Mesa-shaped area, 7... Separation area,
12... Capacitive electrode layer, 14... Control electrode and word line.

Claims (1)

[Scope of Claims] 1. A semiconductor mesa-shaped region of a predetermined conductivity type provided on a semiconductor substrate;
a semiconductor isolation region of opposite conductivity type provided in layers so as to be separated from each other; a control electrode provided via an insulating film so as to cover an exposed surface of the isolation region on a side surface of the mesa-shaped region; an information storage capacitor section provided above the mesa-shaped region and having a separated upper layer portion of this region as one electrode, and selectively applying a predetermined control signal to the control electrode to store the information via the separation region. 1. A semiconductor memory device configured to control writing and reading of information in a capacitor. 2. A patent characterized in that the storage capacitance section includes a separated upper layer portion of the mesa-shaped region, a silicon oxide film formed on the upper layer portion, and an electrode layer formed on the oxide film. A semiconductor memory device according to claim 1.