JPH0370381B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of a semiconductor memory cell, and more particularly to a structure of a semiconductor memory cell that achieves a larger storage capacity.

Semiconductor memory cells that store binary information in the form of charges have a small cell area, making them excellent as highly integrated and large-capacity memory cells. In particular, a memory cell (hereinafter abbreviated as 1TIC cell) consisting of one transistor and one capacitor is important as a memory cell for highly integrated memory because it has few constituent elements and has a small cell area.

Figure 1 shows an example of a 1TIC cell that has been commonly used in the past. In FIG. 1, a capacitor electrode 3 forms a storage capacitor between it and an inversion layer 6. In FIG. 2
is the gate electrode of the switching transistor, which is connected to the word line, and controls the movement of charges between the diffusion layer 4 and the inversion layer 6, which are connected to the bit line. Further, 7 is an isolation region from an adjacent memory cell. In the conventional example, the storage capacity is determined by the area of the capacitor electrode (3) and the dielectric constant and film thickness of the insulating film (5). That is, there are the following three methods for securing a large storage capacity.

(1) Increase the area of the capacitor electrode.

(2) Reduce the thickness of the insulating film.

(3) Use an insulating film with a high dielectric constant.

Incidentally, high integration of memory is generally achieved by reducing memory cell size with advances in microfabrication technology, and in the 1TIC cell structure shown in the conventional example, the area of the capacitor electrode is reduced. Therefore, in conventional 1TIC cells, a significant decrease in storage capacity was prevented by reducing the thickness of the insulating film. However, the thickness of the insulating film is approaching its limit.
On the other hand, cell miniaturization continues to progress, and the storage capacity of conventional 1TIC cells will continue to decrease unless an insulating film with a high dielectric constant is used. Insulating films with high dielectric constants are still in the exploratory stage and there is no prospect that they will be put to practical use in the near future.

As mentioned above, the conventional 1TIC cell has the problem that its storage capacity will decrease more and more in the future.
Moreover, a large memory capacity is desired due to the alpha particle resistance problem, the sensitivity of the sense amplifier, etc. (for example, a memory capacity of 50 fF or more due to the alpha particle resistance problem).
1TIC is no longer sufficient.

An object of the present invention is to provide a semiconductor memory cell with a novel structure that improves the drawbacks of the conventional 1T1C cell and can obtain a larger storage capacity than the conventional type even in a memory cell with a small area. .

According to the present invention, a plurality of regions partitioned by semiconductor walls are formed on a semiconductor substrate, and the side surfaces of the walls or part of the side surfaces and bottom surfaces in each region are covered with a conductive thin film via a thin insulating film. This conductive thin film, the thin insulating film, and the wall or the semiconductor of the wall and the substrate constitute a memory cell capacitor, and the surface of the conductive thin film is covered with an insulating film, and the epitaxial layer is electrically connected to the substrate. an epitaxial semiconductor film is formed to fill each of the regions, one MIS field effect transistor is formed in the epitaxial semiconductor film in one region, and one of the diffusion layers is electrically connected to the conductive thin film. A semiconductor memory cell characterized by this can be obtained.

Typical embodiments of the invention will be described in detail below with reference to FIGS. 2 and 3. Figure 2 shows the memory in the present invention.
Figure 3 shows the top view of the cell.
FIG. 3 is a schematic cross-sectional view of a portion of the plan view shown in the figure cut out along the dashed line AA′, showing the manufacturing process in order.

First, for example, a silicon dioxide film 22 is formed on the surface of a P-type single crystal silicon substrate 21 by a thermal oxidation method, and then a photoresist film 22 having a shape of an element isolation region is formed.
3 was formed (Figure a).

Next, the silicon dioxide film 22 is etched away using the photoresist 23 as an etching-resistant mask, and the silicon substrate 21 is also deeply etched to form a recess on the surface of the silicon substrate. After covering with a film 24, a polycrystalline silicon 25, a silicon dioxide film 26, and a silicon nitride film 27 were successively formed, and then the entire surface except for a portion of the recess was covered with a photoresist 28 (Figure b).

Next, the silicon nitride film 27, the silicon dioxide film 26, the polycrystalline silicon 25, and the silicon dioxide film 24 are removed using the photoresist 28 as an etching-resistant mask, and then the silicon nitride film 27 is used as an oxidation-resistant mask to remove the silicon dioxide film 24. A part of the polycrystalline silicon 25 was oxidized by an oxidation method (Figure c).

Next, using the silicon nitride film 27 as an etching-resistant mask, the silicon dioxide film 29' formed on a part of the bottom of the recess is removed, and after removing the silicon nitride film 27, the window formed at the bottom of the recess is removed. Using a silicon epitaxial growth method, single crystal silicon 30 having the same conductivity type as the substrate silicon was grown to completely fill the recess (Figure d).

Next, after removing the silicon dioxide film 26 exposed on the surface, the polycrystalline silicon 25 and the single crystal silicon 30 formed by epitaxial growth were removed by etching until the surface of the silicon dioxide film 22' was exposed (Fig. e). ).

Next, a gate oxide film 31 is formed on the single crystal silicon.
The gate electrode 11' of the switching transistor is formed using polycrystalline silicon, and the N electrode connected to the bit line is formed by ion implantation of arsenic or phosphorus.
A 1T1C cell was formed by forming an N-type diffusion layer 32 that was electrically connected to the polycrystalline silicon 25 formed in the silicon substrate 21 through the type diffusion layer region 12 and polycrystalline silicon 13 (f
figure).

The plan view in Figure 2, the sectional view in Figure 3 f, and the conventional
Comparing Figure 1 of the 1T1C cell, the gate electrode 2 of the switching transistor connected to the word line in Figure 1 is as follows in Figures 2 and 3 f.
Diffusion layer 4, which corresponds to polycrystalline silicon 11' and is connected to the bit line in FIG. 1, corresponds to diffusion layer 12 in FIGS. 2 and 3f. When storing electric charge, by turning on the switching transistor connected to the word line, the electric charge is accumulated in the polycrystalline silicon 25 formed in the substrate from the diffusion layer connected to the bit line, and the memory state is changed. Become. And this storage capacitance is polycrystalline silicon 25
It is formed by the capacitance of the silicon dioxide film formed between the silicon substrate 21 and the silicon substrate 21. That is, capacitors are formed on both sides of polycrystalline silicon 25. Therefore, the storage capacity becomes extremely large. Furthermore, if an even larger capacitance is required, by forming the polycrystalline silicon 25 deep within the substrate, only the storage capacitance can be significantly increased without increasing the occupied surface area. When reading out the stored charge, the switching transistor connected to the word line is turned on, and the charge accumulated in the polycrystalline silicon 25 formed in the substrate is transferred to the diffusion layer 12 connected to the bit line. Perform reading.

Up to now, the storage capacity of a dynamic memory cell is required to be large enough not to cause a soft error even if one alpha ray is incident thereon. When using a conventional 1T1C memory cell in which the storage capacity section is formed in a planar manner, in a 1Mbit class highly integrated large capacity memory cell, the storage capacity section accounts for approximately 50% of the cell area. According to the invention, since the storage capacitor portion is formed within the substrate, the surface area of this portion is extremely small and is suitable for high integration.

In addition to the ring type MOS transistor shown in Figure 3, which uses the ring type MOS transistor as a switching transistor, there is also a bar type MOS transistor as shown in Figure 4.
A structure in which the transistor is used as a switching transistor may also be used. Regarding element isolation between cells, in the embodiment described above, a thin silicon substrate was left as an isolation region, but there is no need to limit it to this, and isolation may be performed using an insulator such as SiO ₂ . Also, not only MOS transistors but also general
It is clear that MIS transistors can be used as switching transistors.

Further, in the above embodiment, the shape of the capacitance region made of polycrystalline silicon formed in the silicon substrate is extended to below the element region, and is L-shaped as can be seen in the cross-sectional view 3f. However, the shape of this capacitance region itself It does not necessarily have to be an L-shape extending below the element region, and a structure formed only in the depth direction of the substrate is sufficient.
However, in this case, it is necessary to form a capacitance region deeper in the depth direction than in the L-shape to increase the capacitance.

As described above, according to the present invention, a large memory capacity can be obtained even in a small memory cell area, so that a memory cell suitable for high integration can be easily obtained.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view of a conventional 1T1C memory cell.
FIG. 2 is a plan view of a memory cell according to the present invention, and FIG. 3 is a cross-sectional view showing a process for manufacturing an embodiment of the memory cell according to the present invention. FIG. 4 is a plan view showing another embodiment of the present invention. The numbers in the figure indicate the following. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... Gate electrode connected to word line, 3... Capacitor electrode, 4... Diffusion layer connected to bit line, 5... Silicon dioxide film, 6... Inversion layer, 7... Formed in isolation region. 11... Word line, 11'... Gate electrode of switching transistor (polycrystalline silicon), 12... Diffusion layer connected to bit line, 13
...Polycrystalline silicon, 21...Silicon substrate, 22,
22'...Silicon dioxide film, 23...Photoresist, 2
4...Silicon dioxide film, 25...Polycrystalline silicon, 26
...Silicon dioxide film, 27...Silicon nitride film, 28...Photoresist, 29, 29'...Silicon dioxide film, 30...
Single crystal silicon formed by epitaxial growth, 31... silicon dioxide film, 32... diffusion layer, 32...
Silicon dioxide film, 41... Gate electrode of switching transistor, 42... Diffusion layer connected to bit line, 43... Polycrystalline silicon, 45... Polycrystalline silicon, 46... Silicon dioxide film.

Claims (1)

[Claims] 1. A plurality of regions partitioned by semiconductor walls are formed on a semiconductor substrate, and the sides of the walls or part of the sides and bottom of each region are covered with a conductive thin film via a thin insulating film, and the conductive A capacitor for a memory cell is constituted by a thin film, the thin insulating film, and a wall, or a wall and a semiconductor of the substrate, and the surface of the conductive thin film is covered with an insulating film, and the epitaxial semiconductor film is electrically connected to the substrate. It is characterized in that it is formed to fill each region, one MIS field effect transistor is formed in the epitaxial semiconductor film in one region, and one of the diffusion layers is electrically connected to the conductive thin film. semiconductor memory cell.