JPH0423832B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of a semiconductor memory cell, and more particularly to a structure of a semiconductor memory cell that achieves a larger storage capacity.

Semiconductor memory cells that store binary information in the form of charges have a small cell area, making them excellent as highly integrated and large-capacity memory cells. In particular, a memory cell (hereinafter abbreviated as 1T1C cell) consisting of one transistor and one capacitor is important as a memory cell for highly integrated memory because it has few constituent elements and has a small cell area.

Figure 1 shows an example of a 1T1C cell that has been commonly used in the past. In FIG. 1, a capacitor charge 3 forms a storage capacitor between it and an inversion layer 6. In FIG. Reference numeral 2 denotes a gate electrode of a switching transistor, which is connected to a word line and controls the movement of charges between a diffusion layer 4 and an inversion layer 6, which are connected to a bit line. Further, 7 is an isolation region from an adjacent memory cell. In the conventional example, the storage capacity is determined by the area of the capacitor electrode (3) and the dielectric constant and film thickness of the insulating film (5). That is, there are the following three methods for securing a large storage capacity.

(1) Increase the area of the capacitor electrode.

(2) Reduce the thickness of the insulating film.

(3) Use an insulating film with a high dielectric constant.

Incidentally, high integration of memory is generally achieved by reducing memory cell size as microfabrication technology advances, and in the 1T1C cell structure shown in the conventional example, the area of the capacitor electrode is reduced. Therefore, in conventional 1T1C cells, a significant decrease in storage capacity was prevented by reducing the thickness of the insulating film. However, the thickness of the insulating film is approaching its limit.
On the other hand, cell miniaturization continues to progress, and the storage capacity of conventional 1T1C cells will continue to decrease unless an insulating film with a high dielectric constant is used. There is no prospect that high dielectric constant insulating films will be put to practical use in membrane cable staircases in the near future.

As mentioned above, the conventional 1T1C cell has the problem that its storage capacity will decrease more and more in the future.
Moreover, a large memory capacity is desired due to the alpha particle resistance problem, the sensitivity of the sense amplifier, etc. (for example, a memory capacity of 50 fF or more due to the alpha particle resistance problem).
1T1C can no longer deal with it.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory cell having a structure that allows a larger storage capacity than conventional types by making it possible to increase the area of a capacitor electrode even in a memory cell with a small area. It is in.

According to the present invention, the first insulating material covers at least a portion of the recess formed on the surface of the first conductivity type semiconductor substrate, and the first insulating material is in contact with at least a sidewall of the first insulating material and is isolated from each other. 1st and 2nd
a second insulating material covering at least the side surfaces of the first and second conductive materials;
a third conductive material that is insulated from the second conductive material and fills the remaining portion of the recess and is provided with a reference potential; formed in contact with a substance and electrically connected to the first or second conductive substance
A semiconductor memory cell characterized in that it includes a second conductivity type diffusion region that is a source electrode of an MIS transistor is obtained.

A typical embodiment of the present invention will be described in detail below with reference to FIG. FIG. 2 is a schematic cross-sectional view showing the manufacturing process of the memory cell according to the present invention in sequence.

FIG. 2a shows that a silicon dioxide film 12 is formed on the surface of a P-type silicon single crystal substrate 11 by a thermal oxidation method, and then a silicon nitride film 13 is formed thereon.
A state in which the entire surface except the groove portion is covered with photoresist 14 is shown.

FIG. 2b shows that after removing the silicon nitride film 13 and silicon dioxide film 12 using the photoresist 14 as an etching-resistant mask and etching the silicon substrate 11 to form a groove, silicon in the groove is removed by thermal oxidation. A silicon dioxide film 15 is formed on the surface of the substrate, and then the trench is completely filled with polycrystalline silicon 16 doped with impurities at a high concentration.

In FIG. 2c, the polycrystalline silicon 16 is etched away from the surface, leaving the polycrystalline silicon 16' only at the bottom of the groove, and then the surface of the polycrystalline silicon 16' is covered with dioxide by thermal oxidation. A state in which a silicon film 17 is formed is shown.

FIG. 2d shows a state in which polycrystalline silicon 18 heavily doped with n-type impurities is grown over the entire surface of the wafer, and its surface is further covered with a thermal oxide film 19.

FIG. 2e shows that the silicon dioxide film 19 is etched away from the surface using an anisotropic etching technique, such as a reactive sputter etching technique, leaving the silicon dioxide film 19' only on the side surfaces of the groove. Using the silicon dioxide film 19' as an etching-resistant mask, the polycrystalline silicon 18 is etched away from the surface by reactive sputter etching in the same manner as described above.
This shows the state with 18B remaining.

FIG. 2f shows that after the silicon dioxide film 19' and the silicon dioxide film 17' on the bottom of the trench are etched away, the silicon dioxide film 20 and
This figure shows the silicon nitride films 21 formed by the CVD method.

FIG. 2g shows that the silicon nitride film 21 is etched away from the surface by an anisotropic etching technique such as reactive sputter etching, leaving the silicon nitride film only on the side surfaces of the groove, and then the silicon nitride film is etched away. The silicon dioxide film 20 serves as an etching-resistant mask.
After removing the silicon dioxide film 20' by etching and leaving the silicon dioxide film 20' only on the sidewalls of the trench, the silicon nitride film left on the sidewalls of the trench is removed and impurities of the same type as the polycrystalline silicon 16' are added to a high concentration over the entire wafer. This figure shows a state in which thick doped polycrystalline silicon 22 is formed to completely fill the trench and flatten the surface.

FIG. 2h shows that the polycrystalline silicon 22 is etched from the surface by an anisotropic etching technique such as reactive sputter etching, leaving the polycrystalline silicon 22' in the grooves, and then thermal oxidation is applied to the surface to form silicon dioxide. 23 is shown.

FIG. 2i shows that after removing the silicon nitride film 13 and silicon dioxide film 12, a silicon dioxide film 24 is formed by thermal oxidation, a gate electrode 25 of a switching transistor is formed, and this gate electrode is ion-implanted. This figure shows a state in which n-type diffusion layers 26, 27, and 27' are formed by implanting arsenic ions as a mask.

In FIG. 2J, areas other than a part on the diffusion layer 27 and a part on the polycrystalline silicon 18A, 18B are covered with a photoresist 28, and then a silicon dioxide film 23 is formed using the photoresist 28 as an etching-resistant mask. , 24 are partially etched away.

FIG. 2k shows that after the photoresist 28 has been removed, the polycrystalline silicon 18A or 18B buried in the groove and the n-type diffusion layers 27, 27' are replaced by a polycrystalline silicon 29 doped with n-type impurities at a high concentration.
29' is used to show electrical connection.

FIG. 2l shows that the surfaces of the polycrystalline silicon 25, 29, 29' are coated with a silicon dioxide film 30 by thermal oxidation.
The photoresist 31 is shown covering all regions except the upper part of the polycrystalline silicon 22'.

FIG. 2m shows a polycrystalline silicon film doped with the same type of impurity as the polycrystalline silicon 22' at a high concentration after etching the silicon dioxide film 23 using the photoresist 31 as an etching-resistant mask and then removing the photoresist. 32 is formed and electrically connected to the polycrystalline silicon 22', and then a silicon dioxide film 33 is formed on the surface of the polycrystalline silicon 32 by thermal oxidation. In this way, a memory cell for 2 bits is formed.

Comparing the cross-sectional view in Figure 2m with Figure 1 of the conventional 1T1C cell, we see that the gate electrode 2 of the switching transistor connected to the word line in Figure 1.
corresponds to the polycrystalline silicon 25 in FIG. 2m, and the diffusion layer 4 connected to the bit line in FIG.
In Figure m, this corresponds to the diffusion layer 26. When storing electric charge, by turning on the switching transistor connected to the word line, the electric charge is accumulated in the polycrystalline silicon 18A and 18B formed in the substrate from the diffusion layer connected to the bit line, and is stored. state. However, at this time, the polycrystalline silicon 22' formed in the center of the groove is kept in a grounded state. As a result, the storage capacitance is formed by the capacitance of the silicon dioxide film 20' formed between the polycrystalline silicon. Therefore, the storage capacitance is polycrystalline silicon 18
By forming A and 18B deep within the substrate,
In other words, by forming deep trenches, only the storage capacity can be significantly increased without increasing the area occupied by the memory cell as viewed from the surface. When reading the stored charges, the switching transistor connected to the word line is turned on to move the charges accumulated in the polycrystalline silicon 18A and 18B formed in the substrate to the diffusion layer 26 connected to the bit line. to read.

Up to now, the storage capacity of a dynamic memory cell is required to be large enough not to cause a soft error even if one alpha ray is incident. When using a conventional 1T1C memory cell in which the storage capacity section is formed in a planar manner, in a 1Mbit class highly integrated large capacity memory cell, the storage capacity section accounts for approximately 50% of the cell area. According to the invention, since the storage capacitor section is formed inside the substrate, the storage capacity can be easily increased by increasing the depth of the groove, and in addition, the area occupied by this section is extremely small, allowing for high integration. suitable for

Furthermore, in the present invention, the polycrystalline silicon 22' is grounded in order to form a capacitance within the groove, which has the advantage that isolation between elements can be achieved at the same time. Furthermore, considering the shape of the polysilicon 18A in the capacitor forming part, in order to make the channel length of the parasitic MOS transistor formed in the isolation region between elements as long as possible,
18B is not formed directly to the bottom of the trench, but is stopped in the middle of the trench, and the bottom of the trench is filled with grounded polycrystalline silicon 22' to further improve the element isolation effect.
Therefore, the polycrystalline silicon 22' has a convex shape within the groove. Furthermore, by adopting such a shape, sufficient separation characteristics can be obtained even when the width of the groove is narrowed.

In the above embodiment, a convex polysilicon layer 18A, 18B was provided in the groove to improve element isolation characteristics, but the polysilicon shape was as shown in FIG. It's okay to be hot. This can be done more easily than the process shown in the previous example. However, in this shape, the width of the groove isolation region is wider than that of the above-described one.

Furthermore, in the present invention, the reference potential is applied to the polysilicon 22' (FIG. 2) and 42 (FIG. 3) buried in the trench.
2', 42 and the semiconductor substrate are insulated and separated by a silicon dioxide film 15, and a reference potential is applied from the surface. However, another possible method for applying the reference potential to the polysilicon 22' is to apply it from the substrate. This structure is shown in FIG. As can be seen in FIG. 4, the polysilicon 52 buried in the trench is directly electrically connected to the semiconductor substrate. Such a structure can be made more easily than the process described above, and has the advantage that there is no need to provide a new reference potential line when compared with the structure described above.

As described above, according to the present invention, a large memory capacity can be obtained even in a small memory cell area, so that a memory cell suitable for high integration can be easily obtained.

[Brief explanation of drawings]

Figure 1 is a schematic cross-sectional view of a conventional 1T1C memory cell.
FIG. 2 is a schematic cross-sectional view showing a process for manufacturing a memory cell according to the present invention, and FIGS. 3 and 4 are schematic cross-sectional views of the memory cell according to the present invention. 1...Silicon substrate, 2...Gate electrode connected to the word line, 3...Capacitor electrode, 4...
Diffusion layer connected to bit line, 5...Silicon dioxide film, 6...Inversion layer, 7...Silicon dioxide film formed in isolation region, 12, 15, 17, 17', 19,
19', 20, 20', 23, 24, 30, 33...
...Silicon dioxide film, 13,13',21...Silicon nitride film, 14,28,31...Photoresist, 1
6, 16', 18, 18A, 18B, 22, 2
2', 29, 29', 32...polycrystalline silicon, 2
5... Gate electrode connected to the word line, 26...
...diffusion layer connected to the bit line, 27, 27'...
...Diffusion layer, 42...Polycrystalline silicon, 52...Polycrystalline silicon, 53...Silicon dioxide film.

Claims (1)

[Claims] 1. A first insulating material that covers at least a portion of a recess formed on the surface of a first conductivity type semiconductor substrate; a first and a second insulating material that are in contact with at least a side wall of the first insulating material and are separated from each other; conductive material,
a second insulating material covering at least the side surfaces of the first and second conductive materials, the second insulating material being insulated from the first and second conductive materials and filling the remaining portion of the recess and provided with a reference potential; a third conductive substance, an MIS transistor provided on the surface of the first conductivity type semiconductor substrate, in contact with the first insulating substance, and electrically connected to the first or second conductive substance; A semiconductor memory cell comprising a second conductivity type diffusion region serving as a source electrode.