JPS6239053A - Semiconductor memory cell and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain an increased storage capacity with a memory cell having an extremely small area, by forming an isolation region for isolating two memory cells within a groove formed in a semiconductor substrate. CONSTITUTION:Polycrystalline silicon 9 having a reference potential provides a common capacitor electrode for two memory cells and also serves as an isolation region therefor. Electric charges are stored in the polycrystalline silicon 6 buried in a groove (h) of a semiconductor substrate 1. Therefore, if the groove is formed deeper, an increased storing capacity can be obtained without increasing the area of the memory cell as viewed from the surface. Further, a field effect transistor having N channels is formed by utilizing polycrystalline silicon 3 connected to a word line as a gate electrode, an N-type diffused layer 4 connected to a bit line as a drain electrode, and an N-type diffusion layer 6 connected to the polycrystalline silicon charge storing region 6 as a source electrode. Silicon dioxide films 7 and 8 are formed and a P-type impurity layer 2 is formed beneath the N-type diffused layer 4.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention ii: relates to a semiconductor memory cell and a method for manufacturing the same, and more specifically relates to a semiconductor memory cell having a trench-type storage capacitor portion and a method for manufacturing the same. .

(Prior art) At present, in large capacity dynamic I'i, A, and M, there are a few cell components, one transistor and one capacitor, and a small cell area.
Hereinafter abbreviated as lTiC cells) are widely used9,?
However, since a conventional TiC cell has a transistor and a capacitor formed on a plane on the surface of a semiconductor substrate, the area of the capacitor part has been reduced as elements become smaller. Until now, by reducing the thickness of the dielectric material that makes up the capacitor, we have been able to prevent a decrease in the amount of stored charge due to a reduction in the capacitor area, but the thickness of the dielectric material is now approaching its limit, and further miniaturization is expected in the future. In order to improve this drawback of the conventional 1 '1' 1 e cell, a significant decrease in the amount of stored charge is inevitable. A trench-type lTiC cell embedded in a semiconductor substrate has been proposed.

FIG. 4 shows an example of this trench type lTiC cell.

This was published by Kiyoo Ito and others in the proceedings of the International Solid State Circuits Conference (1983), page 283, and is a companion piece. In FIG. 4, the capacitor electrode 43 forms a capacitor between it and the inversion layer 46, and charges are accumulated in the inversion layer 46.

42 is the gate electrode of the switching transistor connected to the word line, and the diffusion Ji+44 connected to the bit line
1. is connected to the inverted M46. The transfer of charges between the diffusion layer 45 and the diffusion layer 45 is controlled. Further, 47 is an isolation region from adjacent memory cells. The groove-type ITIC cell shown in FIG. 4 is realized by using the sidewall of the groove formed in the conductor substrate 1 of the capacitor part t4 of the conventional lTiC cell.
By making the grooves sufficiently deep, it is possible to secure a larger storage capacity. However, in the known prototype ITIC cell shown in FIG. 4, the capacitor portion, which was formed planarly on the semiconductor substrate 41 in the conventional lTiC cell, is only formed in the depth direction, and the element isolation region 47 is separately formed. exist. Therefore, when the minimum feature size is given, the area occupied by the capacitor part and the isolation region in the memory cell part is about the same size as that of a conventional lTiC cell, and there is almost no reduction in the area of the memory cell. I don't contribute anything.

Furthermore, since an inversion layer is formed on the side wall of the groove and charges are accumulated there, the effective collision cross section of α particles increases, making soft errors more likely to occur.

As described above, the known trench-type lTiC cell has many problems, and these problems will become fatal when considering future increases in memory capacity.

(Objective of the Invention) An object of the present invention is to provide a semiconductor memory cell with a novel structure that solves the problems of the above-mentioned well-known trench type TiC cell and can ensure a large storage capacity with a small cell area, and a method for manufacturing the same. It is in.

(Means for Solving the Problems) A semiconductor memory cell according to a first aspect of the present invention includes a first insulating material that covers at least a part of a recess formed on a surface of a first conductivity type semiconductor substrate; The first and second insulating materials are in contact with at least a side wall of the first insulating material and are separated from each other.
a second insulating material covering at least side surfaces of the first and second conductive materials;
a third conductive material which is insulated from the conductive material and which fills the remaining portion of the recess and is provided with a reference potential; A diffusion region of a second conductivity type, which is a source electrode of an M I S transistor, is in contact with and electrically connected to the first or second electrically conductive material, and is isolated from the nuclear diffusion region. , and a first conductivity type diffusion region L2 formed in contact with the side wall of the recess.

Further, the method for manufacturing a semiconductor memory cell according to the second aspect of the present invention includes a step of forming a shallow groove by anisotropic etching in a groove forming region on a surface of a first conductivity type semiconductor substrate, and implanting ions to form a shallow groove at the bottom of the groove. a step of forming a first conductivity type impurity region in the semiconductor substrate; a step of applying heat treatment to push the impurity into the semiconductor substrate; a step of further anisotropically etching the shallow trench to form a deep trench; a step of forming a silicon dioxide film, a step of applying an organic material and an insulating material to the entire surface for 11 times, and then a step of covering the area other than the groove opening and its surrounding area with an organic material, and a step of masking the organic material and applying an insulating material. Then, using an insulating material as a mask, etching the organic material 1.2.
a step of etching and removing the silicon dioxide film near the trench opening using the organic material as a mask; and a step of removing the organic material and etching the polycrystalline silicon containing the second conductivity type impurity to the width of the trench. A process of forming/forming the entire surface to a thickness of /3 or less,
A step of chipping the polycrystalline silicon and leaving it only on the side wall of the trench, a step of thermally oxidizing the polycrystalline silicon to form a silicon dioxide film on the surface of the polycrystalline silicon, and a step of forming a silicon nitride film on the surface of the polycrystalline silicon using a C'V'D method. A step of forming polycrystalline silicon containing impurities of a second conductivity type different from that of the semiconductor substrate and completely filling the gap, and etching the polycrystalline silicon from the surface to form polycrystalline silicon only in the grooves. A second conductivity type diffusion region, which is the source electrode of the MIS transistor, is formed on the surface of the first conductivity type semiconductor substrate, such as a step of leaving a . The process includes the steps of:

(Function) The present invention solves the problems of the known techniques by adopting the above-described configuration.

In other words, the capacitor parts of two adjacent mesoricells,
By forming the isolation region of these two memory cells inside one trench formed in the semiconductor substrate, it is possible to form the capacitor part and the isolation region in a smaller area than the known example, resulting in an extremely small volume. You can secure a large storage capacity. It has a memory cell structure.

By forming an impurity layer of a different conductivity type under the diffusion layer of the transistor formed in contact with the trench sidewall with a distance M from this diffusion layer, it is possible to make contact with the trench sidewall. [7] The vacant i-layer of the semiconductor substrate and the diffusion) are separated, and soft ni-layers caused by α particles are generated.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a schematic cross-sectional view of an embodiment of the present invention.

In Figure 1, a 2-bit memory cell J,- is shown.
The polycrystalline silicon 9υ1 to which a reference potential is applied serves as a common capacitor electrode for the two memory cells, and at the same time serves as a frame for separating the two memory cells. The memory cells in the right half of FIG. 1 will be explained below.

In FIG. 1, charges are stored in polycrystalline silicon 6 embedded within a groove in semiconductor substrate 1. In FIG. Therefore, when deep grooves are formed, a large storage capacity can be obtained without increasing the area of the memory 7 when viewed from the surface.
．． )? 'l can be done. In addition, the polycrystalline silicon 3 connected to the word line is used as a gate electrode, the crab Ti-type diffusion layer 4 is used as a gate electrode, and the crab type diffusion layer 4 is used as a gate electrode, which is a seed region of charge. An n-channel charge effect transistor is formed using the i'i type diffusion layer 5 as a source electrode connected to the crystalline silicon layer 76. 7.8 is a silicon dioxide film. P-type impurity layer 2 under the n-type diffusion layer
is formed.

In the embodiment shown in No. 1 [F], the mesori operation is exactly the same as that of the conventional lTiC cell, and the information on the bit line is connected to the bit line by making the field effect transistor conductive. The charge is transmitted from the diffusion layer 4 to the polycrystalline silicon 6 formed in the substrate 1, and the charge is accumulated therein.

Comparing the embodiment shown in FIG. 1 with the known example shown in FIG. 4, the present invention is characterized in that the charge storage region is provided inside the groove, and the capacitor electrode The polycrystalline silicon 9 also serves as an isolation region between two adjacent memory cells. Therefore, it is clear that a memory cell with p smaller area can be realized with the same minimum feature size compared to the known example.However, in the present invention, since the polycrystalline silicon 9 has a separation function, First, the potential of this polycrystalline silicon 9 is set to the ground level. This brings the capacitor electrode to the ground level, which has the advantage of being less affected by power fluctuations and making it possible to realize a memory that is resistant to noise.

By the way, in the present invention, a p-type impurity layer 2 is formed under the n-type diffusion layer 5, and this p-type impurity layer 2 causes the potential of the polycrystalline silicon 6, which is a charge storage region, to be applied to the semiconductor substrate 1. The formed depletion layer and the depletion layer extending from the n-type diffusion layer 5 are separated. Therefore, the area that affects the accumulated charge is significantly smaller than in the known example. That is, it can be said that the memory cell according to the present invention is more effective against phantom errors caused by α particles, etc., than known memory cells. Furthermore, this p-type impurity layer 2 is
Since it also separates the diffusion layer between adjacent memory cells, miniaturization progresses, the groove width becomes smaller, and polycrystalline silicon 9
It also has the effect of fulfilling the element isolation function when isolation alone becomes insufficient. Further, since the p-type impurity layer 2 is formed separately from the diffusion layer 5, no deterioration occurs from the viewpoint of breakdown voltage of the diffusion layer 2.

Note that in the present invention, the reference potential (ground level in this embodiment) is applied to the polycrystalline silicon 9 embedded in the groove, but in this embodiment, the polycrystalline silicon 9 and the semiconductor substrate 1 are It is insulated and separated by a film 8, and a reference potential is applied from the surface. Another possible method for applying the reference potential to the polycrystalline silicon 9 is to apply it from the substrate. The structure in this case is shown in FIG. As can be seen in Fig. 2, the polycrystalline silicon 31 buried in the groove is directly electrically connected to the semiconductor substrate, and compared to the embodiment shown in Fig. 1, there is no need to provide a separate reference potential line. There is. Note that in FIG. 2, 32 indicates a silicon dioxide film.

FIGS. 3(a) to 3(j) are schematic cross-sectional views shown in order of steps to explain the second invention of the present invention.

An embodiment of the second invention is accomplished through the following steps. First, as shown in FIG. 3(a), after sequentially forming a thin silicon dioxide film 12, a silicon nitride film 13, and a silicon dioxide film 14 on a P-type silicon single crystal substrate 11, resist is applied to the area other than the groove formation area. Cover with 15.

Next, as shown in FIG. 3(b), resist 15ti+
Silicon dioxide film 14 as an etching mask. The silicon nitride film 13 and the silicon dioxide film 12 are etched away by anisotropic etching removal, and the silicon substrate 11 is further etched away by anisotropic etching technology using the resist 15 and the silicon dioxide film 14 as an etching-resistant mask to form a shallow groove A. After forming, the photoresist 15 is used as a mask and 7
Then, boron is implanted into the bottom of the groove by ion implantation to form a boron implanted region 16.

Next, as shown in FIG. 3(C), the implanted boron is forced into the silicon substrate 11 by heat treatment, and then the silicon substrate 11 is removed again using the photoresist 15 and the silicon dioxide film 14 as an etching-resistant mask. Etching is removed using directional etching technology to form deep grooves B.
Thereafter, photoresist 15 and silicon dioxide film 14 are removed by etching, and then silicon dioxide film 17 is formed on the inner wall of groove B using silicon nitride film 13 as an oxidation-resistant mask.

Next, as shown in FIG. 3(d), resist 18 is applied to the entire surface.
and an insulating material 19 are sequentially applied, and then a resist 20 is applied to cover the area other than the groove opening and its surrounding area.

Next, as shown in FIG. 3(e), the insulating material 19 is removed by etching using the resist 20 as an etching mask.
Thereafter, the resist 18 is etched away using the insulating material 19 as an etching mask, and its surface is etched onto the silicon substrate 1.
lower than the surface of 1.

Here, as a technique for etching the insulating material 19 and the resist 1B, a reactive sputter etching technique capable of selective etching is suitable.

Next, as shown in FIG. 3(f), the silicon dioxide film 17 formed near the end of the trench opening is etched away using the resist 18 as an etching mask, and then the resist 18 is removed, and then the The impurity is of a conductivity type different from that of the silicon substrate, such as phosphorus, or less than Go/3 of the width A, so that the trench A is not completely filled. As a method 7 for forming polycrystalline silicon 21 containing impurities, polycrystalline silicon is grown in a state containing impurities by a CVD method, or polycrystalline silicon is grown by a CVD method and then impurities are grown by a thermal diffusion method. There is a method of diffusing polycrystalline silicon into polycrystalline silicon.

Next, as shown in FIG. 3(g), the polycrystalline silicon 21 is etched away using a reactive sputter etching technique, leaving the polycrystalline silicon 21 only on the side walls of the trench, which is used as a first electrode. A thin silicon dioxide film 22 is formed on the surface of the polycrystalline silicon 21 by thermal oxidation.

Next, as shown in FIG. 3(h), after forming a thin silicon nitride film 23 by the CVD method, a silicon substrate 11 is deposited on the entire surface.
Polycrystalline silicon 24 containing an impurity of a different conductivity type, such as phosphorus or arsenic, is formed to completely fill the trench.

Next, as shown in FIG. 3(i), polycrystalline silicon 24
is etched from the surface, leaving polycrystalline silicon 24 only in +11B, and using this as a second electrode, silicon nitride film 13 is etched.
Polycrystalline silicon 2 formed in the groove using as an oxidation-resistant mask
1.24 is oxidized to form a thick silicon dioxide film 25. When the thick silicon dioxide film is formed, impurities 26 that have been diffused into the polycrystalline silicon seep into the silicon substrate 11.

Next, as shown in FIG. 3(j), after removing the silicon nitride film 13 and the silicon dioxide film 12, the gate insulating film 27.
The memory cell is completed by forming a gate electrode 28 connected to a word line, a diffusion layer 29 connected to a bit line 30, and a bit line 30.

(Effects of the Invention) As described above, according to the present invention, a large storage capacity can be realized with a small cell area, and moreover, compared to known semiconductor memory cells, it is less susceptible to the effects of ft errors caused by α particles, etc.
Therefore, a memory cell suitable for high-density integration can be easily obtained in which the breakdown voltage of the diffusion layer is maintained at the same level.

[Brief explanation of drawings]

FIG. 1 is a schematic sectional view of one embodiment of a semiconductor memory cell according to the present invention, FIG. 2 is a schematic sectional view of another embodiment of a semiconductor memory cell according to the present invention, and FIGS. 3(a) to (j) are FIG. 4 is a schematic cross-sectional view of a conventional trench-type ITIC memory cell. 1.11.41...Semiconductor substrate, 2...
- Impurity layer, 3... Polycrystalline silicon connected to the word line. 4... Diffusion layer connected to the bit line, 5...
...Diffusion layer, 6,9...Polycrystalline silicon, 7
, 8...Silicon dioxide film, h...Groove, 1
2.14.17,22゜25...Silicon dioxide film, 13.23...Silicon nitride film, 15,18.2
0...Resist, 16...Boron implantation region, 19...Insulating material, 21. 24...
...Polycrystalline silicon, 26...Impurity, 2
7... Gate insulating film, 28... Gate electrode, 29... Diffusion layer, 30... Bit line. Graduation 1 Autopsy Hanzuka/Da L Seeds 1~ . 4 噸 ￥ 3 autopsy 2 theta

Claims (2)

[Claims] (1) A first insulating material that covers at least a portion of a recess formed on the surface of a first conductivity type semiconductor substrate, and a first insulating material that is in contact with at least a sidewall of the first insulating material and is isolated from each other and a second electrically conductive material, and a second insulating material that covers at least the side surfaces of the first and second electrically conductive materials;
a third conductive material that is insulated from the first and second conductive materials and fills the remaining portion of the recess and is supplied with a reference potential; a second conductivity type diffusion region that is a source electrode of a MIS transistor formed in contact with the first insulating material and electrically connected to the first or second conductive material; and isolated from the diffusion region; a first conductivity type diffusion region formed in contact with a side wall of the recess. (2) forming a shallow groove by anisotropic etching in the groove forming region on the surface of the first conductivity type semiconductor substrate; forming a first conductivity type impurity region at the bottom of the groove by ion implantation; and heat treatment. A step of pushing the impurity into the semiconductor substrate, a step of further performing anisotropic etching on the shallow trench to form a deep trench, a step of forming a silicon dioxide film on the inner wall of the trench, and a step of forming an organic material and an insulating film on the entire surface. a step of sequentially applying a chemical substance and then covering the area other than the groove opening and its surrounding area with an organic substance, etching and removing the insulating substance using the organic substance as a mask, etching the organic substance using the insulating substance as a mask, and etching the surface thereof. a step of lowering the silicon dioxide film from the surface of the semiconductor substrate, a step of etching away the silicon dioxide film near the trench opening using the organic material as a mask, and a step of removing the organic material and removing the polycrystalline silicon containing the second conductivity type impurity to the trench width. a step of etching the polycrystalline silicon to leave it only on the side walls of the groove; and a step of thermally oxidizing the polycrystalline silicon to form a silicon dioxide film on the surface of the polycrystalline silicon. forming a silicon nitride film on the surface by a CVD method, and then forming polycrystalline silicon containing impurities of a second conductivity type different from that of the semiconductor substrate to completely fill the trench;
a step of etching the polycrystalline silicon from the surface to leave the polycrystalline silicon only in the groove; a step of forming a thick silicon dioxide film on the surface of the polycrystalline silicon in the groove; forming a second conductivity type diffusion region that is a source electrode of a semiconductor memory cell.