KR100728967B1 - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

A semiconductor device and its fabricating method are provided to extend the effective length of a channel by increasing the surface area of a gate contacting an active region. A semiconductor substrate(200) has an active region with a groove(R) at a center portion thereof. A buried gate(205) is formed on both sides of the groove, and a source region(207a) is formed in the active region along both sides of the groove. A drain region(207b) is formed in the active region of a center portion of the groove between the gates. A first insulation layer is formed on the substrate to cover the gate, and has a first contact hole(H1) exposing the drain region. A bit line(211) is formed on a portion of the first insulation layer to be contacted with drain region. A second insulation layer is formed on the first insulation layer, and has a second contact hole(H2) exposing the source region. A storage node plug(213) is formed in the second contact hole.

Description

Semiconductor device and method for manufacturing same {SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME}

1A to 1F are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to the prior art.

2 is a cross-sectional view showing a semiconductor device of the present invention.

3A to 3E are cross-sectional views of processes for describing a method of manufacturing a semiconductor device, according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

200: semiconductor substrate 201: device isolation film

202: gate insulating film a: polysilicon film

b: metal film 203: gate conductive film

205: gate 206: spacer

207a: source region 207b: drain region

204: insulating film 208: first interlayer insulating film

210: second interlayer insulating film 211: bit line

213: Plug for storage node R: Groove

H1: 1st contact hole H2: 2nd contact hole

M1 ': first mask pattern M2': second mask pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to increase the effective length of a channel and to suppress short channel effects, thereby improving operating characteristics and refresh characteristics, and between the source region and the storage node. The present invention relates to a semiconductor device capable of shortening distance and improving resistance characteristics, and a method of manufacturing the same.

As the semiconductor devices become more integrated, channel lengths and area of junction regions (source / drain regions) of cell transistors decrease and doping concentrations of the channel regions and junction regions increase. As a result, the gate control ability is degraded to cause a short channel effect in which the threshold voltage (Vt) is drastically reduced, and the junction leakage current is increased as the electric field is increased. ) Increases, resulting in deterioration of device characteristics such as deterioration of refresh characteristics.

Therefore, the structure of a transistor having a conventional planar channel structure has reached its limit in overcoming all the problems caused by the high integration. Accordingly, research on the idea and actual process development of the implementation of a MOSFET device having various types of recess channels capable of securing an effective channel length is being conducted.

Hereinafter, a method of manufacturing a semiconductor device having a conventional planar channel structure and a problem thereof will be described with reference to FIGS. 1A to 1E.

1A to 1D are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to the prior art.

Referring to FIG. 1A, after well-known well ion implantation and channel ion implantation are performed in a semiconductor substrate 100 having an isolation layer 101 defining an active region, a gate is formed on the substrate 100. The insulating film 102, the gate conductive film 103, and the hard mask film 104 are sequentially formed. Thereafter, a first mask pattern M1 defining a gate formation region is formed on the hard mask film 104. Here, the gate insulating film 102 is formed of an oxide film by a thermal oxidation process, and the gate conductive film 103 is formed of a laminated film of a doped polysilicon film (a) and a metal film (b), and a hard mask. The film 104 is formed of a nitride film.

Referring to FIG. 1B, after etching the hard mask film 104 using the first mask pattern as an etching mask, the remaining first mask pattern is removed. Subsequently, the gate conductive layer 103 and the gate insulating layer 102 are etched using the etched hard mask layer 104 as an etch mask layer to form the gate 105.

Subsequently, although not shown, the substrate resultant may be used to recover the etching damage caused to the gate 105 sidewalls and the substrate surface upon formation of the gate 105 and to protect the substrate during the subsequent impurity ion implantation process. Is oxidized to form a reoxidation film on the sidewalls of the gate insulating film 102 and the polysilicon film 103 and on the substrate. In forming the reoxidation film, process conditions must be controlled so that the reoxidation film is not formed on the sidewall of the metal film (b). Thus, the oxidation process is called a selective oxidation process.

Next, spacers 106 are formed on both sidewalls of the gate 105, and impurities are implanted into active regions on both sides of the gate 105 including the spacers 106, so that source and drain regions 107a and 107b are formed. ).

As a result, a transistor having a channel structure having a flat, ie planar channel structure under the gate 105 is formed.

Referring to FIG. 1C, a first interlayer insulating layer 108 is formed on a substrate resultant to cover the gate 105 including the spacers 106, and the first interlayer insulating layer 108 is etched to form several gates. A contact hole LH for a landing plug is formed to simultaneously expose 105 and the source region 107a and the drain region 107b therebetween.

Referring to FIG. 1D, a landing plug conductive film such as a polysilicon film doped on the first interlayer insulating layer 108 may be formed to fill the landing plug contact hole LH. Then, the landing plug conductive film and the first interlayer insulating film 108 are chemically polished (CMP) until the hard mask film 104 is exposed, and the landing plug 109 electrically separated by the gate 105. ). Here, the landing plug 109 formed on the source region 107a is then contacted with the storage node plug, and the landing plug 109 formed on the drain region 107b is contacted with the bit line.

Next, a second interlayer insulating film 110 is formed on the first interlayer insulating film 108 including the landing plug 109, and is formed on the drain region 107b on the second interlayer insulating film 110. A second mask pattern M2 for selectively exposing a portion of the second interlayer insulating film 110 is formed. Here, the second mask pattern M2 has an opening of a hole type.

Referring to FIG. 1E, a portion of the second interlayer insulating layer 110 formed on the drain region 107b is removed using the second mask pattern as an etching mask to form a bit line contact hole BH.

Next, in the state where the second mask pattern is removed, a bit line conductive film such as tungsten is formed on the second interlayer insulating film 110 to fill the bit line contact hole BH, and the bit line conductive film is formed. The bit line 111 is connected to the drain region 107b by the landing plug 109 by etching in a line shape.

Referring to FIG. 1F, a third interlayer dielectric layer 112 is formed on the second interlayer dielectric layer 110 to cover the bit line 111, and the third interlayer dielectric layer 112 and the second interlayer dielectric layer 110 are formed. ) Is etched to form a storage node plug contact hole (SH) exposing the landing plug (109) formed on the source region (107a).

Thereafter, a conductive film such as a polysilicon film doped in the storage node plug contact hole SH is embedded to form the storage node plug 113.

Subsequently, although not illustrated, a capacitor is formed to be in contact with the plug 113 for the storage node, and then a subsequent known step is sequentially performed to manufacture a semiconductor device.

However, in the semiconductor device having a planar channel structure shown and described above, since the channel is formed in a two-dimensional planar structure, as mentioned above, a short channel effect is induced by high integration, and the refresh characteristics are The problem of deterioration occurs.

In addition, in the above-described conventional technology, the gate 105 protrudes on the substrate, and the source region 107a and the capacitor are electrically connected through the landing plug 109 and the plug for the storage node. The distance between 107a and the capacitor is far and the resistance between them is large. As a result, a so-called write recovery time (tWR) characteristic deterioration phenomenon occurs in which a read and write operation time for storing charge in the capacitor or releasing charge stored in the capacitor becomes slow.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, it is possible to increase the effective length of the channel to suppress the short-channel effect and improve the refresh characteristics, and also to narrow the distance between the source region and the capacitor tWR It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same, which can improve the characteristics.

A semiconductor device of the present invention for achieving the above object, the semiconductor device is defined by a device isolation film, the semiconductor substrate having an active region formed with a groove in the center along the longitudinal direction including the gate formation region; A buried gate formed at both sides of the groove; A source region formed in the active region on both sides of the groove; A drain region formed in an active region in the center of the groove between the gates; A first insulating layer formed on the substrate to cover the gate and having a first contact hole exposing the drain region; A bit line formed to contact the drain region on a portion of the first insulating layer including the first contact hole; A second insulating layer formed on the first insulating layer so as to cover the bit line and having a second contact hole exposing the source region; And a storage node plug formed to contact the source region in the second contact hole.

Here, the groove has a depth of 100 to 5000 kPa.

The groove has a width of 40 to 70% of the length of the active region along the longitudinal direction.

The gate is a laminated film of a gate insulating film formed on the groove surface corresponding to the gate formation region, a polysilicon film formed on the gate insulating film with a uniform thickness along the groove surface, and a metal film formed to fill the groove on the polysilicon film. Is done.

In addition, a method of manufacturing a semiconductor device of the present invention for achieving the above object, comprising the steps of providing a semiconductor substrate having a device isolation film defining an active region; Recessing a central portion in the longitudinal direction including the gate forming region of the substrate active region to form a groove; Forming a gate insulating film on the groove surface; Embedding the gate conductive film in the groove in which the gate insulating film is formed; Forming a source region in active regions on both sides of the gate conductive layer; Forming a first insulating film on the entire surface of the substrate product in which the gate conductive film and the source region are formed; Etching the first insulating film, the gate conductive film, and the gate insulating film to form a buried gate at both sides of the groove and to form a first contact hole exposing a drain predetermined region; Forming spacers on both side walls of the first contact hole including the gate side surface; Forming a drain region in an active region in the center of the groove between the gates including the spacers; Forming a bit line on a portion of the first insulating layer including the first contact hole; Forming a second insulating film on the first insulating film so as to cover the bit line; Etching the second insulating layer and the first insulating layer to form a second contact hole exposing the source region; And embedding a conductive film in the second contact hole to form a plug for the storage node.

Here, the groove is formed to a depth of 100 ~ 5000∼.

The groove is formed to a width of 40 to 70% of the length of the active region along the longitudinal direction.

The gate conductive film is formed of a laminated film of a polysilicon film formed in a uniform thickness along the groove surface on the gate insulating film and a metal film formed on the polysilicon film to fill the remaining groove portions.

The source region and the drain region are formed by ion implantation of any one of impurities selected from the group consisting of B, BF 2, P, and As with 1E12 to 1E17 atom / cm 2 dose and 5 to 500 KeV energy.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, referring to FIG. 2, the structure and advantages of the semiconductor device of the present invention will be briefly described.

As shown in FIG. 2, the semiconductor device of the present invention includes a semiconductor substrate 200 having an active region in which a groove R is formed in a central portion along a longitudinal direction including a gate formation region, and both sides of the groove R. A buried gate 205 formed in the gate region, a source region 207a formed in the active region on both sides of the groove R, and a drain region 207b formed in the active region of the center portion of the groove R between the gates 205. And a laminated film of an insulating film 204 and a first interlayer insulating film 208 formed on the substrate to cover the gate 205 and having a first contact hole H1 exposing the drain region 207b. And a bit line 211 formed to contact the drain region 207b on the first interlayer insulating layer 208 including the first contact hole H1, and a first interlayer insulating layer to cover the bit line 211. A second interlayer insulating film 210 and an image formed on 208 and having a second contact hole H2 exposing the source region 207a. Claim characterized in that the contact hole consists of a source region (207a) and a plug (213) for a storage node is formed such that the contact in (H2). Unexplained reference numeral 206 denotes a spacer.

Here, the groove (R) has a depth of 100 ~ 5000Å, and has a width of 40 to 70% of the length of the active region in the longitudinal direction.

The gate 205 may include a gate insulating film 202 formed on a groove R surface corresponding to a gate formation region, and a polysilicon film formed on the gate insulating film 202 with a uniform thickness along the groove R surface. (a) and a laminated film of a metal film (b) formed to fill a groove on the polysilicon film (a). Here, the laminated film of the polysilicon film (a) and the metal film (b) is a gate conductive film 203.

In the semiconductor device of the present invention, as shown in FIG. 2, since the gate 205 is buried inside the substrate active region, the surface area of the gate 205 in contact with the active region is increased than in the conventional planar structure. Thus, the effective length of the channel is increased. Therefore, the present invention can suppress the short channel effect and reduce the junction leakage current between the channel and the source and drain regions 207a and 207b to improve the refresh characteristics.

In addition, in the semiconductor device of the present invention, since the gate 205 does not protrude on the substrate and is buried in the active region of the substrate, the source region 207a and the source region 207a are formed only by the storage node plug 213 without a landing plug in the related art. Since the capacitors can be electrically connected, the tWR characteristics can be improved by narrowing the distance between the source region 207a and the capacitors.

Hereinafter, a method of manufacturing a semiconductor device of the present invention having the structure as shown in FIG. 2 will be described with reference to FIGS. 3A to 3E.

3A to 3E are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 3A, well-known well ion implantation and channel ion implantation are performed in a semiconductor substrate 200 having an isolation layer 201 defining an active region, and then active on the substrate 200. A first mask pattern M1 ′ exposing a central portion in the longitudinal direction including the gate forming region of the region is formed. Then, using the first mask pattern M1 ′ as an etch mask, the exposed active region portion is recessed to form the groove R. FIG.

Here, the groove (R) is formed to a depth of 100 ~ 5000Å, 40 to 70% of the width of the active region length along the longitudinal direction, the depth of the groove (R) by adjusting the depth and width of the effective channel The length, the width of the source region and the drain region can be adjusted.

Next, a gate insulating film 202 is formed on the groove R surface, and then a polysilicon film a has a uniform thickness along the groove R surface on the substrate including the gate insulating film 202. To form. Then, the metal film (b) is formed to fill the remaining groove (R) portion on the substrate including the polysilicon film (a). Here, the laminated film of the polysilicon film (a) and the metal film (b) is a gate conductive film 203.

Referring to FIG. 3B, the metal layer b, the polysilicon layer a, and the first mask pattern M1 ′ are CMP until the substrate is exposed, so that the gate conductive layer 203 is formed only in the groove R. Allow to remain. Thereafter, an ion is implanted into the active region on both sides of the gate conductive layer 203, that is, on both sides of the groove R to form a source region 207a.

The source region 207a is formed by ion implantation of any one of impurities selected from the group consisting of B, BF2, P, and As at 1E12 to 1E17 atom / cm 2 dose and 5 to 500 KeV energy.

Next, an insulating film 204 and a first interlayer insulating film 208 are sequentially formed on the entire surface of the substrate product on which the gate conductive film 203 and the source region 207a are formed. Here, the reason for forming the insulating film 204 of the nitride film material before forming the first interlayer insulating film 208 of the oxide film is that when the oxide film is directly deposited on the metal film (b), the metal film (b) is oxidized. This is because the characteristics deteriorate.

Subsequently, a second mask pattern M2 ′ defining a central portion in the longitudinal direction of the groove R, that is, a drain predetermined region, is formed on the first interlayer insulating film 208. Here, the second mask pattern M2 ′ has a line type opening, unlike the second mask pattern M2 in the related art.

Referring to FIG. 3C, the first interlayer insulating layer 208, the gate conductive layer 203, and the gate insulating layer 202 are sequentially etched using the second mask pattern M2 ′ as an etching mask. (R) A buried gate 205 is formed in both sides, and a first contact hole H1 exposing the drain predetermined region is formed. Then, the second mask pattern is removed.

Then, although not shown, a selective oxidation process is performed to form a reoxidation film on the sidewalls of the polysilicon film (a) and the exposed active region of the gate insulating film 202 and the gate conductive film 203.

Next, a spacer insulating film is formed to a predetermined thickness on the surface of the first contact hole H1 and the first interlayer insulating film 208, and the gate insulating film 205 is anisotropically etched from the spacer insulating film and the reoxidation film. Insulating spacers 206 are formed on both sidewalls of the first contact hole H1 including sidewalls.

Thereafter, an ion is implanted into the active region of the center portion of the groove R between the gates 205 including the spacer 206 to form the drain region 207b.

Here, the drain region 207b is ion-implanted at 1E12 to 1E17 atom / cm 2 dose and 5 to 500 KeV energy in any one of impurities selected from the group consisting of B, BF2, P, and As, similar to the source region 207a. To form.

Referring to FIG. 3D, a bit line conductive layer is formed on the first interlayer insulating layer 208 to fill the first contact hole H1, and the bit line conductive layer is etched in a line shape to form a first contact hole ( The bit line 211 is formed on a part of the first interlayer insulating film 208 including H1.

Referring to FIG. 3E, a second interlayer dielectric layer 210 is formed on the first interlayer dielectric layer 208 to cover the bit line 211, and the second interlayer dielectric layer 210 and the first interlayer dielectric layer 208 are formed. ) And the insulating layer 204 are etched to form a second contact hole H2 exposing the source region 207a.

Thereafter, after forming a storage node plug conductive film on the second interlayer insulating film 210 to fill the second contact hole H2, the second interlayer insulating film 210 may be exposed on the storage node plug conductive film. The storage node plug 213 is formed in the second contact hole H2 by CMP.

Subsequently, although not shown, a capacitor is formed to be in contact with the plug 213 for the storage node, and the subsequent successive known steps are sequentially performed to manufacture the semiconductor device of the present invention.

As such, the present invention increases the surface area of the gate 205 in contact with the active region by burying the gate 205 in the substrate active region, thereby increasing the effective length of the channel. Therefore, the present invention can suppress the short channel effect, reduce the doping concentration in the channel region, reduce the junction leakage current, and improve the refresh characteristics.

Particularly, in the present invention, when the channel R is formed by recessing the central portion in the longitudinal direction of the active region of the substrate after the channel ion implantation, the channel ion implanted portion of the channel ion implanted region is removed from the channel ion implanted region. Since it is accessed, the electric field between the drain region 207b and the channel can be further reduced, and the junction leakage current can be effectively suppressed.

In addition, since the gate 205 is buried in the active region of the substrate without protruding from the substrate, the source region 207a and the capacitor can be formed using only the storage node plug 213 without forming the landing plug in the related art. Can be electrically connected. Therefore, the present invention can reduce the distance between the source region 207a and the capacitor by about 3000 to 5000 micrometers, thereby improving the tWR characteristics and simplifying the manufacturing process of the semiconductor device.

In addition, in the prior art, since the mask pattern (M1 of FIG. 1A) having an opening equal to the gate width is required to form the gate, it is not easy to form a gate having a fine width due to the limitation of the exposure process. In FIG. 2A, a first mask pattern M1 ′ exposing a central portion of an active region including the gate forming region of FIG. 3A and a second mask pattern M2 ′ defining a bit line contact forming region of FIG. 3B are used. Since the gate 205 and the bit line contact hole are simultaneously formed, the gate having the fine width can be easily formed by increasing the size of the opening of the second mask pattern M2 ′. As such, the method of the present invention is suitable for implementing ultra-high density semiconductor devices having transistors with fine gate widths and increased effective channel lengths.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

As described above, the present invention increases the surface area of the gate in contact with the active region by burying the gate in the active region of the substrate than in the conventional planar structure, thereby increasing the effective length of the channel. Therefore, the present invention can improve the operation characteristics of the device by suppressing the short channel effect due to the high integration, and can reduce the doping concentration of the channel region to reduce the junction leakage current and improve the refresh characteristics.

Particularly, the present invention recesses the channel ion implanted portion of the channel ion implanted region from the channel ion implanted region when the center portion along the longitudinal direction of the substrate active region is recessed after the channel ion implantation. The electric field between the channel regions can be reduced, so that the junction leakage current can be effectively suppressed.

In addition, since the gate is buried in the active region of the substrate, the source region and the capacitor can be electrically connected to each other using only a storage node plug without a landing plug in the prior art, so that the distance between the source region and the capacitor is about 3000 to 5000 占 퐉. Can be reduced. Therefore, the present invention can not only simplify the manufacturing process of the semiconductor device but also improve the tWR characteristic by reducing the resistance between the source region and the capacitor.

In addition, in the prior art, since the mask pattern (M1 of FIG. 1A) having an opening equal to the gate width is required to form the gate, it is not easy to form a gate having a fine width due to the limitation of the exposure process. In FIG. 2A, a first mask pattern M1 ′ exposing a central portion of an active region including the gate forming region of FIG. 3A and a second mask pattern M2 ′ defining a bit line contact forming region of FIG. 3B are used. Since the gate and the bit line contact holes are simultaneously formed, the gate having the fine width can be easily formed by increasing the size of the opening of the second mask pattern M2 ′. As such, the method of the present invention has the advantage that it is suitable to implement an ultra-high density semiconductor device having a transistor having a fine gate width and an increased effective channel length.

Claims (9)

A semiconductor substrate defined by an isolation layer, the semiconductor substrate having an active region in which grooves are formed in a central portion in a longitudinal direction including a gate formation region; A buried gate formed at both sides of the groove; Source regions formed in active regions on both sides of the groove; A drain region formed in an active region of a groove center portion between the gates; A first insulating layer formed on the substrate to cover the gate and having a first contact hole exposing a drain region; A bit line formed to contact the drain region on a portion of the first insulating layer including the first contact hole; A second insulating layer formed on the first insulating layer to cover the bit line and having a second contact hole exposing a source region; And A storage node plug formed to contact the source region in the second contact hole; A semiconductor device comprising a. The semiconductor device according to claim 1, wherein the groove is formed to a depth of 100 to 5000 microns. The semiconductor device according to claim 1, wherein the groove is formed to have a width of 40 to 70% of the length of the active region along the longitudinal direction. 2. The gate of claim 1, wherein the gate includes a gate insulating film formed on a groove surface corresponding to a gate formation region, a polysilicon film formed on a uniform thickness along the groove surface on the gate insulating film, and a groove formed on the polysilicon film. A semiconductor device comprising a laminated film of a metal film formed to be buried. Providing a semiconductor substrate having an isolation layer defining an active region; Recessing a central portion in a longitudinal direction including a gate forming region of the substrate active region to form a groove; Forming a gate insulating film on the groove surface; Embedding a gate conductive film in a groove in which the gate insulating film is formed; Forming a source region in active regions on both sides of the gate conductive layer; Forming a first insulating film on an entire surface of the substrate product on which the gate conductive film and the source region are formed; Etching the first insulating film, the gate conductive film, and the gate insulating film to form a buried gate at both sides of the groove, and to form a first contact hole exposing a drain predetermined region; Forming spacers on both side walls of the first contact hole including the gate side surface; Forming a drain region in an active region of a groove center between the gates including the spacers; Forming a bit line on a portion of the first insulating layer including the first contact hole; Forming a second insulating layer on the first insulating layer to cover the bit line; Etching the second insulating layer and the first insulating layer to form a second contact hole exposing a source region; And Forming a plug for a storage node by filling a conductive layer in the second contact hole; Method of manufacturing a semiconductor device comprising a. The method of manufacturing a semiconductor device according to claim 5, wherein the groove is formed to a depth of 100 to 5000 GPa. 6. The method of claim 5, wherein the groove is formed to have a width of 40 to 70% of the length of the active region along the longitudinal direction. 6. The gate conductive film of claim 5, wherein the gate conductive film is formed of a laminated film of a polysilicon film formed in a uniform thickness along the groove surface on the gate insulating film and a metal film formed on the polysilicon film so as to fill the remaining groove portions. A method of manufacturing a semiconductor device. The method of claim 5, wherein the source region and the drain region is formed by ion implantation of any one of impurities selected from the group consisting of B, BF2, P and As with 1E12 to 1E17 atomic / cm 2 dose and 5 to 500 KeV energy A method of manufacturing a semiconductor device, characterized in that.

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