JPS6187359A - Semiconductor memory cell - Google Patents

Abstract

PURPOSE:To form capacitor sections and an isolation region by a small area by shaping the capacitor sections for adjacent two memory cells and the isolation region for the two memory cells into one groove formed to a semiconductor substrate. CONSTITUTION:Polycrystalline silicon 20 given reference potential functions as a capacitor electrode for two memory cells while it also serves as an isolation region for the two memory cells. Charges are stored in polycrystalline silicon 17 buried into a groove (h). A semiconductor substrate 11 in high concentration also functions as the capacitor electrode together with the polycrystalline silicon 20. Potential at which the semiconductor substrate in the bottom of the groove does not invert must be applied to the polycrystalline silicon 20 in order to give the polycrystalline silicon 20 an isolation function. Since the semiconductor substrate 11 in high concentration through which the interface between the semiconductor substrate 11 in high concentration and an silicon dioxide film 19 is not brought into a depletion state even under the state in which high potential is memorized to the polycrystalline silicon 17 as a charge storage region, the polycrystalline silicon 20 sufficiently fulfills an isolation function by previously bringing the polycrystalline silicon 20 to a grounding level.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to the structure of a semiconductor memory cell, and more particularly to the structure of a semiconductor memory cell having a trench-type storage capacitor portion.

(Prior art) At present, in the Daiyongryu dynamic RAM, the memory cell (hereinafter referred to as ITI
(abbreviated as C cell) is widely used. However, since conventional ITIC cells have transistors and capacitors formed flat on the surface of a semiconductor substrate, the areas of the cap and cap portions have been reduced as the elements become smaller. By reducing the thickness of the dielectric that makes up the capacitor, we have been able to prevent the amount of stored charge from decreasing due to the reduction of the surface area of the capacitor, but the thickness of the dielectric is now approaching its limit, and further miniaturization will continue in the future. When this happens, a significant decrease in the amount of stored charge is inevitable.

(Problems to be Solved by the Invention) In order to improve the shortcomings of the conventional ITIC cell, a groove-type ITIC has recently been developed in which the capacitor part is buried in the semiconductor substrate.
cell was proposed.

FIG. 4 shows an example of this trench type ITIC cell. At the International Conference on Solid State Circuits held in 1981, Kiyo Ito, Ryouichi Hori, Jun Eto, Shojiro Asai, Norikazu Hashimoto, Nihiro Yakikuni, and Hideo Sunami published 'AnExperlmental I.
Mb DRAM with On-chip Vol.
In FIG. 4, the capacitor electrode 3 forms a capacitor with the inversion layer 6, and charges are accumulated in the inversion layer 6. 2 is a dirt electrode of a switching transistor connected to a word helix, a diffusion layer 4 connected to a bit line, and a diffusion layer 5 connected to an inversion layer 6.
Controls the transfer of charge between the

Further, 7 is a separation region from adjacent mesoricells.

The trench type ITIC cell shown in FIG.
Since the capacitor portion of the C cell is realized by using the side walls of the groove formed in the semiconductor substrate 1, it is possible to secure a large storage capacity by making the groove deep enough. . However, in this well-known trench type ITIC cell, the capacitor portion, which is formed in a planar manner in the conventional ITIC cell, is simply formed in the horizontal direction, and an isolation region exists separately. Therefore, when the minimum dimensions are given, the area occupied by the capacitor part and the isolation region in the memory cell part is equal to that of the conventional ITI.
The size is about the same as that of the C cell, and it does not contribute to the size and smallness of the area of the memory cell. Furthermore, since an inversion layer is formed on the sea side wall, the effective collision cross section of α particles increases, making soft errors more likely to occur.

As described above, the well-known trench type ITIC cell has many problems, and these problems become fatal when considering increasing the capacity of V memory.

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the above-mentioned well-known trench-type ITIC cells and to provide a novel semiconductor memory cell with a tree top structure that can secure a large storage capacity with a small cell area.

(Means for Solving the Problems) The present invention provides a first conductivity type semiconductor layer 12 formed on a high concentration semiconductor substrate 11 of a first conductivity type. A first insulating material is provided inside the semiconductor substrate in contact with at least a side wall of the first insulating material, insulated from the conductive material, and provided on the surface of the remaining Toden-type semiconductor layer in the recess, and in contact with the first insulating material. The semiconductor memory cell is characterized in that the first or second conductive material is in contact with an electric current.

(Function) The present invention solves the problems of the known technology by adopting the above-described configuration.

By forming the capacitor portions of two adjacent memory cells and the isolation region between these two memory cells inside one trench formed in the semiconductor substrate, the capacitor portion and the isolation region can be formed in a smaller area than the known example. This makes it possible to form a memory cell that can secure a large storage capacity in an extremely small area.

Furthermore, by forming most of the trench in a highly doped semiconductor substrate, it is possible to prevent the formation of a depletion layer in the semiconductor substrate in contact with the trench sidewalls, increase the storage capacity, and make it difficult for soft errors due to alpha particles to occur.

(Example) Hereinafter, a typical example of the present invention will be described in detail using FIG. 1. Figure 1 shows a memory cell for 2 pits, in which a polycrystalline silicon 20 is given a reference potential.
are the capacitor electrodes of the two memory cells,
At the same time, it also serves as an isolation region for these two memory cells. The memory cells in the left half of FIG. 1 will be described below. In FIG. 1, charges are stored in a polycrystalline silicon layer 17 buried inside the groove. polycrystalline silicon 2
0 and the highly doped semiconductor substrate 11 also serve as capacitor electrodes. In addition, the polycrystalline silicon 13 connected to the word line is
-) As an electrode, the diffusion layer 14 connected to the bit line is the drain electrode, and the diffusion layer 15 electrically connected to the polycrystalline silicon 17 via the polycrystalline silicon 16 in the V product region of charge is the source electrode. A field effect transistor is formed.

In the embodiment shown in FIG.
Just like a TIC cell, by turning on the field effect transistor, information on the bit line is transmitted from the diffusion layer 14 connected to the bit line to the polycrystalline silicon 17 formed in the substrate. , charge is accumulated.

Comparing the embodiment shown in FIG. 1 with the known example shown in FIG. It is also used as Therefore, it will be clear that compared to known examples, memory cells with the same minimum feature size and smaller area can actually be produced. In order to provide the polycrystalline silicon 20 with a separation function, it is necessary to apply a potential to the polycrystalline silicon 20 such that the semiconductor substrate at the bottom of the groove is not reversed. In the present invention, even when a high potential is stored in the polycrystalline silicon 17 serving as a charge storage region, the high concentration semiconductor substrate 11
Since a high concentration semiconductor substrate is used so that the interface between the polycrystalline silicon 20 and the silicon dioxide film 19 is not depleted, a sufficient isolation function can be achieved by keeping the polycrystalline silicon 20 at the ground level.

Furthermore, by using a highly doped semiconductor substrate as described above, this highly doped semiconductor substrate can also be used as a capacitor electrode. In other words, since the capacitor electrode exists so as to surround the polycrystalline silicon 17 which is the charge storage region, it is possible to secure an extremely large storage capacity with a small surface area.

Furthermore, the polycrystalline silicon 1 inside the groove, which is a feature of the present invention,
Accumulating charges in the semiconductor substrate 7 and using a highly concentrated semiconductor substrate is very effective from the viewpoint of soft errors caused by α particles and the like. In other words, the depletion layer affected by the incidence of α particles only extends from the diffusion layer 15 into the low concentration semiconductor layer, and is much smaller than in the known example.

Note that in the present invention, the reference potential (ground level in this embodiment) is applied to the polycrystalline silicon 20 embedded in the groove, but in this embodiment, the polycrystalline silicon 20 and the highly doped semiconductor substrate 11 are A silicon dioxide film 19 provides insulation, and a reference potential is applied from the surface. Another possible method for applying the reference potential to the polycrystalline silicon 20 is to apply it from the substrate. The structure in this case is shown in FIG. As can be seen in Fig. 3, the polycrystalline silicon 49 buried in the groove is directly electrically connected to the semicircular substrate, and compared to the embodiment shown in Fig. 1, there is no need to provide a separate reference potential line. There are advantages.

50 is a silicon dioxide film.

Next, the manufacturing process of the memory cell according to the present invention will be described. FIGS. 2(a) to 2(h) are schematic cross-sectional views sequentially showing the manufacturing process of the memory cell of the present invention explained in the examples.

In FIG. 2(,), first, a low concentration p-type silicon single crystal layer 22 is grown by epitaxial growth on a high concentration p-type silicon single crystal substrate 21.
A silicon dioxide film 23 is formed on the surface of the type silicon single crystal layer 22 by a thermal oxidation method, and then a silicon nitride film 24 is formed thereon, and then the entire surface except the groove portion is covered with a photoresist 25.

In the second case (b), the silicon nitride film 24 and the silicon dioxide film 23 are removed using the photorenost 25 as an etching-resistant mask, and the low concentration silicon layer 22 and the high-a silicon substrate 21 are further etched away. After forming the groove, a silicon dioxide film 26 is formed on the surface of the silicon substrate in the groove by a thermal oxidation method to cover the polycrystalline silicon 27 doped with a high concentration of impurities. In this step, the polycrystalline silicon 27 is etched away from the surface, leaving the polycrystalline silicon 27 only on the side walls of the trench, and then a silicon dioxide film 28 is formed on the surface of the polycrystalline silicon 27 by thermal oxidation. After that, the trench is completely filled with polycrystalline silicon 29 heavily doped with n-type impurities.

In the second step 1(d), the polycrystalline silicon 29 is removed by etching from the surface, leaving the polycrystalline silicon 29 only inside the surface, and then the surface of the polycrystalline silicon 29 is removed by thermal oxidation. A silicon dioxide film 30 is formed thereon.

After removing the silicon nitride S film 24 and the silicon dioxide film 23, a silicon dioxide film 31 is formed by a thermal oxidation method, and a dirt electrode 32 of a switching transistor is further formed. Arsenic ions are implanted using the electrode 32 as a mask for ion implantation, and n
Type diffusion layers 33 and 34 are formed.

In FIG. 2(f), a part of the diffusion layer 34 and a part of the polycrystalline polysilicon 27 other than the 'wind area' are covered with photorenost 35, and the photoresist 35 is used as an etching-resistant mask using carbon dioxide. A portion of the silicon film 28.degree. 31 is removed by etching.

In FIG. 20), after removing the photoresist 35, the polycrystalline silicon 27 and the n
The type diffusion layer 34 is electrically connected using polycrystalline silicon 36 heavily doped with n-type impurities.

In FIG. 2(h), the surfaces of the polycrystalline silicon 32 and 36 are covered with a silicon dioxide film 37 by thermal oxidation.
(7) After that, all regions except the upper part of the polycrystalline silicon 29 are covered with photoresist 38.

In the second factor (1), after etching the silicon dioxide film 30 using the photoresist 38 as a surface etching mask, the photoresist 38 was removed, and further, an impurity of the same type as the polycrystalline silicon 29 was doped at a high concentration. Polycrystalline silicon 39 is formed and electrically connected to the polycrystalline silicon 29, and then a silicon dioxide film 40 is formed on the surface of the polycrystalline silicon 39 by thermal oxidation.

In this way, memory cells for two pits are obtained. The manufacturing process of the semiconductor memory cell according to the present invention has been briefly described above, and as described above, the semiconductor memory cell according to the present invention can be easily manufactured using manufacturing processes that have been widely used in the past.

(Effects of the Invention) As described above, according to the present invention, a large storage capacity ti' can be secured with a small cell area, and moreover, compared to conventional semiconductor memory cells, it is less susceptible to the effects of alpha particles, etc., and highly concentrated. This has the effect that a memory cell suitable for 4J can be easily manufactured.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view of a typical embodiment of a memory cell according to the present invention, and FIGS. 2(a) to (1) show a process for molding a memory cell according to the present invention. Schematic sectional view,
FIG. 3 is a straight cross-sectional view of a memory cell according to the present invention;
The figure is a schematic IDr side view of a conventional ITIC memory cell. 11, 21...high concentration semiconductor substrate, 12, 22
... Low concentration hand core layer, 13, 32... Gate electrode connected to word line, 14, 33... Diffusion layer connected to bit line VCm, 15, 34, 34'...
Diffusion layer, 16 + 36... Polycrystalline silicon, 17
, 27... Polycrystalline silicon, 18°19 , 23 ,
28, 30, 31, 37, 50... silicon dioxide film, 20, 29, 29', 36, 36',
39, 49... Polycrystalline silicon, 24... Silicon nitride film, 25, 35, 38... Photorenost. Patent face: NEC Corporation, Patent attorney representing NEC Corporation
Uchihara Shinsato Figure 2 (α) (b) Figure 2 (C) (d) Figure 2 (e) (f) Figure 2 (h) Figure 2 Party Figure 3

Claims (1)

[Claims] (1) A layer that covers at least a portion of the recess formed from the surface of the low concentration first conductivity type semiconductor layer formed on the high concentration first conductivity type semiconductor substrate to the inside of the high concentration first conductivity type semiconductor substrate. a first insulating material; first and second conductive materials that are in contact with at least a side wall of the first insulating material and are separated from each other; and at least a side surface of the first and second conductive materials. a third conductive material that is insulated from the first and second conductive materials, fills the remaining portion of the recess, and is supplied with a reference potential; A source electrode of a MIS transistor provided on the surface of the first conductive type semiconductor layer of a high concentration, in contact with the first insulating material, and electrically connected to the first or second conductive material. A semiconductor memory cell characterized by comprising a two-conductivity type diffusion region.