JPS6184053A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6184053A JPS6184053A JP59204001A JP20400184A JPS6184053A JP S6184053 A JPS6184053 A JP S6184053A JP 59204001 A JP59204001 A JP 59204001A JP 20400184 A JP20400184 A JP 20400184A JP S6184053 A JPS6184053 A JP S6184053A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- capacity
- electrode
- layer
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims 6
- 238000003860 storage Methods 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000012535 impurity Substances 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 239000010410 layer Substances 0.000 abstract description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 12
- 238000000034 method Methods 0.000 abstract description 5
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 230000000149 penetrating effect Effects 0.000 abstract 1
- 239000002344 surface layer Substances 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、１トランジスタ型メモリセルに係り、特に小
面積で蓄積容量が大きくでき、種々の雑音耐性に優れ、
超高集積メモリに好適なメモリセル構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a one-transistor type memory cell, which can have a large storage capacity with a small area, and has excellent resistance to various noises.
The present invention relates to a memory cell structure suitable for ultra-highly integrated memory.
超高集積メモリに好適なメモリセルの一例は、特開昭５
１−１３０．１７１１に記載の溝形容量セルがある。An example of a memory cell suitable for ultra-highly integrated memory is disclosed in Japanese Patent Application Laid-open No. 5
There is a trench-type capacitive cell described in 1-130.1711.
禾セルは、シリコン基板に設けられた溝側面を容量とし
て用いホさい平面面積で大なる容量を得るものである。The cell uses the side surface of a groove provided in a silicon substrate as a capacitor to obtain a large capacitance with a small planar area.
しかし容量は従来通りシリコン表面との容量のみを利用
するもので、溝構造の利点を効果的に生かす配慮が十分
でない。However, as in the past, only the capacitance with the silicon surface is utilized, and insufficient consideration has been given to effectively utilizing the advantages of the groove structure.
又、溝型容量ゆえに生じるセル間リーク電流の問題につ
いては何ら考慮していない。Furthermore, no consideration is given to the problem of inter-cell leakage current caused by the trench capacitance.
本発明の第１の目的は、溝構造の利点を十分に活用し、
同一面積で従来構造より大きな容量を有するメモリセル
構造を提供することにある。第２の目的は、従来より種
々の雑音耐性に優れたメモリセル構造を提供することに
ある。The first object of the present invention is to fully utilize the advantages of the groove structure,
It is an object of the present invention to provide a memory cell structure having a larger capacity than a conventional structure in the same area. A second purpose is to provide a memory cell structure that has better resistance to various noises than conventional ones.
従来の溝形容量セルは、基本的には単一の容量部分しか
利用できないという不十分さがあった。Conventional trench-type capacitive cells have the disadvantage that basically only a single capacitive portion can be utilized.
すなわち基板表面とゲート電極（特開昭５１−１３０．
１７８ ）間の容量、もしくは溝内の多結晶シリコン電
極間の容量のいずれかである。本発明は、これらの容量
要素を同時に多数利用できれば、同一平面面積で従来よ
り大きな記憶容量が実現できるという考え方に基づき、
基板表面でなく基板自体を工夫して一つの容量電極とす
る発想を得、上記目標が達成できることを示した。That is, the substrate surface and the gate electrode (JP-A-51-130.
178 ) or the capacitance between polycrystalline silicon electrodes in the trench. The present invention is based on the idea that if a large number of these capacitive elements can be used simultaneously, a larger storage capacity than before can be achieved with the same planar area.
By devising the idea of using the substrate itself as a single capacitive electrode rather than the surface of the substrate, we have shown that the above goal can be achieved.
更に本発明では高濃度基板上に、低濃度層を設け、該高
濃度層により、蓄積容量の増加、及びセル間リーク電流
の防止をも図るものである。Furthermore, in the present invention, a low concentration layer is provided on the high concentration substrate, and the high concentration layer increases the storage capacity and prevents leakage current between cells.
以下、本発明の一実施例を第１図により説明する。本実
施例は、１トランジスタ形メモリセルであり、電荷蓄積
部５は、３ｍの電極材料との間の容量の総和とでき、従
来に比べ約２倍の記憶容量が得られる特徴を有する。以
下説明を明解にするため、Ｎチャネル形のメモリセルに
ついて説明するが、Ｐチャネル形の場合は、下記導電形
をＰ。An embodiment of the present invention will be described below with reference to FIG. This embodiment is a one-transistor type memory cell, and the charge storage section 5 can be formed by the sum of the capacitances between the charge storage section 5 and the electrode material of 3 m, and has a feature that a storage capacity approximately twice as large as that of the conventional one can be obtained. To make the explanation clear, an N-channel type memory cell will be explained below, but in the case of a P-channel type, the following conductivity type is P.
Ｎ逆にすればよい。電荷蓄積部５は、例えば多結晶シリ
コンであり、セル選択用トランジスタ９の一方のＮ゛拡
散層領域１２と接続され、溝内に形成される。記憶容量
の一つＣ５１は、電荷蓄積部５とＰ形エピタキシャル層
２との間の空之層容吸である。この容量は、通常エピタ
キシ１ル層の濃度を通常のＮチャネルＭＯ５ＬＳＩの基
板濃度１０ ”〜ｌ Ｑ ｌｌ′ｃｆｆｌ−３と１９定
する方が妥当なため、他の容量に比し小さい。次にＣ３
２は、電荷蓄積部５と高濃度Ｐ゛またはＮ“基板との間
の容量であり、薄い絶縁膜（単層でも多層でもよい）を
介した金層−全層間容量と等価な容量と見なせる。更に
Ｃは。N You can do it the other way around. The charge storage section 5 is made of polycrystalline silicon, for example, and is connected to one of the N2 diffusion layer regions 12 of the cell selection transistor 9 and formed in the trench. One of the storage capacitances C51 is an empty layer capacity between the charge storage section 5 and the P-type epitaxial layer 2. This capacitance is usually smaller than other capacitances because it is more appropriate to define the concentration of the epitaxial layer as the substrate concentration of a normal N-channel MO5LSI, which is 10'' to lQll'cffl-3.Next, C3
2 is the capacitance between the charge storage section 5 and the high concentration P'' or N'' substrate, which can be considered to be equivalent to the capacitance between the gold layer and the entire layer through a thin insulating film (either a single layer or a multilayer). .Furthermore, C.
１ｇＩ蓄積部５と、他の絶縁膜（単層でも多層でもよい
）を介して例えば多結晶電極７との間の容量であり、Ｃ
５２と同じく、金層−全層間容量と等価な容量である。It is the capacitance between the 1gI storage section 5 and, for example, the polycrystalline electrode 7 via another insulating film (which may be a single layer or a multilayer), and C
Similar to 52, the capacitance is equivalent to the capacitance between the gold layer and all the layers.
以上の如く基板そのものの構造および容量形成を第１図
の様にすれば、単位平面面積当りの容量を第２図に参考
として示す従来構造（容量Ｃ５は、電荷蓄積部５（表面
反転層領域）と多結晶シリコン７との間の容量のみ）に
比し。As described above, if the structure of the substrate itself and the formation of capacitance are as shown in FIG. 1, the capacitance per unit plane area is shown in FIG. ) and polycrystalline silicon 7).
約２倍程度大きくできる。本発明による構造と従来構造
との蓄積容量の詳細な比較を第３図に示す。It can be made about twice as large. A detailed comparison of storage capacity between the structure according to the present invention and the conventional structure is shown in FIG.
第３図では溝深さｄに対する蓄積容量を本発明の構造（
図中、構造Ｉ）と、従来構造（図中、構造■）とで比較
している。本発明による構造■では溝深さｄが大きくな
ればなるほど、従来構造に比べ、大きな蓄積容量が得ら
れる。第１図の基板構造はたとえばＰｏｎＰ”のエピタ
キシャル基板を使うことにより実現可能である。また単
に第２図のＷ造に上記エピタキシャル基板を使うことは
意味がないことは明らかである。何故ならＰ＋層部分に
は反転層ができず電荷蓄積部５が形成できない。In FIG. 3, the storage capacity is plotted against the groove depth d in the structure of the present invention (
In the figure, structure I) is compared with a conventional structure (structure ■ in the figure). In structure (2) according to the present invention, as the groove depth d becomes larger, a larger storage capacity can be obtained compared to the conventional structure. The substrate structure shown in FIG. 1 can be realized by using, for example, a PonP" epitaxial substrate. It is also obvious that there is no point in simply using the above epitaxial substrate for the W structure shown in FIG. 2.The reason is that P+ An inversion layer is not formed in the layer portion, and the charge storage portion 5 cannot be formed.
なお、容量を形成する絶縁膜４，６は薄いＳｉＯ２膜、
５１３ Ｎａ 膜Ｔａ ２０５ 膜や、それらの
複合膜を用いることができる。Note that the insulating films 4 and 6 forming the capacitance are thin SiO2 films,
513 Na film, Ta 205 film, or a composite film thereof can be used.
第４図は、本発明の他の実施例である。本質的には第１
図と変わりはないがセル選択トランジスタのゲート配線
３０が容量部の上部にも配置できることを示したもので
このような構造は折返しビット線構成のメモリセルには
必要である（例えばｌ５ＳＣＣＤｉｇｅｓｔ ｏｆ Ｔ
ｅｃｈ Ｐａｐｅｒｓ、 Ｐ ２８３ ＋第１図参照）
。FIG. 4 shows another embodiment of the invention. Essentially the first
This is the same as the figure, but it shows that the gate wiring 30 of the cell selection transistor can also be placed above the capacitor section, and such a structure is necessary for memory cells with a folded bit line configuration (for example, 15SCCDigest of T
ech Papers, P 283 + see Figure 1)
.
本発明の他の実施例を第５図に示す。本発明の特長は、
Ｃ，Ｊ、を大きくするためＰ基板領域の溝と接する表面
にＰ領域１２より、やや濃度の高い同一導電形の不純物
（略々ｌ Ｑ １７ｃｍ−３オーダー）領域４１を設け
ることにある。空乏層容量に逆比例する空乏層厚は、領
域４１の不純物濃度の平方根に逆比例するため、Ｃ５１
を約３倍大きくでき（Ｐ領域１２の不純物濃度をｌ Ｑ
１６ｃＩｆｆ−３、領域４１の濃度をｌ Ｑ ｌ７ｃ
ｍ−３とした場合）、全体の電荷蓄積容量を更に大きく
できる。領域４１は、溝エッチ後にＰ形不純物１例えば
ボロンを溝内より拡散することにより形成可能である。Another embodiment of the invention is shown in FIG. The features of the present invention are:
In order to increase C and J, an impurity region 41 of the same conductivity type (approximately lQ 17 cm-3 order) having a slightly higher concentration than the P region 12 is provided on the surface of the P substrate region in contact with the groove. Since the depletion layer thickness, which is inversely proportional to the depletion layer capacitance, is inversely proportional to the square root of the impurity concentration in the region 41, C51
can be increased by about 3 times (the impurity concentration of P region 12 can be increased by l Q
16cIff-3, the concentration of region 41 is l Q l7c
m-3), the overall charge storage capacity can be further increased. The region 41 can be formed by diffusing a P-type impurity 1, for example, boron, from within the trench after etching the trench.
本発明の他の実施例を第６図に示す。本実施例では電荷
が蓄積される電極５が、セル選択用トランジスタのゲー
ト電極９の上にも重なっているため電極６と電極７との
間に形成される蓄積容量はさらに増加することになる。Another embodiment of the invention is shown in FIG. In this embodiment, since the electrode 5 on which charges are stored also overlaps the gate electrode 9 of the cell selection transistor, the storage capacitance formed between the electrodes 6 and 7 further increases. .
本発明の他の実施例を第７図に示す。本発明は第１図の
Ｃａ３をなくした構造であり、プロセスの簡略化を目的
としている。ＣＩ！３をなくした分電荷蓄積容量は、第
２図と略々同じとなる。しかしながら本実施例ばかりで
なく本発明の他の実施例筒１．４，５．６図についても
同様に言えることであるが、本構造は、種々の雑音耐性
が従来に増し優れており同一容量でも本構造が有利であ
る。すなわち、従来構造第２図に比し、以下の利点を有
する。Another embodiment of the invention is shown in FIG. The present invention has a structure in which Ca3 in FIG. 1 is eliminated, and is aimed at simplifying the process. CI! 3 is removed, the charge storage capacity is approximately the same as that in FIG. 2. However, the same can be said not only for this embodiment but also for the other embodiments of the present invention shown in FIGS. However, this structure is advantageous. That is, compared to the conventional structure shown in FIG. 2, it has the following advantages.
１）電源電圧のバンプ雑音がない（反転層を作る必要が
ないので電極材料１，２．７には電源電圧を加える必要
がな（グランド電位とできる。1) There is no bump noise in the power supply voltage (there is no need to create an inversion layer, so there is no need to apply a power supply voltage to the electrode materials 1, 2.7 (they can be at ground potential).
２）メモリセルの反転層間のリーク電流がない。2) There is no leakage current between the inversion layers of the memory cell.
３）α線によるアンプセットに強い（主な電荷蓄積部が
シリコン基板上になく、溝内の低抵抗ポリシリコン電極
であること）。3) Resistant to amplifier set by alpha rays (the main charge storage part is not on the silicon substrate, but is a low resistance polysilicon electrode in the groove).
本発明によるメモリセルの平面レイアウト図を第８図（
Ａ）、（Ｂ）に示す。（Ａ）は第１図に示す構造に対応
する平面レイアウト図であり、（Ｂ）は第４図に示す構
造に対応する平面レイアウト図である。２つの平面レイ
アウト図より明らかなように、２つのメモリセルとも、
深溝領域２０の小さな領域に大きな蓄積容量が形成され
ている。A plan layout diagram of a memory cell according to the present invention is shown in FIG.
Shown in A) and (B). (A) is a plan layout diagram corresponding to the structure shown in FIG. 1, and (B) is a plan layout diagram corresponding to the structure shown in FIG. 4. As is clear from the two plan layout diagrams, both memory cells are
A large storage capacitor is formed in a small region of the deep groove region 20.
以上の如く、本発明のメモリセル構造は、超高集積メモ
リＬＳＩに好適であることが明らかである。As described above, it is clear that the memory cell structure of the present invention is suitable for ultra-highly integrated memory LSI.
次に主に第１図の発明につき詳細な製造方法の一例を第
９図に示す。製造方法は、以下の通りである。Next, an example of a detailed manufacturing method mainly for the invention shown in FIG. 1 is shown in FIG. The manufacturing method is as follows.
（ａ）例えばＰ （２）ｏｎＰ” （１）の基板の所
望部をＬＯＣＯ５法により酸化し、電荷蓄積部の溝加工
を行う。本加工は、ドライエッチ技術で可能であるので
詳細は省略する。表面に薄い絶縁膜４を形成し、電荷蓄
積電極５の一部となる多結晶シリコン５１を最終仕上り
厚の略々半分の厚さに堆積し。(a) For example, a desired part of the substrate of P (2) on P" (1) is oxidized by the LOCO5 method, and a groove for the charge storage part is processed. This process can be done using dry etching technology, so the details are omitted. A thin insulating film 4 is formed on the surface, and polycrystalline silicon 51, which will become part of the charge storage electrode 5, is deposited to a thickness approximately half of the final finished thickness.
所望部以外をエツチングで除去する。Remove parts other than the desired parts by etching.
（ｂ）マスクを用い多結晶シリコンと基板との接触部６
２の絶縁膜を除去する。このとき絶縁膜をオーバエッチ
する。これにより接触部のマスク寸法が小さくできセル
サイズを小さくできる効果がある。(b) Contact area 6 between polycrystalline silicon and substrate using a mask
Remove the insulating film No. 2. At this time, the insulating film is overetched. This has the effect of reducing the mask size of the contact portion and reducing the cell size.
（ｃ）多結晶シリコンを堆積後、ヒ素（Ａｓ）もしくは
リン（Ｐ）のｎ形不純物を拡散もしくは打込みにより、
多結晶シリコン５に添加し熱処理を加えると、多結晶シ
リコン５よりｎ形不純物がシリコン基板に拡散していき
、ｎ形波散層部１２が形成される。その後多結晶シリコ
ン５をエツチング除去し絶縁膜６を形成する。(c) After depositing polycrystalline silicon, by diffusing or implanting n-type impurities such as arsenic (As) or phosphorus (P),
When added to polycrystalline silicon 5 and subjected to heat treatment, n-type impurities diffuse from polycrystalline silicon 5 into the silicon substrate, forming n-type wave dispersion layer portion 12. Thereafter, polycrystalline silicon 5 is removed by etching and an insulating film 6 is formed.
（ｄ）容量Ｃ３３の電極となる多結晶シリコン７を堆積
し所望部以外を除去し、更に所望部以外の絶縁膜６も除
去する。(d) Polycrystalline silicon 7, which will become the electrode of the capacitor C33, is deposited and removed in areas other than the desired areas, and the insulating film 6 is also removed in areas other than the desired areas.
（ｅ）表面酸化、ゲート電極９の形成、ソースおよびド
レイン領域３，１２の形成は従来どおりである。(e) Surface oxidation, formation of gate electrode 9, and formation of source and drain regions 3 and 12 are as conventional.
この後メタライゼーションを行えば第１図を得る。第４
図の製造法は、本製造法にＰ形不純物拡散工程を追加す
ればよいことは明らかである。If metallization is then carried out, the result shown in FIG. 1 will be obtained. Fourth
It is clear that the manufacturing method shown in the figure can be achieved by adding a P-type impurity diffusion step to the present manufacturing method.
以上説明した様に、本発明によれば、従来の溝形状を有
するメモリセルに比べ、同一平面面積で約２倍の電荷蓄
積容量が得られ、超高集積化に好適となる。更に本発明
によれば、
■）電源電圧バンプ雑音が除去でき。As described above, according to the present invention, a charge storage capacity approximately twice as large as that of a conventional memory cell having a groove shape can be obtained in the same planar area, making it suitable for ultra-high integration. Furthermore, according to the present invention, (1) power supply voltage bump noise can be removed;
２）メモリセル間干渉がなく、 ３）α線耐性に優れたメモリセルが実現できる。2) No interference between memory cells, 3) A memory cell with excellent resistance to alpha rays can be realized.
これらの特性も、本発明のメモリセルが超高集積化に好
適であることを示すものである。These characteristics also indicate that the memory cell of the present invention is suitable for ultra-high integration.
第１図は、本発明の第１の一実施例を示す断面図、第２
図は、従来の１トランジスタセルの断面図、第３図は、
従来構造（１）と本構造（ＩＩ）での蓄積容量の溝深さ
依存性を示す図、第４図は本発明の第２の実施例を示す
断面図、第５図は、本発明の第３の実施例を示す断面図
、第６図は、本発明の第４の実施例を示す断面図、第７
図は、本発明の第５の実施例を示す断面図、第８図は、
本発明による実施例の平面図を示す図、第９図は、第１
の実施例の製造工程を工程順に示す断面図である。
１・・・高濃度基板、２・・高濃度基板と同一導電形の
低濃度層、３・・・Ｎ゛もしくはＰ“領域、４および６
・・・薄い絶縁膜、５・・・電荷蓄積電極、７・・電極
、８・・・絶縁膜、９・・・ゲート電極、１０・・・絶
縁膜。
第 ７ 口
早 ２７
第 ４ 力
第 ６０
第 ７ ｚ
第８ 図
（八つ
（Ｂ、）
第 ９ 口
Ｃ）
−２，／FIG. 1 is a sectional view showing a first embodiment of the present invention, and FIG.
The figure is a cross-sectional view of a conventional one-transistor cell, and FIG.
A diagram showing the groove depth dependence of storage capacitance in the conventional structure (1) and the present structure (II), FIG. 4 is a cross-sectional view showing the second embodiment of the present invention, and FIG. 6 is a sectional view showing the third embodiment of the present invention, and FIG. 7 is a sectional view showing the fourth embodiment of the present invention.
The figure is a sectional view showing the fifth embodiment of the present invention, and FIG.
FIG. 9 is a diagram showing a plan view of an embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating the manufacturing process of the embodiment in order of process. 1...High concentration substrate, 2...Low concentration layer of the same conductivity type as the high concentration substrate, 3...N'' or P'' region, 4 and 6
... Thin insulating film, 5... Charge storage electrode, 7... Electrode, 8... Insulating film, 9... Gate electrode, 10... Insulating film. 7th Fast Mouth 27 4th Power 60th 7z 8th Figure (Eight (B,) 9th Mouth C) -2,/
Claims (1)
ン基板上に設けられた該基板と同一もしくは反対の導電
形で該基板より濃度の低い不純物を有する第１の層を備
え、表面より上記第１の層を貫通して上記基板まで達す
る溝を有し、更に溝内に第１の電極を有し、該電極との
間に容量を形成する少なくとも一つの対向電極が上記基
板であることを特徴とする半導体装置。 ２、第２の対向電極が、上記電荷蓄積用の電極と絶縁膜
を介して基板と反対方向に設けられたことを特徴とした
請求範囲第１項記載の半導体装置。 ３、該半導体装置は、１トランジスタセルであり該第１
の電極は、電荷蓄積部であることを特徴とした請求範囲
第１項記載の半導体装置。 ４、上記基板上の低濃度不純物層は、基板上に形成され
たエピタキシャル層であることを特徴とした請求範囲第
１項記載の半導体装置。[Scope of Claims] 1. A first silicon substrate having an impurity of the same or opposite conductivity type and having a lower concentration than the substrate, provided on a silicon substrate having a first conductivity type and having impurities at a high concentration; layer, has a groove that penetrates the first layer from the surface and reaches the substrate, further has a first electrode in the groove, and at least one opposing electrode that forms a capacitance between the groove and the first electrode. A semiconductor device characterized in that an electrode is the substrate described above. 2. The semiconductor device according to claim 1, wherein the second counter electrode is provided in a direction opposite to the substrate with an insulating film interposed between the charge storage electrode and the substrate. 3. The semiconductor device is a one-transistor cell, and the first
2. The semiconductor device according to claim 1, wherein the electrode is a charge storage portion. 4. The semiconductor device according to claim 1, wherein the low concentration impurity layer on the substrate is an epitaxial layer formed on the substrate.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59204001A JPS6184053A (en) | 1984-10-01 | 1984-10-01 | Semiconductor device |
| US06/934,556 US4901128A (en) | 1982-11-04 | 1986-11-24 | Semiconductor memory |
| US07/452,683 US5214496A (en) | 1982-11-04 | 1989-12-19 | Semiconductor memory |
| US07/822,325 US5237528A (en) | 1982-11-04 | 1992-01-17 | Semiconductor memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59204001A JPS6184053A (en) | 1984-10-01 | 1984-10-01 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6184053A true JPS6184053A (en) | 1986-04-28 |
Family
ID=16483129
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59204001A Pending JPS6184053A (en) | 1982-11-04 | 1984-10-01 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6184053A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6187359A (en) * | 1984-10-05 | 1986-05-02 | Nec Corp | Semiconductor memory cell |
| JPS6249650A (en) * | 1985-08-28 | 1987-03-04 | Nec Corp | Semiconductor device |
| US4798794A (en) * | 1984-06-05 | 1989-01-17 | Kabushiki Kaisha Toshiba | Method for manufacturing dynamic memory cell |
| US5041887A (en) * | 1989-05-15 | 1991-08-20 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
| US5075248A (en) * | 1988-09-22 | 1991-12-24 | Hyundai Electronics Industries Co., Ltd. | Method of making DRAM having a side wall doped trench and stacked capacitor structure |
-
1984
- 1984-10-01 JP JP59204001A patent/JPS6184053A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4798794A (en) * | 1984-06-05 | 1989-01-17 | Kabushiki Kaisha Toshiba | Method for manufacturing dynamic memory cell |
| JPS6187359A (en) * | 1984-10-05 | 1986-05-02 | Nec Corp | Semiconductor memory cell |
| JPS6249650A (en) * | 1985-08-28 | 1987-03-04 | Nec Corp | Semiconductor device |
| US5075248A (en) * | 1988-09-22 | 1991-12-24 | Hyundai Electronics Industries Co., Ltd. | Method of making DRAM having a side wall doped trench and stacked capacitor structure |
| US5041887A (en) * | 1989-05-15 | 1991-08-20 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
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