JPS6053470B2 - Manufacturing method of semiconductor memory - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a semiconductor device including a capacitor formed on the surface of a semiconductor substrate as a circuit component, and particularly relates to a manufacturing method for improving the characteristics of a semiconductor MOS type memory cell. be.

[Background of the invention]

FIG. 3 is a diagram showing a cross-sectional structure of a conventional MOS type memory cell.

As shown in FIG. 3, an example in which the transfer gate electrode 5 and the storage gate electrode 4 overlap is electronics? [7]
77 page 2(b) (April 1976) (ElectrO
nicsAprill, 1976).

However, this technique does not describe at all the provision of an impurity layer to prevent leakage current. In Figure 3, 1
is a semiconductor substrate, 2 is an insulating film such as an oxide film, 3 is a diffusion layer, 4
, 5 is a gate electrode, 6 is a gate insulating film, and 7 is an insulating film.A voltage is applied to the gate electrode 4 to form an inversion layer 38 on the surface of the substrate 1. Memory information is stored in the capacity section.

By applying a voltage to the gate electrode 5, memory information is transferred to the capacitive portion. In a memory cell having such a conventional structure, the most problematic point is the so-called PN junction leakage current between the inversion layer 38 and the substrate 1 and the leakage current flowing through the surface of the substrate 1 under the gate of the gate electrode 5. The memory information stored in layer 38 will be lost. FIG. 4 is a sectional view showing another conventional example.

This technique uses an impurity layer 48 instead of the inversion layer 38. The gate electrodes 44 and 45 do not overlap, making it unsuitable for high integration, and also not providing a sufficient effect in preventing leakage current. The technology is disclosed in Japanese Patent Application Laid-open No. 50-125684.
It is disclosed in the publication No. In addition, although it is the same memory cell, the gate is integrated into a so-called CCRAM, and as a technology related to so-called CCRAM, ``Charge Coupled RAM Cell Concept'' by Al F Tasti et al.
E, Transactions on Electron Devices 231! C2l97 Rev. February. (ALF.TAS
CH “Thecharge-CoupledRAMCe
llCOcept” ■EEETR7VsJSACT
IONSONELETRONDEVICESl■0L.
ED-23, NO. 23FEBRUARY1976). However, it is clear that this technique is completely different from the present invention in which two gate electrodes are provided.

The above technique discloses a technique for integrally forming the gate electrode.

In particular, changing the potential by introducing impurities is disclosed. [Object of the Invention] An object of the present invention is to significantly improve the structure of the problems of the prior art.

That is, the present invention aims to increase the speed of operation by lengthening the information storage time and achieving higher integration.

[Summary of the invention]

In order to achieve the above object, the present invention provides impurity layers 8 and 9 in a self-aligned manner.

FIG. 1 shows the cross-sectional structure of a MOS type memory cell according to the present invention, and the present invention shows that impurity layers 8 and 9 are inserted under gate electrodes 4 and 5 in a self-aligned manner. It is a characteristic of

[Embodiments of the invention]

The structure and manufacturing method of the memory cell of the present invention will be explained below using examples.

FIG. 1 shows a device manufactured according to the invention, and FIG. 2 shows a manufacturing method according to the invention.

By forming the impurity layer 8 of a conductivity type different from that of the substrate 1, the PN junction leakage current can be reduced by one to two orders of magnitude, the memory information storage time can be lengthened, and the characteristics can be improved. In order to reduce the leakage current of the inversion layer, the impurity layer must not be depleted in the operating state of the memory. Therefore, the impurity layer Qd to be implanted to form the impurity layer has a voltage stored in the memory node and the impurity layer, V
The following relationship must be satisfied for M(v) and the substrate bias voltage, VBB(V). Here, ES: dielectric constant q of semiconductor substrate: unit charge NB: substrate impurity concentration In a memory using a normal Si substrate, NB=151
Use 5 pieces of about G-3, 1VM] 3 (v) ■B
Since the value of B≧−2(v) is used, the value of Qd is in the following range.

Qd≧2.5×10 11 (cl-2) In order to obtain a sufficient effect, the impurity concentration is preferably at least this level.

As a method for forming the impurity layer, techniques such as impurity ion implantation through SiO2, direct impurity ion implantation into the Si substrate 1, impurity diffusion, and diffusion from SiO2 can be used.

Furthermore, by forming an impurity layer 9 of the same conductivity type as the substrate, it is possible to provide a threshold voltage that can block leakage current flowing through the surface of the lower substrate 5 when no voltage is applied to the gate electrode 5.

Therefore, the memory information storage time can be lengthened and the characteristics can be improved. In other words, for example, if the information storage time becomes longer, the rewriting (refreshing) cycle can be lengthened.Therefore, the ratio of rewriting to the overall operation decreases.From the user's perspective, this reduces the operating speed. This is the same as an improvement in the speed of the circuit itself.Although miniaturization makes it possible to increase the speed of the circuit itself, miniaturization reduces the amount of information charge and therefore shortens the rewrite cycle.

Therefore, the structure of the present invention becomes important. Next, a second method for manufacturing a memory cell having the structure shown in FIG.
This will be explained using figures.

First, the substrate impurity concentration is 1015C711! Using a P-type substrate 10 of about -3, the surface is oxidized by the general LOCOS method to form an oxide film 11 of about 1 μm. Then 100
A gate insulating film (SiO2) 12 of about 0 A is formed in the storage section, and As ions of about 2.5×1011c7I-2 are ion-implanted through 12 to form a single N layer 13 (Figure a).
. POly-S of about 4000A is coated on the surface by CVD method.
Then, POly-Si is doped with phosphorus to reduce its resistance, and a storage gate electrode 14 is formed by ordinary photolithography. An oxide film of about 1000 Å is formed on the surface, an insulating film 15 is formed, and boron ions of about 4×10 11 d−2 are ion-implanted by a self-alignment method using 14 and 15 as masks to form a P+ layer 16 (Figure b). POly-Si having a thickness of about 4000 A is formed on the surface by CVD, and a transfer section gate electrode 17 is formed by photolithography. An N+ layer 18, which is a diffusion layer, is formed to a depth of about 0.5 PWL in a self-aligned manner using 17 as a mask (Figure c).

An insulating film 19 of about 5000 A is formed on the surface by CVD. Finally, holes are made in the insulating film 19 for taking out the electrodes, and metal electrodes 20 such as AI are formed (see figure d). In addition, 1
The formation of 3 may be performed by impurity diffusion from an impurity-doped insulating film, and the same can be done for the formation of 16. The insulating film between 14 and 17 has improved gate-to-gate breakdown voltage,
Alternatively, for the purpose of reducing the parasitic capacitance between 14 and 17,
It is also possible to insert a SiO2 film, a Si3N4 film, etc. using the D method. In addition to M, Sb or P can also be used as the impurity layer 13. The scope of implementation of the present invention is not limited to the above embodiments, but can also be implemented, for example, to a P-channel device using an n-type substrate.

Moreover, it can be used not only as a memory cell but also as a temporary information storage means or as a photodetection element of a photodetection semiconductor device. [Effects of the Invention] As explained above, the memory cell manufactured according to the present invention can improve memory information storage time by one to two orders of magnitude compared to conventional memory cells, and is extremely suitable for high integration. That is, a memory cell can be manufactured by a self-alignment method using the storage gate/electrode and the transfer gate electrode as a mask.

Therefore, speeding up of memory can also be achieved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a memory cell manufactured according to the present invention, FIG. 2 is a diagram showing a method for manufacturing a memory cell according to the present invention, and FIGS. 3 and 4 are diagrams showing a conventional memory cell. FIG.

Claims (1)

[Scope of Claims] 1. A method for manufacturing a semiconductor memory characterized by including the following steps. (a) Step of forming a thick oxide film on a semiconductor substrate. (b) Q_d≧√(2εs・qN_B)√(
｜V_M｜+｜V_B_B)・1/q(pcs cm＾-＾2
) Here, εs: dielectric constant q of semiconductor substrate: unit charge amount N_B: substrate impurity concentration Step of introducing an amount of an impurity having a conductivity type opposite to that of the semiconductor substrate. (c) A step of forming poly-Si on the semiconductor substrate to form a storage portion gate electrode. (d) A step of implanting ions into the entire surface of the substrate in self-alignment with the storage gate electrode to introduce an impurity having the same conductivity type as that of the semiconductor substrate. (e) A step of forming poly-Si on the entire surface and forming the transfer section gate electrode so that at least a part thereof overlaps with the storage section gate. (f) forming a diffusion layer by diffusing an impurity into the surface of the substrate in a self-aligned manner with the transfer section gate electrode to introduce an impurity of a conductivity type opposite to that of the semiconductor substrate; (g) A step of providing an insulating film over the entire surface of the semiconductor substrate, making holes for taking out electrodes in the insulating film, and forming metal wiring.