JPS59175157A - Metal insulator semiconductor type semiconductor memory device and manufacture thereof - Google Patents

Abstract

PURPOSE:To avoid the reduction of an active element region due to the lateral expansion of oxidation by a method wherein an electrode different from the capacitor part is provided on an insulation film provided between adjacent capacitor parts, and then such a voltage that the surface of Si comes to the state of accumulation is impressed on this electrode. CONSTITUTION:An insulation film 2 is formed on a P type Si substrate 1. The surface of the Si substrate 1 is coated with a photo resist, and P type layers 5 are selectively formed by ion implantation. After polycrystalline Si, it is left at regions between elements as electrodes 6. The part other than the capacitor part is covered with a photo resist, and then an N type impurity is implanted to the capacitor part. A P-N junction is formed in the Si substrate at said part, which can be used as a charge accumulated region, and then the charge accumulation capacitance of a memory cell increases together with the capacitance by the insulation film 2. Electrodes 10 are formed by adhering polycrystalline Si. Charge transfer gates 11 of polycrystalline Si are formed, an N type impurity layer 12 is formed by ion implantation, and a digit line 13 by metallic wiring is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to the configuration of a storage capacitor section of a semiconductor device having a storage function.

A memory device using an insulated gate field effect transistor that is widely used today is a so-called one-transistor type memory device, which is constituted by one transistor and a capacitor provided adjacent to the transistor.

In this memory device, the gate of the transistor is connected to the word line, one of the source and drain diffusion layers is connected to the digit line, and the presence or absence of charge accumulated under the capacitor gate corresponds to inversion information.

In recent years, as the capacity of memory devices has increased, elements have become smaller and the area of each memory cell has also tended to be smaller.

When miniaturizing a one-transistor type memory device, a reduction in charge storage capacity must be avoided as much as possible in order to facilitate information determination and maintain resistance to radiation.

In particular, with the miniaturization of devices, the ratio of insulating regions between active devices to the entire cell increases, making it extremely difficult to maintain charge storage capacity.

The present invention provides a method for preventing a reduction in the area of a capacitive part by reducing the area of an insulating region between active elements, thereby miniaturizing the element while maintaining normal memory function. It is.

In the present invention, instead of the conventional selective oxidation method, the inter-element region is formed by an insulated gate field effect transistor, and if the gate electrode of the transistor is a P-type semiconductor substrate in which the silicon surface is in an accumulation state, If the surface is P+
Leakage current between the elements is prevented by applying a voltage such that

According to the present invention, since the width of the inter-element side region is determined by the gate width of the transistor, it is possible to avoid a reduction in the active element area due to lateral inward spread of oxidation, which occurs in ordinary selective oxidation. Useful for expanding the area of the capacitor section.

Next, the content of the present invention will be explained in detail with reference to Examples.

As shown in FIG. 1, a thin insulating film 2 is formed on a P-type silicon substrate 1 to serve as an insulating film for a capacitor section. As the insulating film 2, a silicon nitride film, a two-layer insulating film in which a silicon nitride film is formed on a silicon oxide film, or the like is used. The film thickness ranges from several tens to hundreds of wafers. Next, the silicon substrate 1 except for the portions that should become the capacitive portion and the inter-element portion of the memory cell.
The surface of the substrate is covered with a photoresist 3, and a P-type layer 5 is selectively formed by ion implantation. When boron is used as an impurity, the appropriate ion energy is about 50 to 150 keV, and the implantation amount is about 1012 to 1018/1. Next, as shown in FIG. 2, after depositing polycrystalline silicon, a photo-etching process is performed to leave the polycrystalline silicon as electrodes 6 in the inter-element regions. Next, perform oxidation.

After the surface of the polycrystalline silicon is covered with an oxide film for insulation, the area other than the capacitive part is covered with a photoresist 7, and an n-type impurity is implanted into the capacitive part. When arsenic is used as an impurity, the energy is 50 to 150 keV and the implantation amount is 1013 to 10
Approximately 47d is appropriate. Through the above process, a pH junction is formed in the silicon substrate of the capacitive portion, which can be used as a charge storage region, and together with the capacitance due to the insulating film 2, the charge storage capacity of the memory cell increases. In addition, the threshold voltage value of the capacitor part decreases, and the voltage applied to the capacitor electrode can be lowered.Next, as shown in FIG. An electrode 10 is formed.Next, if necessary, after removing the insulating film on the silicon exposed at the surface, a new insulating film is formed to serve as a gate insulating film of the charge transfer portion of the memory cell. Next, as shown in FIG. 4, a charge transfer gate 11 made of polycrystalline silicon is formed, a thin n-type impurity layer 12 is formed by ion implantation, and a digit line 13 made of metal wiring is formed to complete the memory cell. In addition, in this structure, the polycrystalline silicon electrode 6 is connected to an independent metal electrode or a silicon substrate at the periphery of the cell array, and the silicon substrate surface is kept at a potential that causes an accumulation state. It will be done.

[Brief explanation of the drawing]

1 to 4 are cross-sectional views for detailed explanation of the present invention. In the same figure, 1...Silicon substrate (p type) V
2...Insulating film, 3...Photoresist, 4...Impurity ion (p type), 5...
・Impurity layer (p type), 6...polycrystalline silicon,
7... Photoresist, 8... Impurity ion (n type), 9... Impurity layer (n type), 1
0...-polycrystalline silicon, 11...polycrystalline silicon, 12... impurity layer (n type), 13
...Metal wiring, L...1 information unit. 61

Claims (2)

[Claims] (1) In a storage device whose information unit is one insulated gate field effect transistor on a silicon substrate and a capacitor provided adjacent to it, an insulating film is provided on the silicon substrate between adjacent capacitor parts. 1. An MIS type semiconductor memory device, comprising: an electrode different from an electrode of a capacitor section provided on the insulating film, and a voltage such that a silicon surface becomes in an accumulation state applied to the electrode. (2) A step of forming an insulating film on the surface of the silicon substrate, and selectively injecting impurities of the same conductivity type as the substrate into the silicon substrate in a region that includes at least a part of the capacitive part and the insulating part between adjacent capacitive parts. a step of providing an electrode on the insulating film in a region that includes at least a portion of the insulating portion between adjacent capacitance portions, and a step of providing an electrode on the insulating film in a region that includes at least a portion of the insulating portion between adjacent capacitance portions; manufacturing an MIS type semiconductor memory device in which an information unit is one insulated gate field effect transistor and a capacitance adjacent thereto, comprising the step of selectively introducing an impurity of a conductivity type opposite to that of the substrate. Method.