JP2803729B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and more particularly to a DRAM.
When applied to a semiconductor integrated circuit device having the (D ynamic R andom A ccess M emory) a technique effectively. [Prior Art] A memory cell of a DRAM is composed of an information storage capacitor element connected in series to one semiconductor region of a MISFET for selecting a memory cell. The gate electrode of the MISFET for selecting a memory cell is connected to a word line and controlled by the word line. The other semiconductor region of the MISFET for selecting a memory cell is connected to a data line. 1 [Mbi
In the DRAM having a large capacity of [t], the information storage capacitance element of the memory cell is configured in a planar structure. The information storage capacitor having the planar structure is configured by sequentially stacking an n-type semiconductor region as one electrode, a dielectric film, and a plate electrode as the other electrode. The MISFET for selecting a memory cell mainly includes a gate insulating film, a gate electrode, and a pair of high impurity concentration n-type semiconductor regions (one and the other semiconductor regions) which are a source region and a drain region. A DRAM in which a memory cell is formed by a planar-structured information storage capacitor element is disclosed in, for example, Japanese Patent Application Laid-Open No. 61-2470.
No. 69 is described. [Problems to be Solved by the Invention] The present inventor has found that the following problems occur before the development of a large-capacity DRAM. The source region and the drain region (one and the other semiconductor regions) of the memory cell selecting MISFET are formed by ion implantation with a high impurity concentration. That is, after the gate electrode is formed, the gate electrode is used as an impurity introduction mask, and an n-type impurity (As or P) is formed on the main surface of the semiconductor substrate.
Is introduced by ion implantation to form a source region and a drain region. The n-type impurity is introduced by ion implantation with a high impurity concentration of 10 ¹⁵ [atoms / cm ² ] or more. The introduction of high-concentration impurities by ion implantation frequently causes crystal defects in the main surface of the semiconductor substrate (actually, the well region). This crystal defect cannot be sufficiently recovered by heat treatment (annealing) in a subsequent step. As a result, the charge stored in the information storage capacitor leaks due to crystal defects to the semiconductor substrate side, and the information retention characteristics of the DRAM deteriorate. This deterioration of the information holding characteristic increases the frequency of refreshing, so that the power consumption of the DRAM increases. On the other hand, the other semiconductor region of the memory cell selection MISFET needs to reduce the contact resistance value with the data line (aluminum) in order to increase the information writing speed and the information reading speed. For this reason, the other semiconductor region is provided so that good ohmic characteristics can be obtained by contact with the data line.
It must be formed with a high impurity concentration, for example, a surface concentration of about 10 ²⁰ [atoms / cm ³ ]. It is an object of the present invention to provide a technique capable of improving the refresh characteristics of a memory cell and increasing the operating speed in a DRAM. Another object of the present invention is to achieve the above object,
An object of the present invention is to provide a technology capable of achieving high integration of AM. The above and other objects and novel features of the present invention are as follows.
It will become apparent from the description of the present specification and the accompanying drawings. [Means for Solving the Problems] Of the inventions disclosed in the present application, the outline of a representative one will be briefly described as follows. In a semiconductor integrated circuit device having a DRAM in which an information storage capacitance element is connected to one semiconductor region of a memory cell selection MISFET and a data line is connected to the other semiconductor region, one semiconductor of the memory cell selection MISFET is The region is formed by ion implantation with a lower impurity concentration than the semiconductor region of the MISFET constituting the peripheral circuit other than the memory cell, and the other semiconductor region of the memory cell selecting MISFET is
The low impurity concentration is formed by ion implantation and the high impurity concentration by thermal diffusion. [Operation] According to the above-described means, the occurrence of crystal defects on the substrate surface due to ion implantation is reduced, the leakage of electric charges serving as information stored in the information storage capacitor element is reduced, and the information retention characteristic is improved. As a result, the refresh characteristics of the DRAM can be improved, and the contact resistance between the other semiconductor region and the data line can be reduced, so that the operation speed of the DRAM can be increased. it can. Hereinafter, the configuration of the present invention will be described together with an embodiment in which the present invention is applied to a DRAM in which a memory cell is formed by a planar structure information storage capacitor. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and their repeated description will be omitted. [Embodiment of the Invention] (Embodiment I) A memory cell of a DRAM and an MISFET of a peripheral circuit according to Embodiment I of the present invention are shown in FIG. In FIG. 1, the memory cell is shown on the left and the MISFET of the peripheral circuit is shown on the right. As shown in FIG. 1, the memory cell of the DRAM is formed of a series circuit with an information storage capacitor C having a planar structure of an n-channel MISFET Qs for selecting a memory cell. The memory cell is formed on a main surface of ap ^-- type well region 2 provided on a main surface of an n ^-- type semiconductor substrate 1 made of single crystal silicon. An insulating film for separating elements (field insulating film) is formed on the main surface of the well region 2 between the semiconductor element (memory cell) forming regions.
3 and a p-type channel stopper region 4 are provided.
The element isolation insulating film 3 and the channel stopper region 4
The semiconductor device is configured to be electrically isolated. In the main surface portion of the memory cell forming region of the well region 2,
A p ⁺ -type potential barrier layer 5 is provided. The potential barrier layer 5 includes at least the information storage capacitor C
Although it is sufficient that it is provided below the formation region, in the present embodiment, it is provided substantially over the entire surface of the memory cell formation region. The potential barrier layer 5 mainly includes the semiconductor substrate 1,
A potential barrier is formed for minority carriers generated by the incidence of α-rays inside each of the well regions 2. That is, the potential barrier layer 5 is configured to prevent minority carriers from invading the information storage capacitive element C and prevent soft errors. Further, the potential barrier layer 5 is provided with an information storage capacitor C
Is configured to increase the amount of charge stored in the memory. The information storage capacitor C of the memory cell is formed by sequentially laminating an n ⁺ -type semiconductor region 6 as one electrode (lower electrode), a dielectric film 7, and a plate electrode 8 as the other electrode (upper electrode). It is configured. The information storage capacitance element C has a planar structure as described above. A power supply voltage of 1/2 V _CC is applied to the plate electrode 8. The power supply voltage 1 / 2V _CC is applied to the semiconductor region 6 and the plate electrode 8
Since the electric field strength between the electrodes between the electrodes can be reduced, the dielectric film 7 can be made thinner, and the charge storage amount of the information storage capacitor C can be increased. Power supply voltage 1 / 2V
_CC is an intermediate potential (about 2.5 [V]) between the circuit reference voltage V _SS (= 0 [V]) and the circuit power supply voltage V _CC (= 5 [V]). The plate electrode 8 is made of, for example, a polycrystalline silicon film into which an n-type impurity (As or P) for reducing a resistance value is introduced. The semiconductor region 6 is configured so that a potential ( _VSS or V _CC ) serving as information from the data line (20, DL) is applied through the memory cell selecting MISFETQs. The semiconductor region 6 is configured so that even when the plate electrode 8 is applied to a power supply voltage of 1/2 V _CC , charges serving as information can be reliably stored. When a power supply voltage of 1/2 V _CC is applied to the plate electrode 8, in the MIS capacitor, when the potential of the plate electrode 8 becomes lower than the threshold voltage, the depletion layer extends and a channel is not formed. No longer configured. The semiconductor region 6 is formed by implanting As (or P) having a medium impurity concentration in the range of about 1 × 10 ¹⁴ to 1 × 10 ¹⁵ [atoms / cm ² ] by ion implantation. 1 × 10
^{When the} semiconductor region 6 is formed by ion implantation with a high impurity concentration exceeding ¹⁵ [atoms / cm ² ], crystal defects due to the ion implantation remain in the semiconductor region 6 and the potential barrier layer 5. Since this crystal defect cannot be completely recovered even by heat treatment (annealing) after ion implantation, the information storage characteristic of the information storage capacitor C is deteriorated. When the semiconductor region 6 is formed by ion implantation with a high impurity concentration,
Since the oxidation rate of the surface of the semiconductor region 6 is increased, a silicon oxide film having a small thickness cannot be formed. Since this silicon oxide film is used as the dielectric film 7, the thick dielectric film 7 reduces the charge storage amount of the information storage capacitor C. If the semiconductor region 6 is formed by ion implantation with a low impurity concentration of less than 1 × 10 ¹⁴ [atoms / cm ² ], a depletion layer spreads in the semiconductor region 6 and the charge storage amount decreases. Therefore, the semiconductor region 6 is formed by ion implantation with a medium impurity concentration in the above-described range. The dielectric film 7 is composed of a silicon oxide film formed by oxidizing the surface of the semiconductor region 6 as described above. Further, the dielectric film 7 may be composed of a composite film in which a silicon oxide film and a silicon nitride film are overlapped. The information storage capacitor C is basically composed of the semiconductor region 6, the dielectric film 7, and the plate electrode 8 as described above.
The pn junction capacitance contributes to an increase in the charge storage amount. On the surface of the information storage capacitive element C, an interlayer insulating film 9 that is electrically separated from an upper conductive film is provided. The memory cell selection MISFETs Qs of the memory cells are formed on the main surface of the well region 2 (actually, the potential barrier layer 5). The MISFETs Qs are configured in a region surrounded by the element isolation insulating film 3 and the channel stopper region 4. The MISFETQs mainly includes a well region 2, a gate insulating film 10, a gate electrode 11, and a pair of n-type semiconductor regions 13 which are a source region or a drain region. The well region 2 is used as a channel forming region of the MISFETQs. Gate insulating film 10 is formed of a silicon oxide film formed by oxidizing the main surface of well region 2. Gate electrode 11 is provided on a predetermined upper portion of gate insulating film 10, and is formed of a polycrystalline silicon film into which an impurity for reducing a resistance value is introduced. A word line (WL) 11 formed in the same manufacturing process as the gate electrode 11 extends above the information storage capacitance element C with the interlayer insulating film 9 interposed therebetween. Also, the gate electrode 11 and the word line 11
A single layer of a high melting point metal film or a high melting point metal silicide film may be used. Further, the gate electrode 11 and the word line 11
May be formed as a composite film in which a refractory metal film or a refractory metal silicide film is stacked on a polycrystalline silicon film. One of the pair of semiconductor regions 13 connected to (integrated with) the semiconductor region 6 which is one electrode of the information storage capacitor C is formed by ion implantation with a low impurity concentration. I have. That is, one semiconductor region 13
Is the MISF of peripheral circuits such as decoder circuits other than memory cells
It is formed by ion implantation with a lower impurity concentration than the source region or the drain region of the ET. The one semiconductor region 13 is formed by ion implantation with a lower impurity concentration than the semiconductor region 6 which is one electrode of the information storage capacitor C. The one semiconductor region 13 is formed in a self-aligned manner mainly using the gate electrode 11, the plate electrode 8, and the isolation insulating film 3 as a mask for introducing impurities. In the DRAM of the present embodiment, one semiconductor region 13 is 1 × 10 ¹³ [atoms / cm ² ] or more and 1 × 10 ¹⁴ [atoms / cm ² ].
It is formed by ion implantation with a low impurity concentration within a range of less than [atoms / cm ² ]. The one semiconductor region 13 formed with this low impurity concentration has a resistance value of 1 to 2 [KΩ], but the ON resistance of the memory cell selecting MISFET Qs is several [KΩ].
There is no problem in the information writing operation and the information reading operation because there is a certain degree. The other semiconductor region (the side connected to the data line) 13 of the pair of semiconductor regions 13 is basically formed by ion implantation with a low impurity concentration (in the same manufacturing process) as one semiconductor region 13. Have been. At least a portion of the other semiconductor region 13 connected to the data line (actually, the intermediate conductive layer 17) is formed of the n ⁺ -type semiconductor region 17A having a high impurity concentration. The semiconductor region 17A is formed by introducing an n-type impurity by thermal diffusion from the intermediate conductive layer 17 connected thereto in a self-aligned manner. The intermediate conductive layer 17 is formed of, for example, a polycrystalline silicon film into which P (or As) is introduced at a high impurity concentration. The intermediate conductive layer 17 is connected to the semiconductor region 17A through a connection hole 16 defined by a side wall spacer formed on a side wall of the gate electrode 11. The semiconductor region 17A having a high impurity concentration has, for example, a surface concentration of 10 ²⁰ [atoms].
[ms / cm ³ ] or higher. The intermediate conductive layer 17 is configured such that a central portion is connected to the semiconductor region 17A and a peripheral portion extends above the gate electrode 11. The intermediate conductive layer 17 and the gate electrode 11 are electrically separated via the interlayer insulating film 12. The high impurity concentration semiconductor region 17A is mainly
It is configured to improve the ohmic characteristics of the third conductive layer 17 and the intermediate conductive layer 17 and to reduce the contact resistance value between them. A data line (DL) 20 is connected to the intermediate conductive layer 17 through a connection hole 18A formed in the interlayer insulating layer 18.
The data line 20 causes a mask misalignment in the manufacturing process with respect to the semiconductor region 17A, but since the central portion of the intermediate conductive layer 17 is connected to the semiconductor region 17A in a self-aligned manner, the intermediate conductive layer 17 is interposed. Thereby, the data line 20 and the semiconductor region 17A can be substantially connected in a narrow region between the gate electrodes 11. The data line 20 is formed of, for example, aluminum or an aluminum alloy to which Si or Cu is added. Above the data line 20, an interlayer insulating film 21 is interposed,
A shunt word line (WL) 22 is provided. Although not shown, the shunt word line 22 is connected to the word line 11 in a predetermined region, and is configured to reduce its resistance value. The shunt word line 22 is, for example, a data line.
It is formed of the same material as 20. Peripheral circuits, for example, n-channel MISFETQn of a decoder circuit
Are formed on the main surface of the well region 2. MISFETQn
Mainly consist of well region 2, gate insulating film 10, gate electrode
11, a pair of an n-type semiconductor region 13 and an n ⁺ -type semiconductor region 15 that are a source region and a drain region. The semiconductor region 13 of the MISFET Qn is formed by ion implantation with a low impurity concentration, similarly to the semiconductor region 13 of the MISFET Qs for memory cell selection. The semiconductor region 13 is a MISFET
A channel formation region side of the drain region of the Qn is adapted to form at a low impurity concentration, LDD (L ightly D oped
MISFETQn having a ( D rain) structure. The semiconductor region 15 is formed by ion implantation with a high impurity concentration. The semiconductor region 15 has a source resistance of MISFETQn,
It is formed with a high impurity concentration in order to reduce each of the drain resistances and increase the speed. Further, the semiconductor region 15 is formed by ion implantation in order to form the semiconductor region 15 in a self-aligned manner with respect to the gate electrode 11 for miniaturization and to enhance controllability of the impurity concentration. The semiconductor region 15 is 1 × 10 ¹⁵ [atoms / cm
² ] High impurity concentration (actually 10 ¹⁵ to 10 ¹⁶ [atoms / c
m ² ]). Wiring 20 is connected to each semiconductor region 15 of MISFETQn. The wiring 20 is formed in the same manufacturing process as the data line 20. A connection hole is provided at a connection portion between the wiring 20 and the semiconductor region 15.
An n ⁺ -type semiconductor region 19 having a high impurity concentration formed by introducing an n-type impurity through 18A is provided. This semiconductor area
Reference numeral 19 is mainly configured to prevent a short circuit between the wiring 20 and the well region 2 caused by misalignment of the mask in the manufacturing process. As described above, in the DRAM memory cell, one semiconductor region 13 of the memory cell selecting MISFETQs is formed by ion implantation with a lower impurity concentration than the MISFETQn semiconductor region 15 of the peripheral circuit other than the memory cell. MISF for selection
By forming the other semiconductor region 13 of the ETQs by the low impurity concentration ion implantation and the high impurity concentration thermal diffusion (semiconductor region 17A), generation of crystal defects on the substrate surface based on the high impurity concentration ion implantation , The leakage of electric charges serving as information stored in the information storage capacitor C can be reduced, and the information retention characteristics can be improved.
AM refresh characteristics can be improved,
The other semiconductor region 13 and the data line 20 (actually, the intermediate conductive layer
17) The contact resistance with DRAM can be reduced.
Operation speed can be increased. According to the basic research of the present inventors, the semiconductor region 13 formed by ion implantation with a low impurity concentration of less than 1 × 10 ¹⁴ [atoms / cm ² ] is generated on the main surface of the well region 2 due to the introduction of the impurity. As a result, the crystal defects can be sufficiently recovered by the heat treatment after the impurity is introduced. Further, since the pair of semiconductor regions 13 which are the source region and the drain region of the memory cell selecting MISFET Qs of the memory cell are formed with a low impurity concentration, the amount of impurities flowing under the gate electrode 11 can be reduced. , The effective channel length can be sufficiently ensured. Therefore, the short channel effect is prevented and the MISFET
Since the area of Qs can be reduced, the degree of integration of the DRAM can be improved. Further, by connecting the data line 20 to the other semiconductor region 13 (semiconductor region 17A) of the memory cell selecting MISFETQn of the memory cell with the intermediate conductive layer 17 interposed, the gate electrode 11 of the adjacent memory cell selecting MISFETQs is formed. Since the size between them (data line contact area) can be reduced,
The degree of integration of DRAM can be improved. Although not shown in FIG. 1, the peripheral circuit has a p-channel MI channel on the main surface of the semiconductor substrate 1 or the main surface of the n ⁻ -type well region.
An SFET is configured. Next, a specific method of manufacturing the DRAM will be briefly described with reference to FIG. 2 to FIG. 9 (cross-sectional views of main parts shown in respective manufacturing steps). First, an n ⁻ type semiconductor substrate 1 is prepared. Next, in the memory cell formation region and the n-channel MISFET formation region, the p ⁻ -type well region 2 is formed on the main surface of the semiconductor substrate 1. Next, an inter-element isolation insulating film 3 is formed on each of the main surfaces of the semiconductor substrate 1 and the well region 2 between the semiconductor element formation regions. In the peripheral circuit portion, a p-type channel stopper region 4 is formed in the main surface portion of the well region 2 under the inter-element isolation insulating film 3 by the same manufacturing process as the step of forming the inter-element isolation insulating film 3. Next, as shown in FIG. 2, ap ⁺ -type potential barrier layer 5 is formed on the main surface of the memory cell formation region in the well region 2. The potential barrier layer 5 is formed by implanting p-type impurities by high-energy ion implantation in the memory cell formation region. At this time, the p-type impurity is simultaneously formed on the main surface of the well region 2 under the element isolation insulating film 3. The mold channel stopper region 4 can be formed. In forming the potential barrier layer 5, the peripheral circuit formation region is covered with a mask for impurity introduction such as a photoresist film. Next, as shown in FIG. 3, the potential barrier layer 5 is formed in the region for forming the information storage capacitance element C of the memory cell.
The n ⁺ type semiconductor region 6 is formed on the main surface of the substrate. Semiconductor region 6
Form one electrode of the information storage capacitive element C. The semiconductor region 6 is formed by ion implantation with a medium impurity concentration as described above. Next, a dielectric film 7 is formed on the main surface of the semiconductor region 6. The dielectric film 7 is formed of, for example, a silicon oxide film formed by thermally oxidizing the main surface of the semiconductor region 6. Next, a plate electrode 8 is formed on the dielectric film 7. The plate electrode 8 is formed by introducing an n-type impurity into a polycrystalline silicon film deposited by CVD and performing predetermined patterning. By forming this plate electrode 8, the information storage capacitive element C is completed. Next, as shown in FIG. 4, an interlayer insulating film 9 covering the surface of the plate electrode 8 is formed. By the same manufacturing process as the process of forming the interlayer insulating film 9, the memory cell selecting MI
A gate insulating film 10 is formed on the main surface of the well region 2 in each of the formation regions of the SFET Qs and the n-channel MISFET Qn. Interlayer insulating film 9 is formed of a silicon oxide film obtained by oxidizing the surface of a polycrystalline silicon film. Gate insulating film 10 is formed of a silicon oxide film in which the main surface of well region 2 is oxidized. Next, a gate electrode 11 is formed on a predetermined upper portion of the gate insulating film 10 and an interlayer insulating film 12 is formed thereon, and the word line 11 and the interlayer insulating film 3 extending over the interlayer insulating film 9 and the isolation insulating film 3 are formed. The film 12 is formed. Gate electrode 11 and word line
Step 11 is formed by introducing an n-type impurity into a polycrystalline silicon film deposited by CVD and performing predetermined patterning. The interlayer insulating film 12 is formed of a silicon oxide film deposited by CVD, and the gate electrode 1
Patterning is performed in the same step as 1. Next, as shown in FIG.
An n-type semiconductor region 13 is formed on the main surface of the potential barrier layer 5 in the Qs formation region and on the main surface of the well region 2 in the n-channel MISFET Qn formation region. The semiconductor region 13 is formed by ion implantation with a low impurity concentration as described above, mainly using the gate electrode 11 (actually, the interlayer insulating film 12 or its etching mask) as a mask for introducing impurities. Next, a side wall spacer is formed on the side wall of the gate electrode 11.
Form 14. The sidewall spacers 14 can be formed by performing anisotropic etching such as RIE on a silicon oxide film deposited by CVD. Next, the gate insulating film 10 above the other semiconductor region 13 in the memory cell selection MISFET Qs formation region is removed, and a connection hole 16 is formed as shown in FIG. The connection hole 16 is formed in a region defined by the sidewall spacer 14. Next, an intermediate conductive layer 17 is formed on the interlayer insulating film 12 so as to be connected to the semiconductor region 13A through the connection hole 16. The intermediate conductive layer 17 is formed by adding n to a polycrystalline silicon film deposited by CVD.
It can be formed by introducing a pattern impurity and performing predetermined patterning. As shown in FIG. 7, the n-type impurity introduced into the intermediate conductive layer 17 is diffused into the main surface portion of the semiconductor region 13 by the heat treatment to form a high impurity concentration n ⁺ -type semiconductor region 17A. By forming the semiconductor region 17A, the MISFETQs for memory cell selection is completed. Next, as shown in FIG.
An n ⁺ type semiconductor region 15 is formed in the semiconductor region 13 in the SFET Qn formation region and in the main surface of the well region 2. The semiconductor region 15 is formed by ion implantation with a high impurity concentration as described above, mainly using the sidewall spacers 11 as an impurity introduction mask. By forming the semiconductor region 15, the n-channel MISFETQn is completed. Next, an interlayer insulating film 18 and a connection hole 18A are sequentially formed. Thereafter, in the n-channel MISFET Qs formation region of the peripheral circuit, an n-type impurity is introduced into the main surface portion of the semiconductor region 15 through the connection hole 18A to form an n ⁺ -type semiconductor region 19 having a high impurity concentration. Next, as shown in FIG. 9, a wiring 20 is formed through the connection hole 18A so as to be connected to the intermediate conductive layer 17 and to be connected to the data line 20 and the semiconductor region 19. Next, an interlayer insulating film 21 is formed above the data lines 20 and the wirings 20, and a shunt word line 22 is formed above the interlayer insulating film 21 as shown in FIG. By performing these series of manufacturing steps, the DRAM of this embodiment is completed. (Embodiment II) This embodiment II is a second embodiment of the present invention in which the isolation structure between the memory cells of the DRAM is changed. FIG. 10 (a cross-sectional view of a main part) shows a memory cell of a DRAM according to Embodiment II of the present invention and a MISFET of a peripheral circuit. As shown in FIG. 10, the DRAM of this embodiment has an insulating film 3A,
The information storage capacitor C of the memory cell is electrically isolated by the 3B and the potential barrier layer 5. As the insulating film 3A, for example, a silicon oxide film formed by thermal oxidation is used. Insulating film 3B
For example, a silicon nitride film deposited by CVD is used. The potential barrier layer 5 below the insulating films 3A and 3B is mainly used as an isolation region for increasing the threshold voltage of the parasitic MOS. The information storage capacitor C of the memory cell and the MISFETQs for selecting a memory cell of another memory cell adjacent in the direction in which the word line 11 extends are separated from the element isolation insulating film 3.
Is electrically isolated by The DRAM configured as described above can achieve substantially the same effects as the DRAM of the first embodiment. As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. Of course. For example, the present invention can be applied to a SRAM (S tatic RAM). That is, a semiconductor region serving as an information storage node of an SRAM memory cell is formed by ion implantation with a low impurity concentration, and a semiconductor region connected to a data line is formed by ion implantation with a low impurity concentration and thermal diffusion with a high impurity concentration. I do. [Effects of the Invention] Of the inventions disclosed in the present application, effects that can be obtained by typical ones will be briefly described as follows. The refresh characteristics of the DRAM can be improved, and the operation speed of the DRAM can be increased.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of a main part showing a memory cell of a DRAM according to Embodiment I of the present invention and a MISFET of a peripheral circuit. FIGS. 2 to 9 are specific examples of the DRAM. FIG. 10 is a cross-sectional view of a main part illustrating a manufacturing method for explaining a manufacturing method. FIG. 10 is a cross-sectional view of a main part showing a memory cell of a DRAM according to a second embodiment of the present invention and a MISFET of a peripheral circuit. In the figure, 2 ... well region, 5 ... potential barrier layer, 6,13,15,17A, 19 ... semiconductor region, 7 ... dielectric film,
8 plate electrode, 10 gate insulating film, 11 gate electrode or word line, 17 intermediate conductive layer, 20 data line or wiring, Qs MISFET for memory cell selection, Qn n
Channel MISFET, C ... Information storage capacitance element.

Claims (1)

(57) [Claims] In a method for manufacturing a semiconductor integrated circuit device, a first MISFET forming a memory cell is formed in a predetermined first region on a main surface of a semiconductor substrate, and a second MISFET forming a peripheral circuit is formed in a predetermined second region on the main surface. A first gate electrode in the first region and a second gate electrode in the second region.
Patterning gate electrodes, respectively; using the first gate electrode as a mask, forming a first impurity region having a predetermined impurity concentration by ion implantation in the first region, and using the second gate electrode as a mask, Forming a second impurity region having a predetermined impurity concentration by ion implantation into the two regions; forming sidewalls on side surfaces of the first gate electrode and the second gate electrode, respectively; Forming a third impurity region having a higher impurity concentration than the second impurity region by ion implantation in the second region, and forming a polycrystalline silicon layer connected to the surface of the first impurity region; An impurity is introduced into the first impurity region outside the sidewall by diffusion from the polycrystalline silicon layer, and the impurity concentration is higher than the first impurity region. The method of manufacturing a semiconductor integrated circuit device which comprises a step of forming a fourth impurity region. 2. 2. The method according to claim 1, wherein the polycrystalline silicon layer is connected to a bit wiring layer. 3. Forming the sidewall spacers on the first gate electrode and the second gate electrode during the first gate electrode and the second gate electrode patterning, respectively;
On each of the first gate electrode and the second gate electrode,
2. The method according to claim 1, wherein an insulating film provided during the first gate electrode and second gate electrode patterning steps is left.