JP2644783B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly, to a technology effective when applied to a semiconductor integrated circuit device that connects wiring to a semiconductor region.

[Conventional technology]

A memory cell of DRAM (D ynamic R andom A ccess M emory) is composed of a memory cell selecting MISFET and its one semiconductor region to be connected in series an information storage capacitor. A data line is connected to the other semiconductor region of the memory cell selection MISFET. The data lines are formed of an aluminum film or an aluminum alloy film to which Cu or Si is added.

The two memory cells arranged in the direction in which the data line extends integrally form (share) the other semiconductor region of each of the memory cell selecting MISFETs. That is, the area corresponding to the field insulating film that insulates and separates the other semiconductor region is eliminated, and the DRAM is highly integrated.

A DRAM having a large capacity which is being developed by the present inventors is configured as shown in FIG. 7 (a cross-sectional view of a main part of a memory cell). That, MISFET Q _S for memory cell selection, p monocrystalline silicon ^- is configured to mold the semiconductor substrate (or well region) primary face. MISFET Q _S for memory cell selection, a gate insulating film 2, the gate electrode 3, and a pair of n-type semiconductor regions 5 is a source region and a drain region.
Other semiconductor region 5 of the memory cell selecting MISFET Q _S is
It is connected to the data line 12 with the intermediate conductive film 8 interposed. The intermediate conductive film 8 is formed of a polycrystalline silicon film deposited by CVD, and has an n-type impurity for reducing a resistance value introduced therein. The intermediate conductive film 8 is connected to the other semiconductor region 5 in a self-aligned manner with respect to the gate electrode 3 through a connection hole 7 defined in a sidewall spacer 6 formed on the side wall of the gate electrode 3. The connection portion between the other semiconductor region 5 and the intermediate conductive film 8 in the memory cell selecting MISFET Q _S,
The n-type impurity introduced into the intermediate conductive film 8 is diffused to form an n ⁺ -type semiconductor region 9. Gate electrode 3 and intermediate conductive film 8 are electrically separated by interlayer insulating film 4. The data line 12 is connected to the intermediate conductive film 8 through a connection hole 11 formed in the interlayer insulating film 10. Above the data line 12, an interlayer insulating film 13 is provided.

The DRAM configured in this manner is a memory cell selection MISFET.
Q semiconductor region 5 (actually 9) of the _S can be alleviated mask misalignment in the manufacturing process of the data line 12 in the intermediate conductive film 8. That is, the intermediate conductive film 8 can reduce the area of the other semiconductor region 5 of the memory cell selecting MISFET by the amount corresponding to the mask misalignment amount.
There is a feature that the integration degree of AM can be improved.

The technology for connecting a polycrystalline silicon film to a semiconductor region in a self-aligned manner is described in Japan Journal of Applied
Physics, Vol 8, p35-p42.

[Problems to be solved by the invention]

The present inventor has found that prior to the development of the aforementioned DRAM, the following problems occur.

Intermediate conductive film 8 shown in FIG. 7, as the short-channel effect of the pn junction depth becomes deeper memory cell selecting MISFET Q _S of the semiconductor region 9 does not occur, the n-type impurity solid phase diffusion 10 ¹⁹
It was set to less than [atoms / cm ³ ]. In the case of ion implantation, the n-type impurity was introduced at a high concentration of about 10 ¹⁶ [atoms / cm ² ], but was introduced only into the surface layer of the intermediate conductive film 8. As a result of the analysis of the present inventor, the fact that the intermediate conductive film 8 thus formed forms an inflection point 14 at which the orientation of the crystal grain boundary changes particularly at the step portion is confirmed. The inflection point 14 serves as an entrance for replacing the silicon atoms of the intermediate conductive film 8 with the aluminum atoms of the data line 12, and the silicon inside the data line 12 near the contact portion between the intermediate conductive film 8 and the data line 12. A precipitate 15 was generated. Therefore, the data line
In addition to the increase in the resistance value of No. 12, there is a problem that the data line 12 is disconnected by the heat generated by the increase in the resistance value. The disconnection of the data line 12 lowers the electrical reliability of the DRAM.

An object of the present invention is to provide a technique capable of preventing a silicon precipitate from being generated inside a wiring in a semiconductor integrated circuit device in which a wiring is connected with a silicon film interposed in a semiconductor region. is there.

Another object of the present invention is to provide a manufacturing method for achieving the above object.

Another object of the present invention is to provide a technique capable of achieving the above object and improving the electrical reliability of a semiconductor integrated circuit device.

The above and other objects and novel features of the present invention are as follows.
It will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a typical invention disclosed in the present application is briefly described as follows.

A semiconductor integrated circuit device in which wiring is connected to a semiconductor region with a silicon film interposed therebetween, wherein an inflection point at which the orientation of a crystal grain boundary of the silicon film changes is eliminated.

Further, a polycrystalline silicon film is formed, a high-concentration impurity is introduced into the polycrystalline silicon film, and the polycrystalline property is destroyed to form an amorphous silicon film. And forming the amorphous silicon film into a single crystal silicon film to form the silicon film.

(Operation)

According to the above-described means, since a substitution reaction caused by the inflection point can be eliminated, formation of a silicon precipitate inside the wiring can be prevented, and a reduction in the resistance value of the wiring or disconnection of the wiring can be prevented. Prevention can be achieved. As a result, the electrical reliability of the semiconductor integrated circuit device can be improved.

Further, by forming the polycrystalline silicon film as a single crystal silicon film, a silicon film having no inflection point can be formed.

Hereinafter, the configuration of the present invention will be described together with an embodiment in which the present invention is applied to a DRAM in which a memory cell is formed by a planar structure information storage capacitor.

In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and their repeated description will be omitted.

(Example of the invention)

FIG. 1 is a sectional view of a main part of a DRAM according to an embodiment of the present invention.

A plurality of memory cells M shown in FIG. 1 are arranged in a matrix in a memory cell array (memory cell mat) of a DRAM employing a folded bit line system (a folded bit line system). The DRAM includes an n ^- type semiconductor substrate 20 made of single crystal silicon. The memory cell M is provided on a main surface of a p ^- type well region 21 formed on a main surface of a semiconductor substrate 20. Although not shown, an n ^- type well region is provided on the main surface of the semiconductor substrate 20 in the CMOS p-channel MISFET formation region.

The memory cell M is formed on the main surface of the well region 21 in a region defined (enclosed) by the field insulating film 22 and the p-type channel stopper region 23A. Field insulating film 22 is formed of a thick silicon oxide film in which the main surface of well region 21 is selectively oxidized. The channel stopper region 23A is formed on the main surface of the well region 21 below the field insulating film 22 in the memory cell array formation region. Field insulating film 22 and channel stopper region 23A
Are configured to electrically isolate the memory cells M from each other.

A p-type potential barrier layer 23B is formed on the main surface of the well region 21 below the memory cell M. The potential barrier layer 23B is provided under the entire surface of the memory cell M, that is, over the entire surface of the memory cell array. Basically, the potential barrier layer 23B only needs to be provided at least below the information storage capacitor C of the memory cell M.
The potential barrier layer 23B mainly constitutes a potential barrier for minority carriers generated by the incidence of α-rays inside each of the semiconductor substrate 20 and the well region 21. That is, the potential barrier layer 23B is configured to prevent minority carriers from invading the information storage capacitive element C and reduce the rate of occurrence of soft errors in the memory cell mode. Also, a potential barrier layer
23B is configured to increase the amount of charge stored in the information storage capacitive element C.

This potential barrier layer 23B is formed in the same manufacturing process as the channel stopper region 23A. P that defines the area of the MISFET constituting the peripheral circuit, for example, the decoder circuit
The mold channel stopper region is formed in substantially the same manufacturing process as the field insulating film 22, and is formed in a different manufacturing process from the channel stopper region 23A. That is, before or after forming the field insulating film 22, the potential barrier layer 23B and the channel stopper region 23A can be formed by introducing a p-type impurity by ion implantation and extending and diffusing the p-type impurity. it can.

The memory cell M is constituted by a series circuit of a MISFET for memory cell selection Q _S and the information storage capacitor C.

The information storage capacitive element C is configured by sequentially stacking an n-type semiconductor region 24 as one electrode (lower electrode), a dielectric film 25, and a plate electrode 26 as the other electrode (upper electrode). .

A power supply voltage of 1/2 V _CC is applied to the plate electrode 26. The power supply voltage 1 / 2V _CC is equal to the power supply voltage V _CC (for example, the circuit operating potential 5 [V]) and the reference voltage V _SS (the circuit ground potential 0).
[V]) (about 2.5 [V]). Since the power supply voltage of 1/2 V _CC can reduce the electrolytic strength between the electrodes between the semiconductor region 24 and the plate electrode 26, the dielectric film 24 is made thinner, and the charge storage amount of the information storage capacitor C is reduced. Can be increased. The plate electrode 26 is made of, for example, a polycrystalline silicon film into which an n-type impurity (As or P) for reducing a resistance value is introduced.

Through said semiconductor region 24 is the memory cell selecting MISFET Q _S, the information from the data line (DL) potential (V _SS -Vth
Or V _CC −Vth). The semiconductor region 24 is configured so that even when the plate electrode 26 is applied to the power supply voltage of 1/2 V _CC , charges serving as information can be reliably stored. The semiconductor region 24 is 1 × 10 ¹⁴ to 1
As (or P) with an impurity concentration of about × 10 ¹⁵ [atoms / cm ² ]
Is introduced by ion implantation.

The dielectric film 25 is composed of a silicon oxide film formed by oxidizing the surface of the semiconductor region 24. Further, the dielectric film 25 may be formed of a composite film in which a silicon oxide film and a silicon nitride film are overlapped.

The information storage capacitance element C is basically composed of the semiconductor region 24, the dielectric film 25 and the plate electrode 26 as described above, but the pn junction capacitance between the semiconductor region 24 and the potential barrier layer 23B is charged. This contributes to an increase in the amount of storage.

On the surface of the plate electrode 26 of the information storage capacitor C, an interlayer insulating film 27 that is electrically separated from the upper conductive film is provided.

Memory cell selecting MISFET Q _S of the memory cell M, the well region 21 (actually potential barrier layer 23B) are configured on a main surface of the. MISFET Q _S for memory cell selection is
It is configured in a region defined by the field insulating film 22 and the channel stopper region 23A. MI for memory cell selection
SFET Q _S is mainly well region 21, a gate insulating film 28, gate electrode 29, and a pair of n-type semiconductor regions 31 serving as source and drain regions.

It said well region 21 is used as a channel formation region of the memory cell selecting MISFET Q _S.

Gate insulating film 28 is formed of a silicon oxide film formed by oxidizing the main surface of well region 21.

The gate electrode 29 is provided on a predetermined portion of the gate insulating film 28 and is formed of a composite film in which a high melting point metal film or a high melting point metal silicide film is superposed on a polycrystalline silicon film into which an impurity for reducing the resistance value is introduced. Have been. A word line (WL) 29 formed in the same manufacturing process as the gate electrode 29 extends above the information storage capacitor C or the field insulating film 22 with the interlayer insulating film 27 interposed therebetween. It is configured. Further, the gate electrode 29 and the word line 29 may be formed of a single-layer polycrystalline silicon film, a high-melting-point metal film, or a high-melting-point metal silicide film.

One of the pair of semiconductor regions 31 connected to (integrated with) the semiconductor region 24 that is the lower electrode of the information storage capacitor C is formed by ion implantation with a low impurity concentration. . That is, one semiconductor region 31 is
It is formed by ion implantation with a low impurity concentration of about 1 × 10 ¹³ to 1 × 10 ¹⁴ [atoms / cm ² ]. Semiconductor region 31 of the one hand, 1-2 has a resistance value of [K.OMEGA.], Since the ON resistance of the memory cell selecting MISFET Q _S is the degree number [K.OMEGA.], The information writing operation and an information reading operation on the No problem.

The other semiconductor region 31 (the side connected to the data line 38) 31 of the pair of semiconductor regions 31 is basically formed by ion implantation with a low impurity concentration (in the same manufacturing process) as one semiconductor region 31. Is formed. As shown in FIGS. 1 and 2 (enlarged cross-sectional view of a main part), at least a portion of the other semiconductor region 31 connected to the data line (actually, the intermediate conductive layer 24) has a high impurity concentration of n ⁺ It is composed of a type semiconductor region 35. The semiconductor region 35 is formed by introducing an n-type impurity by thermal diffusion from the intermediate conductive film 34 connected thereto in a self-aligned manner. The semiconductor region 34 is formed with a high impurity concentration of, for example, about 10 ²⁰ to 10 ²¹ [atoms / cm ³ ] or more in surface concentration.

The intermediate conductive film 34 is connected to the semiconductor region 35 through a connection hole 33 defined by a sidewall spacer 32 formed on a side wall of the gate electrode 29. As will be described later in detail, the intermediate conductive film 34 is formed of a single-crystal silicon film formed from a polycrystalline silicon film into which P (or As), which is a high-concentration n-type impurity, is introduced. In the intermediate conductive film 34, there is no inflection point at which the orientation of the crystal grain boundary is changed, which is indicated by reference numeral 34A in FIG. Intermediate conductive film
34 and the gate electrode 29 are electrically separated by the interlayer insulating film 30.

A data line (DL) is connected to the intermediate conductive film through a connection hole 37 formed in an interlayer insulating film. The data line 38 causes a mask misalignment in the manufacturing process with respect to the semiconductor region 35, but since the central portion of the intermediate conductive film 34 is connected to the semiconductor region 35 in a self-aligned manner, the intermediate conductive film 34 is interposed. Substantially by data line 38
And the semiconductor region 35 can be connected in a narrow region between the gate electrodes 29 in a self-aligned manner. The data line 38 mainly includes, for example, aluminum or an aluminum alloy film 38B to which Si or Cu is added. In the present embodiment, the data line 38 is formed of a composite film in which an aluminum alloy film 38B is stacked on the refractory metal silicide film 38A. Refractory metal silicide film 38A is formed, for example, MoSi _2. The refractory metal silicide film 38A is formed to prevent an epitaxial layer from being stacked at a connection portion between silicon (for example, a source region and a drain region of a MISFET of a peripheral circuit) and the aluminum alloy film 38B, thereby preventing ohmic characteristics from deteriorating. Have been. Refractory metal silicide film 38A
Is formed of, for example, MoSi ₂ having a thickness of about 150 [Å], and the aluminum alloy film 38B is formed of, for example, Al- having a thickness of about 5000 [Å].
It is formed of 0.5% Cu-1.5% Si.

Above the data line 38, an interlayer insulating film 39 is interposed,
A shunt word line (WL) 40 is provided. Although not shown, the shunt word line 40 is connected to the word line 29 in a predetermined region, and is configured to reduce its resistance. The shunt word line 40 is, for example, a data line.
As in the case of 38, it is mainly composed of an aluminum film or an aluminum alloy film.

Next, a method of manufacturing the intermediate conductive film 34 will be briefly described with reference to FIGS. 3 to 6 (cross-sectional views of main parts in respective manufacturing steps).

First, the well region 21 (actually, the potential barrier layer
The main surface of the 23B) forming the MISFET Q _S for memory cell selection.
Thereafter, on the other semiconductor regions 31 of the memory cell selecting MISFET Q _S, to form a connection hole 33 which is defined by sidewall spacers 32.

Next, as shown in FIG. 3, a polycrystalline silicon film 34B is formed on the entire surface of the substrate including the upper portion of the interlayer insulating film 30 so as to contact (connect) the other semiconductor region 31 through the connection hole 33. The polycrystalline silicon film 34B has a low-temperature C of about 630 to 650 [° C].
It is deposited by VD, and its film thickness is formed at about 2000 to 3000 [3000]. The polycrystalline silicon film 34B forms the intermediate conductive film 34 described above.

Next, as shown in FIG. 4, a high concentration n-type impurity is introduced into the polycrystalline silicon film 34B. The n-type impurity is, for example, 10 ¹⁶
Using P (or As) with a high concentration of [atoms / cm ² ] or more,
It is introduced by ion implantation at an energy of about 90 [KeV]. The introduction of the n-type impurity can reduce the resistance value. Further, the n-type impurities can diffuse into the crystal grain boundaries of the polycrystalline silicon film 34B and cause distortion between the crystals, so that the crystals of the polycrystalline silicon film 34B can be broken.
This destruction of the crystal is entirely performed in the thickness direction of the polycrystalline silicon film 34B. As described above, when the crystal is broken by the introduction of the high-concentration n-type impurity, the polycrystalline silicon film 34B becomes an amorphous silicon film (a so-called amorphous silicon film) 34C. The amorphous silicon film 34C has at least a MISFET Q _S
Need only be formed at the connection between the other semiconductor region 31 and the polycrystalline silicon film 34B.

Further, the amorphous silicon film 34C may be formed by introducing an n-type impurity by solid-phase diffusion. When introducing an n-type impurity by solid phase diffusion, heat treatment at 850 to 900 [° C] and 10
Perform at a high concentration of ²⁰ [atoms / cm ³ ] or more.

Next, the amorphous silicon film 34C is patterned into a predetermined shape (the shape of the intermediate conductive film 34). This patterning is performed by anisotropic etching such as RIE.

Next, as shown in FIG. 5, the amorphous silicon film 34C is subjected to a heat treatment. Heat treatment is performed at a high temperature of about 900 to 1000 [° C.]. By this heat treatment, single crystal silicon is obtained. Grains are formed from a portion in contact with the other semiconductor region 31 of the memory cell selecting MISFET Q _S to the amorphous silicon film 34C,
Grain grows to increase its size, and a single-crystallized intermediate conductive film 34 can be formed. The low temperature
The polycrystalline silicon film 34B formed by CVD has a small grain size and easily forms an inflection point at which the orientation of a crystal grain boundary changes, but the single crystallized intermediate conductive film 34 does not have the inflection point.

By the heat treatment process for forming the intermediate conductive film 34, as shown in FIG.
Type impurity is thermally diffused into the principal surface portion of the other semiconductor region 31 of the MISFET Q _S for the selected memory cell, a high concentration of n ⁺ -type semiconductor region
35 can be formed.

Next, an interlayer insulating film 36 is formed, a connection hole 37 is formed, and a data line (see FIG. 2 for a detailed structure) 38 is formed as shown in FIG.

Next, as shown in FIGS. 1 and 2, an interlayer insulating film 39 and a shunt word line 40 are sequentially formed to complete the DRAM of this embodiment.

Thus, a polycrystalline silicon film 34B is formed, a high concentration n-type impurity is introduced into the polycrystalline silicon film 34B, and the polycrystalline property is destroyed to form an amorphous silicon film 34C. The inflection point at which the orientation of crystal grain boundaries changes is obtained by forming the intermediate conductive film 34 by performing a heat treatment on the crystalline silicon film 34C and forming the amorphous silicon film 34C on the single crystal silicon film (34). An intermediate conductive film 34 having no voids can be formed.

That is, the data line (wiring) 38 is connected to the semiconductor region 31 (actually, the semiconductor region 35) with the intermediate conductive film 34 interposed therebetween.
In the DRAM, by replacing the inflection point at which the orientation of the crystal grain boundary of the intermediate conductive film 34 changes, replacement of silicon atoms of the intermediate conductive film 34 with aluminum atoms of the data line 38 caused by the inflection point is performed. Since the reaction can be eliminated, the formation of a silicon precipitate inside the data line 38 is prevented, and the data line 38 is prevented from forming.
Can be reduced, or disconnection of the data line 38 can be prevented. This effect is the same not only in the memory cell array but also in the peripheral circuit connecting the wiring with the intermediate conductive film interposed in the semiconductor region. As a result, the electrical reliability of the DRAM can be improved.

As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and may be variously modified without departing from the gist of the invention. Of course.

For example, the present invention is not limited to a DRAM, but can be applied to a case where a wiring is connected to each of a source region and a drain region of a MISFET with an intermediate conductive film interposed in a MOS integrated circuit device.

Further, the present invention can be applied to a case where an aluminum wiring is connected with a silicon film interposed in an emitter region or the like in a bipolar transistor integrated circuit device.

〔The invention's effect〕

The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.

In the semiconductor integrated circuit device, the existence of the inflection point of the silicon film interposed between the semiconductor region and the wiring can be eliminated.

Further, the electrical reliability of the semiconductor integrated circuit device can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a main part of a DRAM according to an embodiment of the present invention, FIG. 2 is an enlarged cross-sectional view of a main part of the DRAM, and FIGS. FIG. 7 is an enlarged cross-sectional view of a main part of each manufacturing process for explaining a method of manufacturing the main part. In the figure, 20 ... semiconductor substrate, 21 ... well region, 31,35 ...
... Semiconductor region, 33,37 ... Connection hole, 34 ... Intermediate conductive film (silicon film), 38 ... Data line, Q _S ... Memory cell selective opening
MISFET, C... Are information storage capacitance elements, and M are memory cells.

Claims (2)

(57) [Claims] 1. A main surface of a single crystal silicon substrate is covered with an insulating film, and a semiconductor region formed inside the main surface is connected to a wiring mainly composed of an aluminum film or an alloy film thereof through a silicon film. A method of manufacturing a semiconductor integrated circuit device, comprising: forming a polycrystalline silicon film in contact with the semiconductor region through an opening in an insulating film formed on the main surface of the substrate;
Introducing a predetermined impurity into the polycrystalline silicon film, destroying the polycrystallinity of the polycrystalline silicon film to form an amorphous silicon film, and subjecting the amorphous silicon film to heat treatment, Converting the amorphous silicon film into a single-crystal silicon film from a portion in contact with the silicon film, and thereafter, patterning the silicon film so that a portion thereof remains on the insulating film around the opening. When,
A method of manufacturing a semiconductor integrated circuit device, comprising a step of connecting a wiring mainly composed of an aluminum film or an alloy film thereof to the patterned silicon film. 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said heat treatment is performed at a temperature of about 900 to 1000 [° C.].