JP2531345B2 - Semiconductor memory device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a structure of a static type semiconductor memory device in which a resistance load element and a switching transistor and a driver transistor are easily connected.

[0002]

2. Description of the Related Art A static semiconductor memory device (hereinafter referred to as an SRAM) has been particularly highly integrated in recent years, and an SRAM having a large capacity of, for example, 4 megabits has also appeared. The SRAM has a memory cell load means,
There are a type having a depletion load type cell formed of a depletion type MOS transistor and a type having a resistance load type cell formed of a resistance load element such as polycrystalline silicon (polysilicon). The latter is a resistance load type SRAM. Called. Since the resistance load type SRAM is easy to form polycrystalline silicon into a high resistance load element, it is particularly suitable for large capacity and high integration due to reduction of current consumption, and has tended to be adopted in recent years. .

FIG. 3 is a circuit diagram showing a general structure of a resistance load type memory cell. As shown in the figure, in the resistance load type memory cell, one end r1 of the resistance (high resistance) load element R, the drain Q1d of the first driver transistor (first transistor) Q1, and the second driver transistor (first Second transistor) Q2 gate electrode Q2g,
First switching transistor (third transistor)
A node a for electrically collectively connecting the source Q3s of Q3
There is one. Conventionally, in order to make these connections, FIG.
And the structure shown in FIG. 6 is adopted. FIG. 5 is a schematic plan view of a node a1 portion of a conventional resistance load type memory cell, and FIG. 6 is a VI-VI sectional view thereof.

In FIGS. 5 and 6, when the locos oxide film 2 and the gate oxide film of each transistor are formed on the P-type substrate 1, the drain 9 of the first transistor Q1 and the source 11 of the third transistor Q3 are formed. A part of the upper gate oxide film 4 is selectively removed using a lithography technique to provide a gate oxide film removal region 20. Next, when forming the gate electrode of the second transistor Q2, the drain 9 of the first transistor Q1 and the source 11 of the third transistor Q3 which form the gate oxide film removal region 20.
Are directly connected by the polycrystalline silicon 7 forming the gate electrode.

After that, the first insulating layer 13 is formed on the entire surface so as to cover the gate electrode 7 of the second transistor Q2, and the upper portion of the gate electrode 7 of the second transistor Q2 is formed by using an etching technique by photolithography. The contact hole 23 is opened. Next, when the high resistance load element 14 is formed of polysilicon, a polysilicon contact is also formed in the contact hole 23, so that the gate electrode 7 of the second transistor Q2 and the high resistance load element 1 are formed.
The node a1 is formed by connecting 4 and 4.

Next, a second insulating layer 15 is formed so as to cover the high resistance load element 14, and a contact hole 16 is opened by using an etching technique by photolithography. The other end r2 of the high resistance load element 14 and the first transistor Q
In order to connect the source Q1s of 1 to the power supply line,
A barrier metal 17 and a tungsten burying layer 18 are formed inside the contact hole 16.

The one end r3 of the other high resistance load element R shown in FIG. 3, the source Q4s of the second switching transistor Q4, the drain Q2d of the second driver transistor Q2, and the gate Q1g of the first driver transistor Q1. The connection structure is similar to the connection structure shown in FIGS.

Japanese Unexamined Patent Publication (Kokai) No. 2-79470 discloses another example of the connection structure of the node a1 of the SRAM as shown in the sectional view (FIG. 7) and the circuit diagram (FIG. 8) of the memory cell. There is. According to the known technique described in this publication, the high resistance load element is divided into two parts, a first resistance part R1 and a second resistance part R2, and a first layer formed of a semiconductor layer is formed on the insulating layer 24. A contact 2 that is made of a material having a higher specific resistance than that of the resistance portion 27 and the first resistance portion 27 and that forms a second resistance portion formed in the contact hole 26.
And 5 form a high resistance load element. This contact 25
Thus, the drain 9 of the first transistor Q1 is connected to the high resistance load element, and the gate electrode 7 of the second transistor Q2 is connected to the high resistance load element.

[0009]

According to the prior art shown above, the drain 9 of the first transistor Q1, the gate electrode 7 of the second transistor Q2, and the third transistor Q are used.
3 for connecting the source 11, the high resistance load element 14, and the aluminum wiring 19 to each other,
In order to selectively remove each of the first insulating layer 13 and the second insulating layer 15 whenever necessary, an etching process by three photolithography is adopted.

Further, in the known technique described in the above publication, in addition to the contact hole 26, the gate oxide film for selectively removing the drain 9 of the first transistor Q1 and the gate electrode 7 of the second transistor Q2 is selectively removed. , And the source 1 of the first transistor Q1 (not shown).
It is necessary to selectively remove the insulating layer in order to connect 0 to the wiring, and the etching process is also performed three times.

As described above, according to the conventional technique and the known technique described in the above publication, an insulating layer is provided for collectively connecting the diffusion layer of the transistor, the gate electrode, the high resistance load element, and the wiring in the memory cell portion of the SRAM. 3 selective removal steps are required. Due to the large number of processes, there is a problem that the manufacturing time and cost of the SRAM are increased.

In view of the above, according to the present invention, the number of steps for forming the collective connection portion of the memory cells is small, so that the manufacturing time and cost can be saved in the resistive load type S.
It is intended to provide a RAM.

[0013]

In order to achieve the above object, a semiconductor memory device of the present invention comprises four transistors formed on a semiconductor substrate and two resistive load elements formed above the transistors. In a static type semiconductor memory device provided in one memory cell, a diffusion layer of the first transistor, and a gate electrode of the second transistor formed on a gate oxide film covering a part of the diffusion layer. A first contact for collectively connecting one end of the first resistance load element formed on the first insulating layer covering the gate electrode with each other in a contact hole for the diffusion layer. Characterize.

[0014]

With the configuration including the first contact for collectively connecting the diffusion layer of the first transistor, the gate electrode of the second transistor, and one end of the high resistance load element in the contact hole for the diffusion layer, The selective removal step of the insulating film necessary for connection is only the selective removal step at the time of forming the contact hole for the diffusion layer, and the number of steps can be reduced.

[0015]

The present invention will be described in more detail with reference to the drawings. 1 and 2 are a cross-sectional view and a plan view, respectively, schematically showing the structure of a memory cell portion in a resistance load type SRAM forming a semiconductor memory device of a first embodiment of the present invention.
Note that FIG. 1 is a cross-sectional view taken along the line I-I of FIG. 2. In addition, FIG.
FIG. 3 is also a circuit diagram of the memory cell of the resistance load type SRAM shown in FIGS. 1 and 2. That is, the drain Q1 of the first driver transistor (first transistor) Q1 in FIG.
d, second driver transistor (second transistor)
A gate electrode Q2g of Q2, a source Q3s of a first switching transistor (third transistor) Q3, and
The structure of the connection node a1 that collectively connects one end r1 of the high resistance load element R is shown in FIGS.

The structure of the semiconductor memory device of the above embodiment will be described with reference to FIGS. 1 and 2 mainly by describing the manufacturing process thereof. After forming the locos oxide film 2 on the P-type substrate 1, the gate oxide film of each transistor is formed. Next, for example, polycrystalline silicon doped with phosphorus so as to have a sheet resistance of about 40 Ω / sq.
The gate electrode 6 is formed by growing it to a thickness of 0Å and patterning it using an etching technique by photolithography.
~ 8 are formed.

Next, for example, arsenic is added with an acceleration voltage of 70 keV,
Ions are implanted under the condition of a dose amount of 5E15 (1 / cm ² ) to form the source and drain of each transistor.
At this time, the gate oxide film 5 of the second transistor Q2 is interposed between the drain 9 of the first transistor Q1 and the gate electrode 7 of the second transistor Q2, and thus they are electrically insulated from each other. Has been done. Next, the first oxide film 13 is formed on the entire surface by the CVD method to a thickness of 1000 Å, for example.

After that, the sheet resistance is 1 teraΩ /
The high resistance load element 14 is formed by growing and forming polycrystalline silicon having a thickness of about □ to a thickness of about 1000 Å and patterning it by using an etching technique by photolithography.
To form. As shown in FIG. 1, patterning of the high resistance load element 14 and the gate electrode 7 of the second transistor Q2 is performed by patterning the gate electrode 7 of the second transistor Q2.
However, in the contact hole formed later, the high resistance load element 14 is exposed stepwise from below. The gate electrode 7 of the second transistor Q2 and the high resistance load element 14 are electrically insulated by the first insulating layer 13.

Next, the second insulating layer 15 is formed, and necessary contact holes 16 are opened by using an etching technique by photolithography. Contact hole 16
Are formed by selectively removing the first and second insulating layers 13 and 15 and the gate oxide film 5 at the same time. The two contact holes 16 shown in the drawing are respectively the drains of the first transistor Q1. And a part of the source 11 of the third transistor Q3 are exposed. Further, inside the one contact hole 16, a part of the gate electrode 7 of the second transistor Q2 and a part of the high resistance load element 14 are exposed, respectively.

Next, a barrier metal 17 composed of, for example, titanium and titanium nitride is formed on the entire surface, and further, for example, tungsten is grown and formed on the entire surface including the inside of the contact hole 16 by the CVD method to a thickness of about 8000 Å. Next, by removing the tungsten other than inside the contact hole 16 by anisotropic etching, a buried layer 18 of tungsten is formed. By using a tungsten material having a low specific resistance in this way, a contact having a low resistance value can be formed. After that, aluminum wiring 19 is formed by deposition and patterning.
To form electrical connections between the elements.

In the SRAM thus obtained, which constitutes the semiconductor memory device of the embodiment of the present invention, as shown in FIG. 1, the drain 9 of the first transistor Q1 and the gate of the second transistor Q2 are provided. Electrode 7 and high resistance load element 1
4 has a drain 9 of the first transistor Q1
Inside the contact hole 16 for electrical connection, the barrier metal 17 and the buried layer 18 of tungsten are electrically connected to the drain 9 of the first transistor Q1.
The source 11 of the third transistor Q3 and the buried layer 18 of tungsten are electrically connected by an aluminum wiring 19.

Incidentally, one end r3 of the other high resistance load element R shown in FIG. 3, the source Q4s of the second switching transistor (fourth transistor) Q4, the drain Q2d of the second driver transistor Q2, and the first The connection structure of the gate Q1g of the driver transistor Q1 is similar to the connection structure shown in FIGS.

FIG. 4 is a view similar to FIG. 1, showing the configuration of the semiconductor memory device of the second embodiment of the present invention. FIG.
The same reference numerals as those in FIG. 1 are adopted for the reference numerals of FIG. In the second embodiment, similarly to the first embodiment, the contact 18 for the drain 9 of the first transistor Q1 allows the gate electrode 7 of the second transistor Q2, the high resistance load element 14, and Connect the drains of one transistor Q1 together to the contact hole 16
The internal configuration is adopted. However, instead of connecting the aluminum wiring to the contact 18 on the drain 9 of the first transistor Q1, the connection between the contact 18 and the source of the third transistor Q3 is, for example, as shown in FIG. This is done by using the gate electrode of the second transistor Q2 and directly connecting the gate electrode 7 to the source of the third transistor Q3.

As described in the above embodiments, in the semiconductor memory device of the present invention, the drain of the first transistor Q1, the gate electrode of the second transistor Q2, the high resistance load element, and the Since we adopted a configuration in which the wiring is connected all at once with one contact,
The etching process by photolithography can be performed only once, and it is possible to reduce the etching process twice as compared with the conventional technique.

In the first embodiment described above, since the drain Q1d of the first transistor Q1 and the source Q3s of the third transistor Q3 are connected by the aluminum wiring, as compared with the connection using the gate electrode. Since it is possible to reduce the parasitic capacitance between the P-type substrate and the P-type substrate and the wiring resistance, the read / write speed of the memory cell is increased.

In the second embodiment, the drain Q1d of the first transistor Q1 and the source Q3s of the third transistor Q3 are connected using the gate electrode of the second transistor Q2. By doing so, although the read / write speed of the memory cell is reduced as compared with the first embodiment, it is possible to increase the degree of freedom in circuit design.

The structure shown in the above embodiment is a preferred embodiment of the present invention, and the present invention can be variously modified and modified from the above embodiment. Therefore, the present invention is not limited to the configurations of the above-described embodiments.

[0028]

As described above, according to the semiconductor memory device of the present invention, it is possible to reduce the manufacturing time and cost of the semiconductor memory device by reducing the step of selectively removing the insulating film.

[Brief description of drawings]

FIG. 1 is a sectional view of a memory cell portion of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a plan view of a memory cell portion of the semiconductor memory device of the embodiment of FIG.

FIG. 3 is a circuit diagram showing a configuration of a memory cell of an embodiment of the present invention and a general resistance load type semiconductor memory device.

FIG. 4 is a sectional view of a memory cell portion of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 5 is a plan view of a memory cell portion of a conventional semiconductor memory device.

6 is a VI-VI sectional view in the memory cell portion of FIG. 5;

FIG. 7 is a cross-sectional view of a memory cell portion of a known semiconductor memory device.

FIG. 8 is a circuit diagram showing a configuration of a memory cell portion of FIG.

[Explanation of symbols]

 Q1 to Q4 Transistors R, R1, R2 High resistance load element 1 Semiconductor substrate 2 Locos oxide film 3 to 5 Gate oxide film 6 to 8 Gate electrode 9 Drain of first transistor Q1 10 12 Source 13 First insulating layer 14 High resistance load element 15 Second insulating layer 16 Contact hole 17 Barrier metal 18 Tungsten embedded layer 19 Aluminum wiring

Claims (5)

(57) [Claims] 1. A static semiconductor memory device comprising, in one memory cell, four transistors formed on a semiconductor substrate and two resistance load elements formed on the transistors, wherein the first transistor Of the diffusion layer, a gate electrode of the second transistor formed on the gate oxide film covering a part of the diffusion layer, and a first insulating layer formed on the first insulating layer covering the gate electrode. A semiconductor memory device, comprising: a first contact for collectively connecting one end of the resistive load element within a contact hole for the diffusion layer. 2. The semiconductor memory device according to claim 1, wherein the first contact is formed as a buried layer of tungsten. 3. The semiconductor according to claim 1, wherein an upper end of the first contact is connected to a wiring layer formed on a second insulating layer that covers the resistance load element. Storage device. 4. The semiconductor memory device according to claim 3, further comprising a second contact that connects the wiring layer and a diffusion layer of the third transistor. 5. The semiconductor memory device according to claim 1, wherein the gate electrode is connected to a diffusion layer of the third transistor.