JP3247536B2 - Semiconductor memory device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic semiconductor memory device (DRAM), and more particularly to a dynamic semiconductor memory device having an improved memory cell structure having a trench capacitor and a vertical transistor.

[0002]

2. Description of the Related Art In recent years, the area of memory cells has been increasingly reduced with the increasing integration of DRAMs. In a DRAM cell currently used, one transfer transistor and one capacitor are arranged in a plane. However, even if the integration is further advanced and the cell area is to be reduced, it is difficult to reduce the cell area because the transistor and the capacitor each require a specific area.

On the other hand, there has been proposed a cross-point type cell structure in which a transfer transistor and a capacitor are vertically overlapped to realize a half area of the conventional cell structure with the same minimum processing size. However, in the case of this structure, when the cell area is reduced, the distance between the junction of the capacitor and the transistor becomes shorter, and it becomes difficult to electrically separate the cells.

Recently, as a method for compensating this point, a cell structure using a vertical thin film transistor as a transfer transistor has been proposed, as shown in FIG. 9, in which the channel region of the transfer transistor and the storage electrode of the capacitor are completely insulated from the substrate. Have been. In this cell structure,
Electrical separation between cells is maintained, and the cell area can be reduced.

In FIG. 9, 201 is a silicon substrate, 203 is a trench, 204 is a capacitor insulating film,
05 is a storage electrode, 206 is a gate insulating film, 207 is a gate electrode, 208 is an interlayer insulating film, 209 is a bit line contact, 210 is a bit line, 211 is a semiconductor thin film forming a channel of a transistor, 212 is a source or a drain, 213 indicates an insulating film.

However, this type of cell structure has the following problems. That is, in the cell structure of FIG. 9, a vertical thin film transistor formed in a trench is used as a transfer transistor. Since the channel region is insulated from the substrate, polycrystalline silicon or amorphous silicon is deposited on the insulating film using LPCVD or the like instead of single crystal silicon on the substrate. When a MOS transistor is formed on such a non-single-crystal silicon film, the characteristics are inferior to those formed on a single-crystal silicon, and in particular, a large leak current flows between the source and drain of the transistor. In this case, the memory stored in the capacitor cannot be held for a sufficient time. Therefore, it is extremely difficult to satisfy the specifications as the transfer transistor of the DRAM.

[0007]

As described above, conventionally, in a DRAM in which a memory cell is formed by using a trench capacitor and a vertical transistor, the leakage current of the transistor increases, which is a factor of deteriorating the element characteristics. Was.

The present invention has been made in consideration of the above circumstances, and has as its object to reduce the leakage current between the source and drain of a vertical transistor in a memory cell using a trench capacitor and a vertical transistor. It is another object of the present invention to provide a DRAM which can improve device reliability.

[0009]

In order to solve the above problems, the present invention employs the following configuration. That is, according to the present invention (claim 1), in a DRAM in which a memory cell is formed using a trench capacitor and a vertical transistor, a plurality of trenches formed on one main surface of a semiconductor substrate and a plurality of trenches are formed in these trenches. Except for the upper part of the trench, the storage electrode is formed buried via the capacitor insulating film. A single connection connected to the drain or source formed in contact to form the channel of the MOS transistor
A crystalline semiconductor thin film, a gate electrode which is buried through a gate insulating film above the trench in which the semiconductor thin film is formed, and is formed as a word line continuously formed in one direction, and one main surface of the semiconductor substrate. A conductor line serving as a bit line connecting the formed drain or source in a direction crossing the word line.

According to the present invention (claim 2), in the method of manufacturing a DRAM having the above structure, a thick oxide film is formed on a main surface of a semiconductor substrate of the first conductivity type with a portion of the substrate exposed by selective oxidation. After forming the transmural it from the oxide film
A plurality of trenches having a depth reaching the inside of the substrate through the trench, a capacitor insulating film is formed on each of the wall surfaces in the trenches, and a semiconductor film of the second conductivity type is buried halfway in the trench. A thin film semiconductor layer serving as a channel of a MOS transistor is deposited on the substrate, and then the thin film semiconductor layer is exposed when forming an oxide film.
Some solid phase epitaxial grown as a seed the contact portion, followed by removing an unnecessary portion of the thin film semiconductor layer and then forming a gate insulating film on the surface of the thin film semiconductor layer, and then a gate electrode is buried in the trench upper Then, a second conductivity type impurity region is formed in the semiconductor layer using the gate electrode as a mask, and then a bit line is connected to the impurity region.

Here, preferred embodiments of the present invention include the following. (1) A trench is formed on both sides of the opening of the insulating film,
The semiconductor thin film is continuous between these trenches. (2) A NAND cell is formed by connecting two or more memory cells in series, and one end of the NAND cell is connected to a conductor wiring (bit line). The semiconductor thin film is continuous in each NAND type cell. (3) As the substrate, an SOI substrate in which a single crystal semiconductor layer is formed on a semiconductor substrate with an insulating layer interposed therebetween is used. Solid phase epitaxial growth of thin film polycrystalline silicon as a seed.

[0012]

In order for a vertical thin film transistor formed in a trench to have sufficient characteristics as a transfer transistor of a DRAM, the channel layer of the thin film transistor may be monocrystallized. Therefore, in the present invention, a semiconductor substrate covered with an insulating film is brought into contact with a polycrystalline silicon layer or an amorphous silicon layer serving as a channel layer of a transistor in the vicinity of a trench, and solid-phase epitaxial growth is performed by using the seed as a seed. The channel layer is single-crystallized. Therefore, in a memory cell using a trench capacitor and a vertical transistor, the leak current between the source and the drain of the vertical transistor can be reduced, and the reliability of the device can be improved.

In the present invention, the connection between the transfer transistor and the storage electrode of the capacitor is formed in a self-aligned manner in the trench, and the connection with the bit line is made at the junction with the substrate that has been subjected to solid phase epitaxial growth. Will be Since silicon of the first conductivity type is used for the substrate used for the counter electrode of the capacitor and silicon of the second conductivity type is used for the impurity diffusion layer of the transistor and the storage electrode of the capacitor, the substrate and the channel layer are electrically insulated. Further, since a thick insulating film is formed between adjacent elements, leakage between bit line contacts due to a parasitic MOS transistor does not pose a problem.
Further, the single-crystallized semiconductor layer is subjected to appropriate patterning. That is, due to such solid phase epitaxial growth, electrical isolation between cells is achieved even when the transistor is in contact with the substrate.

When an SOI substrate is used, since the substrate and the channel layer of the transistor are not in contact with each other, the single crystal silicon layer and the channel layer are appropriately patterned to electrically separate cells. You.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 shows a DR according to a first embodiment of the present invention.
FIG. 2 is a plan view showing a schematic configuration of the AM, and FIG.
FIG. 3 is a sectional view taken along the line BB 'of FIG.

A plurality of trenches 4 are arranged in a matrix on the surface of a p-type silicon substrate 1. Substrate 1
A relatively thick insulating film 2 is formed on the surface of the semiconductor device, and an opening 3 is provided in a portion of the insulating film 2 adjacent to the trench 4. In the trench 4, a storage electrode 6 of polycrystalline silicon is buried through a capacitor insulating film 5 to a position deeper than the upper end of the trench.

Further, a semiconductor thin film to be a channel layer 7 is formed on the upper side wall of the trench 4 in which the recess remains without being buried. The semiconductor thin film 7 is formed not only on the side walls of the trench 4 but also on the substrate surface near the trench 4 and is in direct contact with the substrate surface at the opening 3 of the insulating film 2.
The semiconductor thin film 7 is to be single-crystallized by solid phase epitaxy using the opening 3 as a seed.

A gate insulating film 8 is formed on the surface of the channel layer 7.
A gate electrode 9 of polycrystalline silicon is formed through the gate electrode. The gate electrode 9 fills the upper part of the trench and is formed continuously in the word line direction, and connects adjacent trenches to form a word line. An insulating film 10 is formed on the surface of the gate electrode 9, and an interlayer insulating film 1 is formed on the entire surface.
1 is formed.

On the interlayer insulating film 11, a bit line 12 is formed in a direction orthogonal to the word line. The bit line 12 is connected to the n-layer (source or drain) on the substrate surface at the opening 3 of the insulating film 2. Further, an n-type layer 1 by LDD implantation is provided in a portion exposed to the opening 3.
3, 14 are formed.

Next, a method of manufacturing the DRAM of this embodiment will be described with reference to FIGS. First, as shown in FIG. 4A, an insulating film 2 by LOCOS is formed on a p-type silicon substrate 1 except for a portion serving as a seed 3 for solid phase epitaxial growth. Next, as shown in FIG. 4B, a trench 4 deep enough to reach the substrate 1 from the insulating film 2 immediately adjacent to the portion where the substrate 1 is exposed is formed by, for example, a reactive ion etching (RIE) method. I do.

Next, as shown in FIG. 5A, after the wall surface of the trench 4 is thermally oxidized to form a capacitor insulating film 5, an n-type polysilicon 6 serving as a storage electrode of the capacitor is formed in the trench 4. Is etched back so that the upper end of the polycrystalline silicon 6 is lower than the upper end of the trench 4. Next, as shown in FIG. 5B, a thin film of amorphous silicon or polycrystalline silicon to be the channel layer 7 of the transfer transistor is deposited, and solid phase epitaxial growth is performed at an appropriate temperature to form the channel layer 7 simply. Crystallizes. At this time, the channel layer 7 is
Since the opening 3 is in direct contact with the substrate 1, this portion is used as a seed for single crystallization by solid phase epitaxy.

Next, as shown in FIG. 6A, after removing unnecessary portions of the channel layer 7, a gate insulating film 8 is formed on the surface of the channel layer 7. Subsequently, after the gate polycrystalline silicon 9 is deposited, patterning is performed, and LDD implantation is performed to form the n-type layers 13 and 14. Further, a protective insulating film 10 is formed so as to cover gate polycrystalline silicon 9. Next, as shown in FIG. 6B, the interlayer insulating film 11 is formed.
Then, a contact hole for making contact between the transistor and the bit line 12 is opened corresponding to the position of the opening 3 in the insulating film 2. 1 to 3 by depositing the bit line 12 and performing patterning.
The structure shown in FIG.

As described above, according to this embodiment, a memory cell is constituted by using a trench capacitor and a vertical transistor, and can be operated as a DRAM as in the conventional device shown in FIG. In this case, since the semiconductor thin film serving as the channel layer 7 of the vertical transistor is monocrystallized by solid phase growth from the substrate surface, the leakage current between the source and drain of the vertical transistor can be reduced, and the device reliability can be reduced. It is possible to improve the performance.

Further, in this embodiment, the connection between the transfer transistor and the storage electrode 6 of the capacitor is formed in a self-aligned manner in the trench 4, and the connection with the bit line 12 is made with the substrate on which the solid phase epitaxial growth has been performed. Joint 3 of
Done in Since p-type silicon is used for the substrate 1 used for the counter electrode of the capacitor and n-type silicon is used for the impurity diffusion layer of the transistor and the storage electrode 6 of the capacitor, the substrate 1 and the channel layer 7 are electrically insulated. In addition, a thick insulating film 2 is formed between adjacent elements, and leakage between bit line contacts due to a parasitic MOS transistor does not pose a problem. Further, even if the transistor and the substrate are in contact with each other for the purpose of solid phase epitaxial growth, electrical isolation between cells is achieved. (Embodiment 2) FIG. 7 is a block diagram of a second embodiment of the present invention.
FIG. 2 is a cross-sectional view illustrating an element structure of a RAM. 1 to 3 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In this embodiment, two or more (four in the figure) memory cells described in the first embodiment are connected in series to form a NAND cell, and a bit line is connected to one side of the NAND cell. 12 was contacted. In this case, the number of contacts between the bit line 12 and the cell is the first.
Less than the embodiment. Therefore, the same effect as that of the first embodiment can be obtained, and the number of bit line contacts can be reduced, so that high integration can be achieved.

In this embodiment, since the channel layers of the four cells constituting the NAND cell are continuous, the opening 3 of the insulating film 2 is used as a seed to start with the channel layer closer to the bit line contact. Single crystallization is sequentially performed by solid phase epitaxy on the channel layer farther from the bit line contact. (Embodiment 3) FIG. 8 is a block diagram of a third embodiment of the present invention.
FIG. 2 is a cross-sectional view illustrating an element structure of a RAM. 1 to 3 are denoted by the same reference numerals, and detailed description thereof will be omitted.

This embodiment differs from the first embodiment in that:
Instead of a normal silicon substrate, a single crystal silicon layer 23 is formed on a silicon substrate 21 with an insulating film 22 interposed therebetween.
That is, the OI substrate 20 is used.

When such an SOI substrate 20 is used, since the silicon substrate 21 and the channel layer 7 of the transistor are not in contact with each other, by appropriately patterning the single crystal silicon layer 23 and the channel layer 7, the cell There is an electrical separation between them. At this time, the insulating film 2 by the selective oxidation as in the first embodiment is unnecessary. Further, since the channel layer 7 is in contact with the single-crystal silicon layer 23, it can be single-crystallized by solid phase epitaxy as in the first embodiment. Therefore, the same effects as in the first embodiment can be obtained.

The present invention is not limited to the above embodiments. In the embodiment, an opening serving as a seed portion for solid phase growth is provided in a region adjacent to the trench. However, the present invention is not limited to this, and the position of the seed portion can be appropriately changed. For example, a large seed portion may be provided in a stripe shape at the end of the element formation region. Further, a seed portion may be provided for each predetermined pitch of the memory cells. Further, the configuration of the transfer transistor and the capacitor constituting the memory cell is as follows.
The configuration is not limited to those shown in FIGS. 2, 7, and 8, but may be changed as appropriate as long as it has a vertical thin film transistor and a trench capacitor. In addition, various modifications can be made without departing from the scope of the present invention.

[0030]

As described above in detail, according to the present invention, the channel layer of a vertical thin film transistor in a trench in which a channel layer is insulated from a substrate is formed by solid phase epitaxial growth using a substrate single crystal as a seed. Crystallized D
A transfer transistor of a RAM can be formed. Therefore, it is possible to reduce the leakage current between the source and the drain of the vertical transistor and to realize a DRAM that can improve the reliability of the device.

[Brief description of the drawings]

FIG. 1 is a plan view showing a schematic configuration of a DRAM according to a first embodiment.

FIG. 2 is a sectional view taken along line AA ′ of FIG.

FIG. 3 is a sectional view taken along line BB ′ of FIG. 1;

FIG. 4 is a sectional view showing the manufacturing process of the first embodiment.

FIG. 5 is a sectional view showing the manufacturing process of the first embodiment.

FIG. 6 is a sectional view showing the manufacturing process of the first embodiment.

FIG. 7 is a sectional view showing an element structure of a DRAM according to a second embodiment.

FIG. 8 is a sectional view showing an element structure of a DRAM according to a third embodiment.

FIG. 9 is a sectional view showing an element structure of a conventional DRAM.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 p-type silicon substrate 2 LOCOS insulating film 3 opening (seed part) 4 trench 5 capacitor insulating film 6 polycrystalline silicon (storage electrode) 7 channel layer (semiconductor thin film) 8 gate insulating film 9 Gate electrode (word line) 10 ... Protective insulating film 11 ... Interlayer insulating film 12 ... Bit line 13,14 ... LDD implant region (n-type layer) 20 ... SOI substrate 21 ... Silicon substrate 22 ... Insulating film 23 ... Single crystalline silicon layer

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/108 H01L 21/8242 JICST file (JOIS)

Claims (2)

(57) [Claims] A plurality of trenches formed on one principal surface of a semiconductor substrate, storage electrodes respectively buried in the trenches via a capacitor insulating film except for an upper portion of the trench, and Each is formed on the side wall via an insulating film, and the lower end is connected to the storage electrode,
A single-crystal semiconductor thin film having an upper end connected to a drain or a source formed in contact with one main surface of the semiconductor substrate to form a channel of a MOS transistor; and a gate insulating film over a trench in which the semiconductor thin film is formed. A gate electrode, which is formed as a buried word line and is formed continuously in one direction, is connected to a drain or source formed on one main surface of the semiconductor substrate in a direction intersecting the word line. A semiconductor memory device comprising: a conductor wiring serving as a bit line. 2. A process in which the first conductivity type portion of the substrate by selective oxidation on the main surface of the semiconductor substrate to form an oxide film in a state of being exposed, the interior of the substrate therethrough from above the oxide film Forming a plurality of trenches having a depth reaching the surface, forming capacitor insulating films on respective wall surfaces in these trenches, embedding a second conductivity type semiconductor film halfway in the trenches, Depositing a thin film semiconductor layer serving as a channel of a MOS transistor on a substrate, and a substrate exposing the thin film semiconductor layer when forming the oxide film
Solid-phase epitaxial growth using a contact portion with a part of the thin-film semiconductor layer as a seed, removing an unnecessary portion of the thin-film semiconductor layer, forming a gate insulating film on the surface of the thin-film semiconductor layer, Burying a gate electrode in the semiconductor layer, forming a second conductivity type impurity region in the semiconductor layer using the gate electrode as a mask, and connecting a bit line to the impurity region. Of manufacturing a semiconductor memory device.