JPH0654801B2 - Semiconductor memory cell and manufacturing method thereof - Google Patents

Description

TECHNICAL FIELD The present invention relates to a semiconductor memory cell suitable for application to a highly integrated semiconductor memory and a manufacturing method thereof.

[Conventional technology]

A semiconductor memory cell composed of one transistor and one capacitor (hereinafter abbreviated as 1T cell) has few constituent elements, and the memory cell area can be easily miniaturized.
It is widely used as a memory cell for highly integrated semiconductor memory. The problems of the conventional semiconductor memory cell will be described below using the 1T cell.

The output voltage from the 1T cell is proportional to the value of the capacitor (hereinafter referred to as the cell capacitor) forming the 1T cell,
In order to guarantee stable operation even with high integration, the cell capacitor value must be sufficiently large. Therefore, in order to highly integrate the 1T cell, a cell capacitor having a small area and a sufficient capacitor value is required. Conventionally, as such a cell capacitor, a 1T cell has been proposed in which a capacitor formed in a groove is used as a constituent element.

[Problems to be solved by the invention]

However, in the conventional trench capacitor, it is necessary to increase the distance between the capacitors in order to insulate the capacitors between the adjacent memory cells. Therefore, even if the memory cell itself can be made small, the area of the element isolation region for insulation becomes large and it is difficult to reduce the size of the memory as a whole.

An improved trench capacitor structure has also been proposed to facilitate isolation between cell capacitors. However, in the conventionally proposed improved groove capacitor, it is necessary to process the electrode conductor and the insulator inside the groove. However, as the degree of integration of memory increases, the opening of the groove tends to become narrower and its depth tends to become deeper. Therefore, the 1T cell including the improved groove capacitor, which requires processing inside the groove, as a constituent element has problems in reproducibility in processing and reliability of the groove capacitor itself.

Although the problems of the semiconductor memory cell have been described above by taking the 1T cell as an example, these problems also apply to other semiconductor memory cells having a cell capacitor.

[Object of the Invention]

An object of the present invention is to easily insulate between cell capacitors of adjacent memory cells and to eliminate processing in the groove, so that reproducibility in processing and reliability of the groove capacitor itself can be improved. Another object of the present invention is to provide a semiconductor memory cell having a structure of a cell capacitor that can be used.

Another object of the present invention is to provide a manufacturing method by which the above semiconductor memory cell structure can be easily obtained.

[Means for solving problems]

A semiconductor memory cell according to the present invention includes: a plurality of grooves formed on a surface of a substrate; a first insulator film formed inside these grooves; and a plurality of grooves connected to the first insulator film. Formed on the first conductor film, a second insulator film formed on the first conductor film, and a second conductor formed on the second insulator film. A film, a third insulator formed on a side surface of the first conductor film, and a fourth insulator made of a different material from the third insulator formed on the second conductor film. A body film, a switching transistor, and a third conductor film that connects the one conducting electrode of the switching transistor and the second conductor film to each other.

A method of manufacturing a semiconductor memory according to the present invention includes a step of forming a plurality of grooves on a surface of a substrate, a step of forming a first insulator film inside these grooves, and a step of forming the first insulating film of the plurality of grooves. Forming a first conductor film, a second insulator film, and a second conductor film on the body film in order, and forming a third insulator on a side surface of the first conductor film. And a step of forming a fourth insulator film made of a material different from that of the third insulator on the second conductor film, and removing a part of the fourth insulator film. Exposing the second conductor film, forming a third conductor film in contact with the exposed portion of the second conductor film, and cutting the second conductor film And a step of performing.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

The first (a) and (b) are a plan view and a sectional view showing a structure of an embodiment of a semiconductor memory cell of the present invention. Fig. 1 (b)
The sectional view of is cut open at AA 'in the plan view of FIG. 1 (a). In FIG. 1, 101 is a P-type silicon crystal substrate, 103 is a groove portion, 104 is a silicon oxide film, 105, 107, 10
7 ', 111, 111', 114, 114 ', 116 are conductor films, 106, 1
10, 110 , 110 ' , 113, 115 are insulator films, 108 is a filling material for the groove, 109 is a side insulator, 112 is an N-type silicon region, 117
Is a boundary between the active region and the inactive region, 118 is a contact hole,
Are shown respectively. In the plan view of FIG. 1A, some lines are omitted in order to avoid making the drawing unclear.

The semiconductor memory cell shown in FIG. 1 is a MOSFET having a conductor film 111 as a gate electrode, an insulator film 110 as a gate insulator film, a P-type silicon crystal substrate 101 as a substrate, and two N-type silicon regions 112 as current-carrying electrodes. And a cell capacitor having the conductor film 105 as a plate electrode, the conductor film 107 as a charge storage electrode, and the insulator film 106 as a capacitive insulator film, and a conductor connecting one of the conducting electrodes 112 and the conductor film 107. Membrane 114 and energizing electrode 112
Of bit lines 116 connected to the other. The conductor film 111 serves also as a word line together with the gate electrode of the MOSFET, and the plate electrode 105 is connected to the power supply. 107 ', 11
The primed portions such as 0 ', 111' and 114 'indicate corresponding portions of adjacent memory cells.

For example, the following materials can be used as materials for the conductors and insulators used in the embodiment of FIG.
Lindove polysilicon films as the conductor films 105, 107 and 114, a composite film of silicon oxide and silicon nitride as the insulator film 106, in-doped polysilicon as the filler 108, silicon nitride as the side surface insulator 109, and an insulator film 110. , 110 , 1
13 is a silicon oxide film, the conductor film 111 is a silicide film, the insulator film 115 is a glass film, the conductor film 116 is an aluminum film, and the like.

In the cell capacitor of the semiconductor memory cell of the present invention, most of the charge storage electrodes 107 are the insulator films 106, 110 , 113, 11
Surrounded by 5. Therefore, it is easy to insulate between the capacitors of the adjacent memory cells, and the interval between the capacitors can be reduced to its limit by reducing the interval between the charge storage electrodes 107 as much as possible.

In the semiconductor memory cell of the present invention, the shapes of the electrode conductors and insulators inside the trenches are the same as when they were buried in the trenches. Therefore, it is not necessary to process the electrode conductor or insulator inside the groove.

In the semiconductor memory cell of the present invention, the capacitor electrode is formed in the groove. Therefore, even if the memory cell area becomes small, by increasing the groove depth, the capacitor electrode area can be kept large independently of the memory cell area.

FIG. 2 is a process chart showing an embodiment of a method of manufacturing a semiconductor memory cell according to the present invention. The structure of the embodiment of the semiconductor memory cell of FIG. 1 can be obtained by this embodiment of the manufacturing method.

As shown in FIG. 2A, a P-type silicon crystal substrate 201
After forming the insulator film 202 on the top, the groove 203 is formed by anisotropic etching.

Next, as shown in FIG. 2 (b), the substrate surface is oxidized in the state of FIG. 2 (a) to form a silicon oxide film 204 (at this time, the silicon oxide film 202 is slightly thickened). Becomes a part of the silicon oxide film 204), a phosphorus-doped polysilicon film 205, a composite film 206 of silicon oxide and silicon nitride, and a phosphorus-doped polysilicon film 207 are respectively formed, and non-doped polysilicon 208 is filled in the remaining groove. To do.

Next, as shown in FIG. 2C, after removing the portion of the substrate 201 where the MOSFET is formed, a silicon nitride film 209 is formed by a chemical vapor deposition method. In this state, the silicon nitride film 209
Is etched by an anisotropic etching method, as shown in FIG.
5, the silicon nitride 209 'remains only on the side surfaces of the three-layer film of the composite film 206 and the phosphorus-doped polysilicon film 207. As described above, the reason why silicon nitride can be left only on the side surface is that if a silicon nitride film is formed by a chemical vapor deposition method at the step portion such as between the three-layer film and the silicon surface, the step portion becomes thicker. Silicon nitride is formed.

Next, as shown in FIG. 2E, after forming a gate oxide film 210 forming a MOSFET, a silicide film 211 for a gate electrode, and an N-type diffusion region 212 serving as a conducting electrode, a silicon oxide film 213 is formed. To do. Then, one N-type diffusion region 2
Part of 12 and part of the phosphorus-doped polysilicon film 207 are exposed to form a phosphorus-doped polysilicon film 214 connecting them. At this time, phosphorus-doped polysilicon film 2
05, the composite film 206, the 3 layer of phosphorus-doped polysilicon film 207, a silicon oxide film 210 corresponding to the gate oxide film 210,
Silicide film 2 corresponding to the gate electrode silicide film 211
11 'is formed.

After that, the phosphorus-doped polysilicon film 207 is cut between adjacent memory cells to form a glass film and an aluminum film, and the structure of the semiconductor memory cell of FIG. 1 is obtained.

In the method of manufacturing a semiconductor memory cell according to the present invention whose embodiment is shown in FIG. 2, the phosphorus-doped polysilicon film 207 is cut between adjacent memory cells to insulate the capacitors of adjacent memory cells from each other. You can Therefore, the capacitors of the adjacent memory cells can be brought close to each other up to the limit of the processing technology.

In the method of manufacturing a semiconductor memory cell according to the present invention whose embodiment is shown in FIG. 2, as shown in FIG.
An insulator film, a conductor film, and a filling material are continuously formed in the formed groove to fill the groove. Therefore, there are problems in reproducibility in processing and reliability of the groove capacitor itself. No machining of electrode conductors or insulators inside the groove is required.

In the method of manufacturing a semiconductor memory cell according to the present invention whose embodiment is shown in FIG. 2, as shown in FIG.
When the phosphorus-doped polysilicon film 214 is formed to connect the phosphorus-doped polysilicon film 207 and one of the N-type diffusion regions 212, the phosphorus-doped polysilicon film 214 and the phosphorus-doped polysilicon film 205 are separated by the silicon nitride 209. Insulation is automatically separated. Therefore, phosphorus-doped polysilicon film
There is almost no alignment margin between one of the N-type diffusion regions 212 and 207 and the phosphorus-doped polysilicon film 214.

In a highly-integrated semiconductor device, a margin for aligning each part of the semiconductor device has a great influence on its integration density. When the method for manufacturing a semiconductor memory cell of the present invention is used, this alignment margin is not needed, and therefore it is easy to increase the integration density of capacitors.

〔The invention's effect〕

As described above, according to the present invention, a sufficiently large cell capacitor can be provided in a small area, cell capacitors of adjacent memory cells can be easily insulated, and processing in a groove can be eliminated. It is possible to obtain a semiconductor memory cell and a method of manufacturing the same, which are capable of improving the reproducibility of the above-mentioned method and the reliability of the groove capacitor itself and reducing the alignment margin.

[Brief description of drawings]

FIG. 1 is a plan view and a sectional view showing the structure of one embodiment of a semiconductor memory cell of the present invention, and FIG. 2 is a process drawing showing one embodiment of a method of manufacturing a semiconductor memory cell of the present invention. 101 ... P-type silicon crystal substrate 103 ... Groove 104 ... Silicon oxide film 105, 107, 107 ', 111, 111', 114, 114 ', 116 ... Conductor film 106, 110 , 110 , 110' , 113,115 …… Insulator film 109 …… Side insulator 112 …… N type silicon region 201 …… P type silicon crystal substrate 202 …… Insulator film 203 …… Groove 204 …… Silicon oxide film 205 …… Phosphorus-doped Polysilicon film 206 …… Composite film 207 …… Phosphorus-doped polysilicon film 208 …… Non-doped polysilicon 209 …… Silicon nitride 210 …… Silicon oxide film 211 …… Silicide film 212 …… N-type diffusion region 213 …… Silicon oxide Membrane 214 ... Phosphorus-doped polysilicon film

Claims (2)

[Claims] 1. A plurality of grooves formed on a surface of a substrate, a first insulating film formed inside these grooves, and a plurality of grooves connected to the first insulating film on the first insulating film. A first conductor film formed on the first conductor film, a second insulator film formed on the first conductor film, and a second conductor film formed on the second insulator film, A third insulator formed on a side surface of the first conductor film, and a fourth insulator film formed on the second conductor film and made of a material different from that of the third insulator, A semiconductor memory cell, comprising: a switching transistor; and a third conductor film that connects one current-carrying electrode of the switching transistor and the second conductor film. 2. A step of forming a plurality of grooves on a surface of a substrate, a step of forming a first insulating film inside the grooves, and a step of connecting the plurality of grooves on the first insulating film. And sequentially forming a first conductor film, a second insulator film, and a second conductor film, and a step of forming a third insulator on the side surface of the first conductor film. Forming a fourth insulator film made of a material different from that of the third insulator on the second conductor film, removing a part of the fourth insulator film, and removing the second insulator film from the second insulator film. Exposing the conductor film, forming a third conductor film so as to contact the exposed portion of the second conductor film, and cutting the second conductor film. A method of manufacturing a semiconductor memory cell, comprising: