KR100316020B1 - Method for forming capacitor of semiconductor device - Google Patents
Method for forming capacitor of semiconductor device Download PDFInfo
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- KR100316020B1 KR100316020B1 KR1019980024724A KR19980024724A KR100316020B1 KR 100316020 B1 KR100316020 B1 KR 100316020B1 KR 1019980024724 A KR1019980024724 A KR 1019980024724A KR 19980024724 A KR19980024724 A KR 19980024724A KR 100316020 B1 KR100316020 B1 KR 100316020B1
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- Prior art keywords
- film
- forming
- capacitor
- iro
- semiconductor device
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- 239000003990 capacitor Substances 0.000 title claims abstract description 27
- 238000000034 method Methods 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 44
- 229920005591 polysilicon Polymers 0.000 claims abstract description 44
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 2
- 238000004544 sputter deposition Methods 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 abstract description 8
- 230000003405 preventing effect Effects 0.000 abstract description 6
- 230000004888 barrier function Effects 0.000 abstract description 5
- 229910004298 SiO 2 Inorganic materials 0.000 abstract description 4
- 230000009257 reactivity Effects 0.000 abstract description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 적층된 IrO2막으로 확산방지막을 형성하고 Ir막으로 캐패시터의 하부전극을 형성하는 방법에 있어서, 정전용량 감소와 접촉저항 증가를 방지할 수 있는 반도체 소자의 캐패시터 형성 방법에 관한 것으로, 도핑된 폴리실리콘막 및 비도핑 폴리실리콘막의 적층구조로 이루어진 폴리실리콘 플러그를 형성한 후, IrO2막 및 Ir막을 증착하여 캐패시터의 하부전극을 형성함으로써, 비도핑 폴리실리콘막과 IrO2막의 반응성을 감소시켜 폴리실리콘 플러그와 IrO2막 사이에 SiO2막이 생성되는 것을 방지하는데 그 특징이 있다.The present invention relates to a method for forming a capacitor of a semiconductor device capable of preventing a decrease in capacitance and an increase in contact resistance in a method of forming a diffusion barrier film with a stacked IrO 2 film and forming a lower electrode of a capacitor with an Ir film. After forming a polysilicon plug having a laminated structure of a doped polysilicon film and an undoped polysilicon film, the IrO 2 film and Ir film are deposited to form a lower electrode of the capacitor, thereby improving the reactivity of the undoped polysilicon film and the IrO 2 film. It is characterized by a reduction in preventing the formation of a SiO 2 film between the polysilicon plug and the IrO 2 film.
Description
본 발명은 반도체 장치 제조 분야에 관한 것으로, 특히 고온 산소 분위기에서 증착되는 유전막을 갖는 캐패시터 형성 방법에 관한 것이다.TECHNICAL FIELD The present invention relates to the field of semiconductor device manufacturing, and more particularly, to a method of forming a capacitor having a dielectric film deposited in a high temperature oxygen atmosphere.
고집적 DRAM(dynamic random access memory) 소자를 이루는 캐패시터의 정전용량을 증가시키기 위하여 고유전 특성을 갖는 (Ba,Sr)TiO3막을 캐패시터의 유전막으로 사용한다.In order to increase the capacitance of a capacitor constituting a highly integrated dynamic random access memory (DRAM) device, a (Ba, Sr) TiO 3 film having high dielectric properties is used as the dielectric film of the capacitor.
첨부된 도면 도1은 종래 기술에 따른 캐패시터 형성 공정 단면도로서, 반도체 기판(10) 상에 형성된 절연막(11)을 선택적으로 제거하여 반도체 기판(10)을 노출시키는 콘택홀을 형성하고, 콘택홀 내에 도핑된 폴리실리콘막으로 플러그(plug)(12)를 형성한 후, 폴리실리콘 플러그(12)로부터 캐패시터의 하부전극으로 실리콘이 확산되는 것을 방지하기 위하여 Ti막(13) 및 TiN막(14)을 형성하고, TiN막(14) 상에 캐패시터의 하부전극을 이룰 Pt막(15)을 형성한 다음, Pt막(15), TiN막(14) 및 Ti막(13)을 패터닝하여 확산방지 패턴 및 하부전극 패턴을 형성하고, (Ba,Sr)TiO3유전막(16) 및 Pt 상부전극(17)을 형성한 것을 보이고 있다.1 is a cross-sectional view illustrating a capacitor forming process according to the related art, in which a contact hole for exposing the semiconductor substrate 10 is formed by selectively removing the insulating layer 11 formed on the semiconductor substrate 10, and in the contact hole. After the plug 12 is formed of the doped polysilicon film, the Ti film 13 and the TiN film 14 are formed to prevent silicon from diffusing from the polysilicon plug 12 into the lower electrode of the capacitor. A Pt film 15 to form the lower electrode of the capacitor on the TiN film 14, and then pattern the Pt film 15, the TiN film 14, and the Ti film 13 to form a diffusion barrier pattern and The lower electrode pattern is formed, and the (Ba, Sr) TiO 3 dielectric layer 16 and the Pt upper electrode 17 are formed.
(Ba,Sr)TiO3막 증착은 고온의 산소 분위기에서 이루어지므로, 하부전극은 산소확산 방지 특성이 우수하여야 한다. 그러나, 캐패시터의 하부전극으로 선호되고 있는 Pt막은 산소에 대한 확산방지 특성이 없어, Pt막의 결정립계(grain boundary) 또는 주상(columnar) 경계를 통하여 Pt막 하부로 산소가 확산된다. 이에 따라, 폴리실리콘의 확산방지막으로 사용되는 TiN막이 산화되어 TiO2가 생성되는 문제점이 있다.Since the deposition of the (Ba, Sr) TiO 3 film is performed in a high temperature oxygen atmosphere, the lower electrode should have excellent oxygen diffusion preventing properties. However, the Pt film, which is preferred as the lower electrode of the capacitor, has no diffusion preventing property against oxygen, and oxygen diffuses below the Pt film through the grain boundary or columnar boundary of the Pt film. Accordingly, there is a problem in that the TiN film used as the diffusion barrier of polysilicon is oxidized to generate TiO 2 .
이와 같은 문제점을 해결하기 위하여 확산방지 특성이 우수한 IrO2막 및 Ir막으로 하부전극을 형성하는 방법에 제공되었으나, 도핑된 폴리실리콘 플러그와 IrO2막 계면에 SiO2와 같은 저유전율의 막이 형성되어 정전용량을 감소시킬 뿐만 아니라 접촉저항을 증가시키는 단점이 있다.In order to solve the above problems, a method of forming a lower electrode using an IrO 2 film and an Ir film having excellent diffusion preventing properties is provided, but a low dielectric constant film such as SiO 2 is formed at an interface between a doped polysilicon plug and an IrO 2 film. In addition to reducing the capacitance, there is a disadvantage of increasing the contact resistance.
상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 IrO2막으로 확산방지막을 형성하고 Ir막으로 캐패시터의 하부전극을 형성하는 방법에 있어서, 정전용량 감소와 접촉저항 증가를 방지할 수 있는 반도체 소자의 캐패시터 형성 방법을 제공하는데 그 목적이 있다.In order to solve the above problems, the present invention provides a semiconductor device capable of preventing a decrease in capacitance and an increase in contact resistance in a method of forming a diffusion barrier film with an IrO 2 film and forming a lower electrode of a capacitor with an Ir film. It is an object of the present invention to provide a method for forming a capacitor.
도1은 종래 기술에 따른 캐패시터 형성 공정 단면도1 is a cross-sectional view of a capacitor forming process according to the prior art
도2a 내지 도2e는 본 발명의 일실시예에 따른 캐패시터 형성 공정 단면도2A through 2E are cross-sectional views of a capacitor forming process according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 도면 부호의 설명* Explanation of reference numerals for the main parts of the drawings
21: 반도체 기판 22: 절연막21: semiconductor substrate 22: insulating film
23: 도핑된 폴리실리콘막 24: 비도핑 폴리실리콘막23: doped polysilicon film 24: undoped polysilicon film
25: IrO2막 26, 28: Ir막25: IrO 2 film 26, 28: Ir film
27: (Ba,Sr)TiO3막27: (Ba, Sr) TiO 3 Membrane
상기 목적을 달성하기 위한 본 발명은 반도체 기판 상에 절연막을 선택적으로 제거하여 상기 반도체 기판을 노출시키는 콘택홀을 형성하는 제1 단계; 상기 제1 단계가 완료된 전체 구조 상에 도핑 폴리실리콘막을 형성하고, 상기 도핑 폴리실리콘막을 전면식각하여 상기 콘택홀 내에 상기 도핑 폴리실리콘막을 잔류시키는 제2 단계; 상기 제2 단계가 완료된 전체 구조 상에 비도핑 폴리실리콘막을 형성하고, 상기 비도핑 폴리실리콘막을 화학적 기계적으로 연마하여 상기 도핑폴리실리콘막과 상기 비도핑폴리실리콘막의 적층구조로 이루어진 플러그를 형성하는 제 3 단계; 상기 제3 단계가 완료된 전체 구조 상에 IrO2막 및 Ir막을 차례로 형성하고, 상기 Ir막 및 IrO2막을 선택적으로 식각하여 하부전극 패턴을 형성하는 제4 단계; 상기 하부전극 패턴 상에 유전막을 형성하는 제5 단계; 및 상기 유전막 상에 상부전극을 형성하는 제6 단계를 포함하는 반도체 소자의 캐패시터 형성 방법을 제공한다.The present invention for achieving the above object is a first step of forming a contact hole to expose the semiconductor substrate by selectively removing the insulating film on the semiconductor substrate; Forming a doped polysilicon film on the entire structure of the first step, and etching the doped polysilicon film over the entire surface to leave the doped polysilicon film in the contact hole; An undoped polysilicon film is formed on the entire structure of the second step, and the undoped polysilicon film is chemically and mechanically polished to form a plug having a laminated structure of the doped polysilicon film and the undoped polysilicon film. Three steps; A fourth step of sequentially forming an IrO 2 film and an Ir film on the entire structure in which the third step is completed, and selectively etching the Ir film and the IrO 2 film to form a lower electrode pattern; Forming a dielectric layer on the lower electrode pattern; And a sixth step of forming an upper electrode on the dielectric layer.
본 발명은 도핑된 폴리실리콘막 및 비도핑 폴리실리콘막의 적층구조로 이루어진 폴리실리콘 플러그를 형성한 후, IrO2막 및 Ir막을 증착하여 캐패시터의 하부전극을 형성함으로써, 비도핑 폴리실리콘막과 IrO2막의 반응성을 감소시켜 폴리실리콘 플러그와 IrO2막 사이에 SiO2막이 생성되는 것을 방지하는데 그 특징이 있다.The present invention forms a polysilicon plug comprising a laminated structure of a doped polysilicon film and an undoped polysilicon film, and then deposits an IrO 2 film and an Ir film to form a lower electrode of the capacitor, thereby forming an undoped polysilicon film and IrO 2. It is characterized by reducing the reactivity of the film to prevent the formation of SiO 2 film between the polysilicon plug and the IrO 2 film.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.
도2a 내지 도2e는 본 발명의 일실시예에 따른 캐패시터 형성 공정 단면도이다.2A through 2E are cross-sectional views of a capacitor forming process according to an embodiment of the present invention.
먼저, 도2a에 도시한 바와 같이 반도체 기판(21) 상에 형성된 절연막(22)을 선택적으로 제거하여 반도체 기판(21)을 노출시키는 콘택홀을 형성하고, 전체 구조 상에 500 Å 내지 3000 Å 두께의 도핑된 폴리실리콘막(23)을 화학기상증착법으로 형성하고 전면식각하여 콘택홀 내에 도핑된 폴리실리콘막(23)이 남도록 한다.First, as shown in FIG. 2A, the insulating film 22 formed on the semiconductor substrate 21 is selectively removed to form a contact hole for exposing the semiconductor substrate 21, and the thickness of 500 3000 to 3000 Å on the entire structure. The doped polysilicon film 23 is formed by chemical vapor deposition, and the surface is etched so that the doped polysilicon film 23 remains in the contact hole.
다음으로, 도2b에 도시한 바와 같이 전체 구조 상에 도핑된 폴리실리콘막 보다 반응성이 낮은 비도핑 폴리실리콘막(24)을 1000 Å 내지 2000 Å 두께로 형성하고, 비도핑 폴리실리콘막(24)을 화학적 기계적 연마(chemical mechanical polishing) 하여, 도핑된 폴리실리콘막(23)이 전면식각되면서 생성된 리세스(recess) 내에 비도핑 폴리실리콘막(24)이 남도록하여 도핑된 폴리실리콘막(23) 및 비도핑 폴리실리콘막(24)으로 이루어지는 폴리실리콘 플러그를 형성한다. 이후의 유전막 형성이 고온에서 진행되므로, 상기 비도핑 폴리실리콘막(24) 내로 불순물을 확산시키기 위한 별도의 열처리 공정은 실시하지 않는다.Next, as shown in FIG. 2B, an undoped polysilicon film 24 having a reactivity less than that of the doped polysilicon film is formed to have a thickness of 1000 GPa to 2000 GPa, and the undoped polysilicon film 24 is formed. Chemical mechanical polishing, and the doped polysilicon film 23 remains in the recesses formed while the doped polysilicon film 23 is etched entirely. And a polysilicon plug made of the undoped polysilicon film 24. Since the subsequent dielectric film formation is performed at a high temperature, a separate heat treatment process for diffusing impurities into the undoped polysilicon film 24 is not performed.
다음으로, 도2c에 도시한 바와 같이 자연산화막(도시하지 않음) 제거를 위해 HF 용액 등을 이용하여 세정공정을 실시하고, 전체 구조 상에 300 Å 내지 1000 Å 두께의 IrO2막(25)을 반응성 스퍼터링(sputtering) 방법으로 증착한 후, IrO2막(25) 상에 Ir막(26)을 1000 Å 내지 3000 Å 두께로 형성한다.Next, as illustrated in FIG. 2C, a cleaning process is performed using a HF solution or the like to remove a natural oxide film (not shown), and an IrO 2 film 25 having a thickness of 300 GPa to 1000 GPa is formed on the entire structure. After deposition by reactive sputtering, an Ir film 26 is formed on the IrO 2 film 25 to a thickness of 1000 kPa to 3000 kPa.
다음으로, 도2d에 도시한 바와 같이 Ir막(26) 및 IrO2막(26)을 패터닝하여 하부전극 패턴을 형성한다.Next, as shown in FIG. 2D, the Ir film 26 and the IrO 2 film 26 are patterned to form a lower electrode pattern.
다음으로 도2e에 도시한 바와 같이 하부전극 패턴 형성이 완료된 전체 구조 상에 300 Å 내지 2000 Å 두께의 (Ba,Sr)TiO3막(27)을 증착하고, (Ba,Sr)TiO3막(27) 상에 상부전극을 이룰 500 Å 내지 2000 Å 두께의 Ir막(28)을 형성한다.Next, as shown in FIG. 2E, a (Ba, Sr) TiO 3 film 27 having a thickness of 300 mV to 2000 mV is deposited on the entire structure where the bottom electrode pattern is formed, and a (Ba, Sr) TiO 3 film ( 27, an Ir film 28 having a thickness of 500 m to 2000 m is formed on the upper electrode.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
상기와 같이 이루어지는 본 발명은 캐패시터의 하부전극과 연결되는 폴리실리콘 플러그를 도핑된 폴리실리콘막 및 비도핑 폴리실리콘막의 적층구조로 형성하고 확산방지막으로 IrO2막을 형성함으로써, 폴리실리콘 플러그와 IrO2막 사이에 저유전막인 SiO2막이 형성되는 것을 억제하여 캐패시터의 정전용량을 증가시킬 뿐만 아니라 접촉 저항의 증가를 방지할 수 있다.According to the present invention, a polysilicon plug and an IrO 2 film are formed by forming a polysilicon plug connected to a lower electrode of a capacitor in a stacked structure of a doped polysilicon film and an undoped polysilicon film and forming an IrO 2 film as a diffusion barrier. It is possible to suppress the formation of the SiO 2 film, which is a low dielectric film, in between, to increase the capacitance of the capacitor and to prevent an increase in the contact resistance.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980024724A KR100316020B1 (en) | 1998-06-29 | 1998-06-29 | Method for forming capacitor of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980024724A KR100316020B1 (en) | 1998-06-29 | 1998-06-29 | Method for forming capacitor of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20000003482A KR20000003482A (en) | 2000-01-15 |
| KR100316020B1 true KR100316020B1 (en) | 2002-02-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980024724A KR100316020B1 (en) | 1998-06-29 | 1998-06-29 | Method for forming capacitor of semiconductor device |
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|---|---|
| KR (1) | KR100316020B1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030028045A (en) * | 2001-09-27 | 2003-04-08 | 삼성전자주식회사 | Ferroelectric memory device and method of forming the same |
| KR100663356B1 (en) * | 2005-02-14 | 2007-01-02 | 삼성전자주식회사 | Methods of fabricating feroelectric memory device having partially chemical mechanical polishing process |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6418253A (en) * | 1987-07-13 | 1989-01-23 | Nec Corp | Semiconductor memory cell and its manufacture |
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Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6418253A (en) * | 1987-07-13 | 1989-01-23 | Nec Corp | Semiconductor memory cell and its manufacture |
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| KR20000003482A (en) | 2000-01-15 |
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