JP2621820B2 - Static memory cell - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a thin film transistor (TFT).
(Transistor) as a load transistor.

[0002]

2. Description of the Related Art In an SRAM (static type memory), it is desired that the standby current of a device be suppressed to 1 μA or less while increasing the integration density in recent years. For this purpose, it is necessary to reduce the leakage current per cell together with the degree of integration. Therefore, instead of high resistance polysilicon, which has been often used as a load element, T
A memory cell using FT is used.

[0003] This is because, by using an active element as a load element, it is possible to secure a large on-current while reducing leakage current due to a high off-resistance.

FIG. 5 shows an equivalent circuit diagram of a static memory cell using a TFT. In a static memory cell using a TFT as a load transistor, an N-channel type driving transistor Q1 formed on a substrate by using a general semiconductor manufacturing process technique and a P-channel type having a polysilicon layer as an active layer above the driving transistor Q1. A CMOS inverter is constituted by the load thin film transistor Q2 of the type, and a flip-flop circuit is formed by another CMOS inverter constituted by the drive transistor Q3 and the load thin film transistor Q4 which are similarly formed. Stored information is accumulated.
Nodes N1 and N2 are connected to bit lines BL and BL via transfer transistors (transfer transistors for information) Q5 and Q6 selected by word line WL for writing and reading stored information to and from this flip-flop circuit. BL ′.

Then, an N-channel type MOSFE on the substrate
In the connection between the T and the P-channel type TFT, the P-type region portion of polysilicon forming the drain region of the TFT is
The N-type region of polysilicon forming the gate electrode of the SFET or the P-type region of polysilicon forming the drain region of one of the two load thin film transistors and the gate electrode of the other TFT are formed. To the N-type region portion of the polysilicon. As a result, mutual diffusion of impurities occurs at this connection portion, and P
Parasitic diodes D1 and D2 formed by N-junction are arranged.

Hereinafter, a conventional structure of such a memory cell will be described with reference to FIGS. 6 and 7. FIG. FIG. 6 is a plan view of the aforementioned conventional memory cell. Here, FIG.
FIG. 6A is a plan view after a step of forming a driving transistor and a transistor (hereinafter referred to as a base step), and FIG. 6B is a plan view after forming a load thin film transistor and a bit line by a TFT. Also,
FIG. 7 is a cross-sectional view for explaining the vertical structure of the memory cell. Here, this cross-sectional view shows a section cut along A′-B ′ shown in FIG.

As shown in FIG. 6A, silicon active regions 102 and 102a surrounded by an element isolation insulating film 101 are formed on the surface of a silicon substrate having a p-type conductivity. Then, the gate electrodes 103 and 103 of the driving transistor
a is provided to connect to the silicon active regions 102a and 102 via direct contacts 104 and 104a, respectively. Further, word lines 105 and 105a serving as gates of transfer transistors are formed.

The source and drain regions of the driving transistor and the transfer transistor are
An impurity such as arsenic is ion-implanted into a region where the gate electrode is not formed in the silicon active region described above. After this, an interlayer insulating film covering the whole is formed, and this interlayer insulating film is
6, 106a are formed. Then, the source region of the driving transistor and the ground wiring 1 are connected through the contact hole.
07 is electrically connected.

As shown in FIG. 6B, first node contacts 108 and 108a are formed in the interlayer insulating film, and the above-mentioned gate electrode 103 and TFT gate electrode 109a, and the above-mentioned gate electrode 103a and TFT gate electrode are formed. 109 are electrically connected to each other. Here, the gate electrode of the driving transistor and the gate electrode for TFT are N ⁺ regions containing phosphorus or arsenic impurities. Furthermore, TF
The node portion second contacts 110 and 110a are formed on the TFT gate insulating film layer covering the T gate electrodes 109 and 109a.
Is formed, and the above-described TFT gate electrode 109 and the TFT
Drain region 111a, TFT gate electrode 109a
And the TFT drain region 111 are electrically connected to each other. Here, the TFT drain region is a P ⁺ region containing boron impurities.

As described above, the TFT source region 1
12, 112a, TFT channel regions 113, 113
a, TFT drain regions 111, 111a and TF
The above-described two load thin-film transistors composed of the T gate electrodes 109 and 109a are formed. Then, bit line contacts 115 and 115a are provided, and bit lines 116 and 116a are formed.

Next, a vertical structure of the conventional memory cell will be described with reference to FIG. As shown in FIG. 7, an element isolation insulating film 202 and an n ⁺ diffusion layer 203 are formed on a surface of a silicon substrate 201 having a p-type conductivity. Then, the gate insulating film 204 for the drive transistor and the gate electrode 20
5 are formed. Here, the gate insulating film 204 for the drive transistor is formed of a silicon oxide film having a thickness of 10 to 20 nm, and the gate electrode 205 is formed of tungsten polycide containing a phosphorus impurity having a thickness of about 200 nm.

After the above, a silicon oxide film is deposited by a CVD (chemical vapor deposition) method, and the surface is planarized by an etch-back method or a CMP (chemical mechanical polishing) method to form a first interlayer insulating film. 206 is formed. Then, a grounding contact (not shown) is formed, and a tungsten silicide patterned grounding wiring 207 having a thickness of 200 nm to 300 nm covering these is formed.
Is formed.

After the formation of the ground wiring 207, the CV
A second interlayer insulating film 208 is deposited by the D method. Here, the thickness of the second interlayer insulating film 208 is about 200 nm. Then, a node portion first contact 209 is provided on the first interlayer insulating film 206 and the second interlayer insulating film 208. Next, TFT gate electrodes 210 and 210a are formed. The thickness of the TFT gate electrode is 50 n
m is sufficient, and the volume concentration is 5 × 10 ¹⁹ atoms / cm.
^{About 3} phosphorus impurities are doped. Where TF
The T gate electrode 210a is a part of the other TFT gate electrode, and the TFT gate electrode 10a shown in FIG.
9a.

Thereafter, a TFT gate insulating film 211 is formed by depositing a silicon oxide film by the CVD method. Here, the thickness of the silicon oxide film is 20 to 30 nm. Then, the node portion second contact 212 is provided on the TFT gate insulating film 211.

After the above, an N-type polysilicon film for the TFT is formed, and the drain region 213 for the TFT, the offset region 214 for the TFT,
TFT source region 215, TFT channel region 21
6 are formed. Here, the TFT drain region 213
And the TFT for the source region 215 concentration is introduced 1 × 10 ²⁰ atoms / cm ³ order holon impurities. Then, a P ⁺ N ⁺ junction surface 217 is formed between the TFT drain region 213 and the above-described TFT gate electrode 210a.

Next, a third interlayer insulating film 218 is formed by a thick silicon oxide film, a bit line 219 is formed by aluminum metal, and a fourth interlayer insulating film 220 is further formed thereon.

[0017]

As described above, the TF used for the load element of the memory cell of the SRAM is used.
A polysilicon film containing a phosphorus impurity is usually used for the T gate electrode. This is because such a polysilicon film is effective for electrically stabilizing the TFT gate insulating film. Alternatively, even if a polysilicon film containing a boron impurity is used for the gate electrode of the TFT, a phosphorus impurity is introduced into the gate electrode of the drive transistor connected to the gate electrode for the TFT.
As described above, in a static memory cell using a TFT as a load thin film transistor, formation of a parasitic PN junction at an information storage node cannot be avoided as shown in FIG.

In the above-described conventional memory cell structure, the parasitic P ⁺ N ⁺ junction surface is formed by TF as described with reference to FIG.
T gate electrode 210a and TFT drain region 213
, That is, in the vicinity of the node portion second contact 212. Here, the crystal grains of the polysilicon film are usually formed in a columnar shape. For this reason, in the conventional memory cell structure, when the above-described crystal grain boundary crosses the P ⁺ N ⁺ junction, the electrical characteristics of the junction change greatly. This is because the diffusion of boron or phosphorus impurities progresses along the crystal grain boundaries and abnormal junctions are formed.

Further, the structure of the conventional memory cell is easily affected by the peripheral wiring because of such a PN junction. That is, when the potential of the bit line 219 changes as shown in FIG.
3 easily changes due to the capacitive coupling. this is,
This is because the TFT drain region is electrically separated from the TFT gate electrode by the PN junction and is in a floating state.
Here, the fluctuation in the potential of the bit line is caused by operations such as reading and writing of other memory cells.

As described above, in the SRAM composed of the conventional memory cells, the electrical characteristics of the parasitic P ⁺ N ⁺ junction tend to be unstable, so that the operating margin such as the operating voltage or the operating speed is increased. Need to be done. In addition, lowering the operating voltage or increasing the speed of operation has been restricted.

An object of the present invention is to reduce the variation in the electrical characteristics of a parasitic diode formed in a static memory cell having a TFT as a load thin film transistor or to suppress instability, thereby reducing the operating margin of an SRAM. The purpose is to improve operating characteristics.

[0022]

For this purpose, in the static memory cell of the present invention, a pair of information transfer MOSFETs formed on the surface of a semiconductor substrate and a pair of drive MOSFETs forming a flip-flop circuit are provided. And a pair of load thin film transistors, wherein a gate electrode of the pair of load thin film transistors is formed of a first-layer silicon thin film containing an N-type high-concentration impurity. The source region of the source / drain of the load thin film transistor is formed in a region containing a P-type high-concentration impurity of the second layer silicon thin film separated by the first layer silicon thin film and the interlayer insulating film, One drain region is a second-layer silicon layer having a PN junction diode composed of an N-type high concentration impurity and a P-type high concentration impurity. A gate electrode of one load thin film transistor of the pair of load thin film transistors and a drain region containing the N-type high-concentration impurity of the other load thin film transistor are formed in the interlayer insulating film. The PN junction diode is electrically connected through a contact hole, and the junction region of the PN junction diode is covered with a thin conductive material film via a thin insulating film, and the thin conductive material film is fixed at a constant potential.

Here, the source of the information transfer MOSFET is formed on a diffusion layer formed on the surface of the semiconductor substrate and fixed to the ground potential, and the conductive material thin film is electrically connected to the diffusion layer. You.

[0024]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a plan view of a memory cell for explaining a first embodiment of the present invention, and FIGS. 2 and 3 are sectional views thereof. here,
FIG. 1A is a plan view after a base step described in the related art, and FIG. 1B is a plan view after forming a load thin film transistor and a bit line by a TFT.

As shown in FIG. 1A, the underlying step is the same as that of the above-described conventional technique. That is, first, silicon active regions 2 and 2a surrounded by the element isolation insulating film 1 on the surface of the silicon substrate are formed. Then, gate electrodes 3 and 3a of the driving transistor are provided so as to be connected to silicon active regions 2a and 2 via direct contacts 4 and 4a, respectively. Further, word lines 5, 5a serving as gates of transfer transistors are formed. The source / drain regions of the drive transistor and the transfer transistor described above are:
An impurity such as arsenic is ion-implanted into a region where the gate electrode is not formed in the silicon active region described above. After this, an interlayer insulating film is formed so as to cover the whole.

Next, as shown in FIG. 1B, first node contacts 6 and 6a are formed on the interlayer insulating film, and the gate electrode 3 and the TFT gate electrode 7a, and the gate electrode 3a and the TFT Gate electrodes 7 are electrically connected to each other. Further, the node portion second contacts 8 and 8a are formed on a layer of the TFT gate insulating film that covers the TFT gate electrodes 7 and 7a, and the above-described TFT gate electrode 7a and the TFT drain region 9 and the TFT gate electrode 7 are formed. And TF
The drain regions 9a for T are electrically connected to each other.
Then, TFT source regions 10 and 10a and TFT channel regions 11 and 11a are formed. In this manner, the two load thin film transistors described above, each including the TFT gate electrodes 7 and 7a, are formed.

Next, an interlayer insulating film is deposited again, ground contacts 12 and 12a are formed on the insulating film, and a ground wiring 13 is formed. Here, the ground wiring 13 is connected to the silicon active regions 2 and 2a through the ground contacts 12 and 12a and is fixed at the GND (ground) potential. As described above, in the present invention, the ground wiring is formed in the upper layer of the load thin film transistor.

The bit line contacts 14, 14
a is provided, and bit lines 15 and 15a are formed.

Next, the vertical structure of the memory cell of the present invention will be described with reference to FIGS. FIG. 2 is a cross-sectional view taken along the line AB shown in FIG. As shown in FIG. 2, a silicon substrate 2 having a p-type conductivity or a p-well is formed.
An element isolation insulating film 22 is formed on the surface of the substrate 1. And
An n ⁺ diffusion layer 23 is provided, and a gate insulating film 24 and a gate electrode 25 for a driving transistor are formed. here,
The gate insulating film 24 for the driving transistor has a thickness of 10 to 10.
The gate electrode 25 is formed of a 20 nm silicon oxide film.
Is formed of tungsten polycide having a thickness of about 200 nm. The gate electrode 25 contains phosphorus impurities at a concentration of about 5 × 10 ¹⁹ atoms / cm ³ .

After the above, a silicon oxide film is deposited by the CVD method, and the surface is flattened by the etch back method or the CMP method to form the first interlayer insulating film 26. Here, the thickness of the first interlayer insulating film 26 is 200
It is set to about nm. Then, the first interlayer insulating film 2
6, a first contact 27 of the node portion is formed, and gate electrodes 28 and 28a for TFT are formed. The TFT gate electrode is a polysilicon film having a thickness of about 50 nm, and is doped with a phosphorus impurity at a volume concentration of about 10 ²⁰ atoms / cm ³ .

Thereafter, a TFT gate insulating film 29 is formed by depositing a silicon oxide film by the CVD method. Here, the thickness of the silicon oxide film is 20 to 30 nm. Then, a node second contact 30 is formed in a predetermined region of the TFT gate insulating film 29.

After the above, an N-type polysilicon film is formed. For forming the polysilicon film, a so-called solid phase growth method of amorphous silicon is used.

In CVD, Si ₂ H _{4 is used} as a reaction gas.
An amorphous silicon film is deposited to a thickness of 50 nm at a film forming temperature of 450 to 500 ° C. by using, and then annealed at a temperature of 600 ° C. to crystallize the amorphous silicon film. A polysilicon film having a crystal grain size of about 3 μm obtained by this method is entirely doped with phosphorus impurities and patterned. Here, the concentration of this phosphorus impurity is 1
It is set to about × 10 ¹⁷ atoms / cm ³ .

Next, a TFT drain region 31, a TFT offset region 32, a TFT source region 33, and a TFT channel region 34 are formed in the patterned N-type polysilicon film. The TFT drain region 31 and the TFT source region 33 are doped with a boron impurity at a concentration of 5 × 10 ¹⁹ atoms / cm ³ .

Next, a silicon oxide film having a thickness of about 30 nm is deposited by a CVD method and subjected to a heat treatment. After this, the ground wiring 36 is formed of tungsten silicide containing a phosphorus impurity with a thickness of about 300 nm. Here, the pattern of the grounding wiring 36 is shown in FIG.
As shown in FIG. 7, the node portion first contacts 6, 6a, the node portion second contacts 8, 8a, the bit line contacts 14, 14a, a part of the TFT drain regions 9, 9a and one of the TFT gate electrodes 7, 7a. The portion is formed so as to be exposed.

After this, arsenic or phosphorus ions are implanted using the patterned ground wiring 36 as a mask. Here, the implantation energy of this ion implantation is 150 keV, and the dose is 5 × 10 ¹⁵ ions /
cm ² . Next, heat treatment is performed at 850 ° C. for about 20 minutes. Thus, the N ⁺ drain region 37 is formed. This N ⁺ drain region 37 has 1 × 10 ²⁰
An N-type impurity concentration of atoms / cm ³ is included.

As described above, the P ⁺ N ⁺ junction surface 38 as shown in FIG. 2 is formed. In this case, the P ⁺ N ⁺ junction surface 38 thus formed is parallel to the thickness direction of the drain region for the TFT, and is covered with the ground wiring 36 via the second interlayer insulating film 35. Furthermore, this P ⁺ N ⁺
The bonding surface 38 is connected to the TFT via the gate insulating film 29 for the TFT.
The gate electrode 28a is also covered.

Next, a third interlayer insulating film 39 is formed by a BPSG film (a silicon oxide film containing boron glass and phosphorus glass).
Is formed thereon, a bit line 40 is formed of aluminum metal, and a fourth interlayer insulating film 41 is further formed.

Next, the effect of the present invention will be described with reference to FIG. FIG. 3 is an enlarged view of the formation region of the P ⁺ N ⁺ junction surface described above. Here, FIG. 3A shows the case of the present invention, and FIG. 3B shows the case of the conventional technique.

As shown in FIG. 3A, the features of the present invention are as follows.
The P ⁺ N ⁺ junction surface is in the direction of the crystal grain boundary of the polysilicon film, and this junction surface is covered with the ground wiring 36 via the thin second interlayer insulating film 35 having a thickness of about 30 nm. At the P ⁺ N ⁺ junction, the impurity concentration of the N ⁺ region, that is, the N ⁺ drain region 37 is higher than that of the P ⁺ region, that is, the TFT drain region 31.

On the other hand, as described above, in the prior art, as shown in FIG. 3B, the P ⁺ N ⁺ junction surface is formed in a direction perpendicular to the aforementioned crystal grain boundaries. Further, the bonding surface is not covered with the wiring having a constant potential as in the present invention.

Due to the characteristics of the joint surface of the present invention, the following effects can be obtained. That is, even if a crystal grain boundary is formed in the region of the P ⁺ N ⁺ junction surface, the deterioration of the electrical characteristics of this junction surface is small. This is because the crystal grain boundary moves from the N ⁺ drain region 37 to TF
This is because it does not extend to the T drain region 31 for a long time. Further, the P ⁺ N ⁺ junction has improved resistance to external electric disturbance. This is because this electrical disturbance is shielded by the ground wiring 36 fixed to the GND potential. Note that, in the case of FIG.
In this structure, the gate electrode 28a is covered from below through a TFT gate insulating film 29. For this reason, the above-mentioned effect becomes larger. Furthermore, this P ⁺
At the N ⁺ junction, the electrical properties at the interface between the second interlayer insulating film 35 and the P ⁺ N ⁺ junction are stabilized, and depletion of impurities near the junction is suppressed. . Then, the deterioration of the electrical characteristics of the P ⁺ N ⁺ junction, which usually occurs near the interface between the junction surface and the insulating film, is suppressed. This is because a gate control diode structure using the ground wiring 36 as a gate and the second interlayer insulating film 35 having a thickness of about 30 nm as a gate film is formed. Here, 0 V or a positive voltage is applied to the N ⁺ drain region 37 and the TFT drain region 31, and the ground wiring 36 is applied.
Is applied with 0V. Then, no depletion layer is formed in the interface region between the TFT drain region 31 and the second interlayer insulating film 35, and the diode characteristics of the P ⁺ N ⁺ junction are improved.

As described above, the diode characteristics of the P + N + junction according to the present invention are improved, and the variation among the memory cells is reduced and further stabilized. Then, the operation margin of the memory cell having such a junction is reduced. As a result, the operating voltage of the SRAM becomes
For example, in the case of 4 megabit SRAM and 2.5
The voltage of the V operation is reduced to 1.8 V operation. Further, the guaranteed operation speed is improved.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 4 shows the memory cell of FIG.
It is sectional drawing cut | disconnected by B. The difference between this embodiment and the first embodiment described with reference to FIG. 2 is the manufacturing method. Therefore, in the following description, the difference will be mainly described.

The gate electrode 25 for the driving transistor is formed on the surface of the silicon substrate 21 in the same manner as described with reference to FIG.
Is formed. Here, the gate electrode 25 has a thickness of 200 n.
m of tungsten polycide. This gate electrode 25 has a concentration of 1 × 10
^It is contained in about ²⁰ atoms / cm ³ .

After this, the TFT gate electrodes 28 and 28a are formed through the same steps as described with reference to FIG. The thickness of the TFT gate electrode is 80 n.
m polysilicon film with a volume concentration of 2 × 10 ²⁰
A phosphorus impurity of about atoms / cm ³ is doped.

Thereafter, a TFT gate insulating film 29 is formed by depositing a silicon oxide film by the CVD method. Here, the thickness of the silicon oxide film is 30 to 40 nm.

After the above, an N-type polysilicon film having a thickness of about 30 nm is formed. For forming the polysilicon film, a so-called solid phase growth method of amorphous silicon is used.

Next, the N-type polysilicon film is patterned to form a TFT drain region 31, a TFT offset region 32, a TFT source region 33, and a TFT channel region. The drain region 31 for TFT and the source region 33 for TFT are doped with a boron impurity at a concentration of 8 × 10 ¹⁹ atoms / cm ³ .

Next, a silicon oxide film having a thickness of about 40 nm is deposited by the CVD method, and a second interlayer insulating film 35 is formed. Then, a heat treatment is applied. Here, this heat treatment is performed at a treatment temperature of 900 ° C. in a nitrogen gas atmosphere for about 30 minutes. By this heat treatment, phosphorus impurities are thermally diffused from the TFT gate electrode 28a containing a high concentration impurity to the TFT drain region 31, and the N ⁺ drain region 37
It is formed in the FT drain region 31. And FIG.
A P ⁺ N ⁺ junction surface 38 is formed at a position as shown in FIG.

After the above, the grounding wiring 36 is made of tungsten containing phosphorus impurity having a thickness of about 300 nm.
It is formed of silicide. Here, the ground wiring 36
As shown in FIG. 4, the pattern of P ⁺ N ⁺
Is formed so as to cover only the region with the second interlayer insulating film 35 interposed therebetween. Thereafter, bit lines are formed and memory cells are formed in the same manner as in the first embodiment.

In the case of the present embodiment, the ion implantation step for forming the N ⁺ drain region 37 as in the first embodiment is eliminated, and the manufacturing process is shortened.

In the above embodiment, the case where the P ⁺ N ⁺ junction is formed in the region of the load thin film transistor of the static memory cell has been described. However, it should be noted that the same effect is obtained even when a structure similar to the present invention is applied to a diode mounted on another semiconductor device.

[0054]

As described above, in the diode parasitically formed in the load thin film transistor portion of the static memory cell of the present invention, the P ⁺ N ⁺ junction surface is formed in the direction of the crystal grain boundary of the polysilicon film. This joint surface is covered with a ground wiring via a thin interlayer insulating film. And this P
^{At the +} N ⁺ junction, the impurity concentration of the N ⁺ region, that is, the N ⁺ drain region is higher than that of the P ⁺ region, that is, the drain region for the TFT.

In such a structure of the memory cell of the present invention, the parasitic diode characteristics are improved and the variation in the diode characteristics between the memory cells is reduced.
Then, the operation performance of the SRAM in which such a memory cell is mounted is improved.

Further, in the structure of the memory cell of the present invention, the resistance to electrical disturbance from the peripheral wiring at the PN junction is improved. In other words, when the potential of the bit line arranged in the memory cell fluctuates, the TFT drain region is likely to fluctuate due to the capacitive coupling.
It becomes strong against such a change.

As described above, the present invention reduces the variation in the electrical characteristics of the parasitic diode formed in the static memory cell in which the TFT is the load thin film transistor, or suppresses the instability, thereby reducing the operation margin required for the SRAM. Enable reduction. This facilitates miniaturization or high integration of the SRAM.

[Brief description of the drawings]

FIG. 1 is a plan view of a memory cell for describing the present invention.

FIG. 2 is a cross-sectional view of a memory cell for explaining a first embodiment of the present invention.

FIG. 3 is a sectional view of a PN junction for explaining the first embodiment of the present invention.

FIG. 4 is a cross-sectional view of a memory cell for explaining the first embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram of a memory cell.

FIG. 6 is a plan view of a conventional memory cell.

FIG. 7 is a cross-sectional view of a conventional memory cell.

[Explanation of symbols]

1,2,101,202 Element isolation insulating film 21,201 Silicon substrate 2,2a, 102,102a Silicon active region 3,3a, 25,103,103a, 205 Gate electrode 4,4a, 104,104a Direct contact 5, 5a, 105, 105a Word line 6, 6a, 27, 108, 108a, 209 Node portion first contact 7, 7a, 28, 28a TFT gate electrode 109, 109a, 210, 210a TFT gate electrode 8, 8a, 30 , 110, 110a, 212 Node section second contact 9, 9a, 31, 111, 111a, 213 TFT
Drain region 10, 10a, 33, 112, 112a, 215 T
FT source region 11, 11a, 34 TFT channel region 113, 113a, 210 TFT channel region 12, 12a, 106, 106a Ground contact 13, 36, 107, 207 Ground wiring 14, 14a, 115, 115a bit Line contact 16, 16a, 40, 116, 116a, 219 Bit line 23, 203 n ⁺ diffusion layer 24, 204 Gate insulating film 26, 206 First interlayer insulating film 35, 208 Second interlayer insulating film 29, 211 For TFT Gate insulating films 32, 214 TFT offset region 37 N ⁺ drain region 38, 217 P ⁺ N ⁺ junction surface 39, 218 Third interlayer insulating film 41, 220 Fourth interlayer insulating film Q1, Q3 Driving transistor Q2, Q4 Load thin film transistor Q5, Q6 transfer transistor N1, 2 node WL word lines BL, BL 'bit lines D1, D2 parasitic diode Vcc power supply voltage Vss a ground voltage

Claims (2)

(57) [Claims] 1. A static memory cell formed by a pair of information transfer MOSFETs formed on the surface of a semiconductor substrate, a pair of drive MOSFETs forming a flip-flop circuit, and a pair of load thin film transistors. Wherein the gate electrode of the pair of load thin film transistors is formed of a first layer silicon thin film containing an N-type high concentration impurity, and the source region of the source / drain of the pair of load thin film transistors is the first region. Formed in a region containing a P-type high-concentration impurity of a second-layer silicon thin film separated by a layer of a silicon thin film and an interlayer insulating film,
One drain region is formed in a region of the second layer of silicon thin film having a PN junction diode composed of an N-type high-concentration impurity and a P-type high-concentration impurity. The gate electrode of the thin film transistor and the drain region containing the N-type high-concentration impurity of the other load thin film transistor are electrically connected via a contact hole provided in the interlayer insulating film, and the PN
A static memory cell, wherein a junction region of a junction diode is covered with a thin conductive material via a thin insulating film, and the thin conductive material is fixed at a constant potential. 2. A source of the information transfer MOSFET is formed on a diffusion layer formed on a surface of the semiconductor substrate and fixed to a ground potential, and the conductive material thin film is electrically connected to the diffusion layer. 2. The static memory cell according to claim 1, wherein: