JPS61292343A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a preferable internal wiring of step coverage by selectively forming a conductive layer made of single or polycrystalline silicon in a hole to prevent a spike and to improve an aspect ratio. CONSTITUTION:A gate electrode 24 of a polycrystalline silicon is formed through a gate oxide film 23 on a substrate 21. Then, with the electrode 24 as a mask an N-type impurity is implanted to the substrate 21 to form shallow N<+> type source and drain regions 25, 26. Then, a silicone oxide film 27 on the regions 25, 26 is selectively removed to form holes (contacting holes) 281, 282, and with dichlorosilane and hydrochloric acid as main reaction gases conductive layers 291, 292 made of single crystal silicon are thickly formed selectively in the holes 281, 282 at approx. 950 deg.C. Thus, an aspect ratio can be improved, and to interpose the layers 281, 282 between the internal wiring 30 and the shallow regions 25 and 26, a spike is prevented to prevent a malfunction due to a shortcircuit between the wirings 30 and the substrate 21.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular, improves internal wiring connected to a diffusion layer formed on the surface of a semiconductor substrate.

[Technical background of the invention and its problems]

Conventionally, as a semiconductor device, one shown in FIG. 2, for example, is known. 1 in the figure is, for example, a P-type silicon substrate. On the surface of this substrate 1, an N4 type diffusion layer 21.
22 are provided. An insulating film 3 is provided on the substrate 1, and openings 41 and 42 are provided in the insulating film 3 corresponding to the diffusion layers 2s and 2'2. These openings 41 and 42 have wirings 5t and 52 made of Affi.
are provided for each.

However, according to the semiconductor device shown in FIG. 2, the diameters of the openings 41 and 43 become smaller as the device becomes finer, and for example, in the portion of the opening 41 (dotted line portion) A problem arises in that a step break occurs. Also, spikes occur because the arrangement 5x, 52 is in direct contact with the diffusion layer 21.22.

However, in forming fine contacts, it is necessary to improve the aspect ratio, prevent spikes, etc., and selective tungsten (W) CVD technology is known as one solution (Reference: IEDM, p550.1983. Moriya et al. )
. That is, a semiconductor device using the above-mentioned W+7) CVD technique is as shown in FIG. 3, for example. In the figure, 111
．． 112 is a W layer deposited in the openings 41 and 42, respectively. However, according to the semiconductor device shown in FIG.
The selectivity of tllll, 112 deteriorates as the film thickness increases, and the above-mentioned problems cannot be sufficiently solved.

(Object of the Invention) The present invention has been made in view of the above circumstances, and solves the problems of aspect ratio and spikes by selectively providing a conductive layer made of single crystal silicon or polycrystalline silicon in the opening. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, in which internal wiring with good step coverage can be obtained.

[Summary of the invention]

A first invention of the present application includes a semiconductor substrate, a diffusion layer provided on a surface of the semiconductor substrate, an insulating film provided on the semiconductor substrate and having an opening in a portion corresponding to the diffusion layer, and a A conductive layer made of single crystal silicon or polycrystalline silicon provided on the exposed semiconductor substrate, and the conductive layer provided in the opening. It is characterized by having internal wiring that connects to the layer, and aims to avoid spikes, improve the aspect ratio, and improve the step coverage of the internal wiring.

A second invention of the present application includes a step of forming a diffusion layer on a surface of a semiconductor substrate, a step of forming an insulating film on the semiconductor substrate,
selectively removing the insulating film on the diffusion layer to form an opening; selectively forming a conductive layer made of single crystal silicon or polycrystalline silicon in the opening; The present invention is characterized by comprising a step of forming an internal wiring connected to the conductive layer, and thereby aims to obtain the same effect as the first invention of the present application.

(Embodiments of the Invention) Hereinafter, a case in which the present invention is applied to manufacturing an N-channel MoS transistor will be described with reference to FIGS. 1(a) to 1(C).

First, a field oxide film 22 was formed on the surface of a P-type silicon substrate 210. Next, this field oxide film 2
A gate electrode 24 made of polycrystalline silicon was formed on the substrate 21 surrounded by 2 with a gate oxide film 23 interposed therebetween.

Next, using this gate electrode 24 as a mask, the substrate 2
An n-type impurity was introduced into 1 to form shallow N+ type source and drain regions 25 and 26, respectively. After that, C on the entire surface.
A VD5i021 (hereinafter referred to as silicon oxide film) 27 was formed (as shown in FIG. 1(a)).

Next, the silicon oxide ll! on the source/drain regions 25, 26! 27 was selectively removed to form openings (contact holes) 281 and 282.

Subsequently, the contact hole 28 is heated to approximately 950° C. using dichlorosilane and hydrochloric acid as the main reaction gases. , 282 selectively conductive Ji29x made of single crystal silicon.
, 292 are formed thickly (as shown in FIG. 1(b)). Next, AX-S+ alloy is deposited by sputtering to fill the contact holes 28s and 282 with the conductive material.
N-channel M
An OS transistor was manufactured (as shown in FIG. 1(C)).

Therefore, according to the present invention, before forming the internal wiring 30 made of AR-8i alloy,
Since the layer 2811282 is selectively formed in the contact hole 291.292, the conductive layer 291.292 can be formed thicker, that is, the aspect ratio can be improved compared to the conventional one, and the step coverage of the internal wiring 30 can be improved. Internal wiring 30 and shallow N+ type source/drain regions 25.2
6, the conductive layers 28s and 282 are interposed between the conductive layers 28s and 282, respectively, to prevent spikes and improve the internal wiring [130-m plate 2
It is possible to prevent defects due to short circuits in 1111. As a result, highly reliable internal wiring can be realized economically and efficiently.

In the N-channel MOS transistor according to the present invention, as shown in FIG.
Internal wiring 3 via conductive layers 291 and 292 to 1,282
In order to provide 0, the aspect ratio is improved as mentioned above,
It can prevent spikes.

In the above embodiment, a case was described in which a conductive layer made of single crystal silicon was provided in the contact hole, but the present invention is not limited to this, and similar effects can be expected even if a conductive layer made of polycrystalline silicon is provided.

Further, in the above embodiment, a case has been described in which a conductive layer is provided in the contact hole of the silicon oxide film on the source/drain region, but the present invention is not limited to this. For example, as shown in FIG. A conductive layer made of silicon may also be provided. Note that 321 and 322 in the figure are conductive layers made of polycrystalline silicon provided in the contact holes 281 and 282, respectively. In the case of FIG. 4 as well, the same effects as in the above embodiment can be obtained.

Further, in the above embodiment, the case where the application is applied to an N-channel MOS transistor has been described, but the application is not limited to this.
(Complementary type) MOS transistors, bipolar transistors, etc. can be similarly applied.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to provide a semiconductor device that prevents spikes, improves the aspect ratio, and has internal wiring with good step coverage, and a method for manufacturing the same.

[Brief explanation of the drawing]

FIGS. 1(a) to (C) are cross-sectional views showing the manufacturing method of an N-channel MOS transistor according to an embodiment of the present invention in the order of steps; FIGS. 2 and 3 are cross-sectional views of a conventional semiconductor device, respectively; FIG. 4 shows an N-channel MOS according to another embodiment of the present invention.
FIG. 2 is a cross-sectional view of a transistor. 21... P type silicon substrate, 22... Field oxide film, 23... Gate oxide film, 24... Gate electrode, 25... N+ type source region, 26... N+ type source region Drain region, 27...CVD5IO2 film, 281
．． 282...Opening (contact hole), 291.29
2.32t, 322... Conductor 1i11.30... Internal wiring. Applicant's agent Patent attorney Takehiko Suzue Figure 1

Claims (3)

[Claims] (1) A semiconductor substrate, a diffusion layer provided on the surface of the semiconductor substrate, an insulating film provided on the semiconductor substrate and having an opening in a portion corresponding to the diffusion layer, and a semiconductor substrate exposed from the opening. 1. A semiconductor device comprising: a conductive layer made of single crystal silicon or polycrystalline silicon provided above; and an internal wiring connected to the diffusion layer provided in the opening. (2) A semiconductor substrate, a diffusion layer provided on the surface of the semiconductor substrate, a wiring layer made of polycrystalline silicon provided on the semiconductor substrate, and a wiring layer provided on the semiconductor substrate and connected to the diffusion layer and the wiring layer. an insulating film having openings in corresponding portions, a conductive layer made of polycrystalline silicon provided on the semiconductor substrate and wiring layer exposed from the opening, and the wiring layer and wiring provided in the opening. 2. The semiconductor device according to claim 1, further comprising internal wirings connected to the respective layers. (3) forming a diffusion layer on the surface of the semiconductor substrate; forming an insulating film on the semiconductor substrate; selectively removing the insulating film on the diffusion layer to form an opening; It is characterized by comprising the steps of selectively forming a conductive layer made of single crystal silicon or polycrystalline silicon in the opening, and forming an internal wiring connected to the conductive layer in the opening. A method for manufacturing a semiconductor device.