JPH03191574A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enhance a resistant property to an electrostatic breakdown by a method wherein a silicon film is formed on the surface of a source-drain diffusion layer formed on a silicon substrate, a high-melting metal film formed on the surface of the silicon film is formed and a high-melting metal silicide film is formed on the surface of the silicon film by a reaction. CONSTITUTION:A field oxide film 2 is formed selectively on one main face of a P-type silicon substrate 1; an element formation region is partitioned; a source region and a drain region 8. 9 of an opposite conductivity type, i.e., of an N<+> type, are provided inside the element formation region so as to be aligned with gate electrodes 4, 5; and insulating sidewall parts 10 are formed on side faces of the gate electrodes 4, 5. A silicon film 11 is grown on the surface of the N<+> type diffusion layers 8, 9. A titanium film 12 is deposited on the surface including the silicon film 11; it is reacted with the silicon film 11; a titanium silicide film 13 is formed; and after that, the titanium film 12 which has not been reacted is removed; a high-melting metal silicide film is formed. Thereby, it is possible to relax that an electric current supplied form a contact is concentrated in gate-electrode end parts of the sourcediffusion layer and the drain-diffusion layer 8, 9; and it is possible to enhance an electrostatic breakdown strength.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having an insulated gate field effect transistor.

[Conventional technology]

Due to the increasing density of semiconductor integrated circuits, element dimensions are becoming increasingly finer. For this reason, insulated gate field effect transistors (hereinafter referred to as MOS transistors) must also be reduced in size, but it is known that short channel effects pose a problem in this case.

One possible way to prevent the short channel effect is to reduce the diffusion depth of the source and drain of the transistor. However, if the diffusion layer is made shallow, the layer resistance becomes high, which causes the problem that the wiring resistance due to the diffusion layer increases and the operating speed of the circuit decreases significantly.

As a method to solve the above problem, as shown in FIG. 5, a titanium film is deposited on the surface of the N+ type scattering layer 89 in the source/drain region formed on the P type silicon substrate 1, and then heat treatment is performed. Accordingly, a method has been proposed in which a titanium silicide film 13 is formed by causing a reaction between a titanium film and a silicon substrate 1 to realize a low resistance of a shallow diffusion layer.

[Problem to be solved by the invention]

The above-mentioned conventional semiconductor device suffers from electrostatic breakdown (electrostat) in a MOS (MOS) transistor having a high melting point metal silicide film formed by directly reacting with the surface of a diffusion layer.
For example, the problem of deterioration of IC discharge (ESD) withstand voltage has been
ng-Long Chen) et al.
ical Digest) 1986, 484-48
It is reported on page 7.

This is because the surface of the diffusion layer has a low resistance due to the high melting point metal silicide film, so the current supplied from the mount concentrates on the end of the gate electrode of the source/drain diffusion layer, resulting in local thermal damage to the junction. It is thought that this is because it is more likely to occur.

[Means to solve the problem]

The semiconductor device of the present invention includes: - an element formation region partitioned by a field oxide film provided on one principal surface of a conductive type semiconductor substrate; and a gate electrode provided on a gate insulating film provided on the surface of the element formation region; and an insulating sidewall portion provided on a side surface of the gate electrode, and an insulating sidewall portion adjacent to the sidewall portion in a semiconductor device having source/drain regions of opposite conductivity type provided in the element formation region in alignment with the gate electrode. and a high melting point metal silicide film provided on the upper surface of the silicon film.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1A to 1H are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the manufacturing method of the first embodiment of the present invention.

First, as shown in FIG. 1(a), a P-type silicon substrate 1
0- A field oxide film 2 is selectively provided on the main surface to define an element formation region, and a gate oxide film 3 is formed by thermally oxidizing the surface of the element formation region. Next, a polycrystalline silicon film 4 and a tungsten silicide film 5 are sequentially deposited to a thickness of 0.1 to 0.3 μm on the surface including the gate oxide film 3 by a vapor phase growth method, and the tungsten silicide film 5 is A silicon oxide film 6 is deposited to a thickness of 0.05 to 0.2 μm by vapor phase growth.

Next, a photoresist film 7 is applied and patterned on the silicon oxide film 6 to form a pattern for forming a gate electrode.

Next, as shown in FIG. 1(b), using the photoresist film 7 as a mask, the silicon oxide film 6, the tungsten silicide film 5, and the polycrystalline silicon film 4 are sequentially etched and removed. A gate electrode having a two-layer structure of a silicon silicide film 5 and a silicon silicide film 5 is formed. Next, after removing the photoresist film 7, the gate electrode and field oxide film 2 are removed.
Using the mask as a mask, arsenic ions are implanted to form an N+ type scattering layer 89 for source/drain regions in the element formation region.

Next, as shown in FIG. 1(c), a silicon oxide film 10 is deposited on the surface including the gate electrode by vapor phase growth.

Next, as shown in FIG. 1(d), the entire surface is anisotropically etched to leave the silicon oxide film 10 only on the side surfaces of the gate electrode and remove the silicon oxide film 10 in other areas, thereby forming an N+ type silicon oxide film. The surface of the dispersed layer 89 is exposed.

Next, as shown in FIG. 1(e), the N+ type scattering layer 89
A silicon film 11 is grown on the surface of the silicon film 11 using a selective growth method.
It is grown to a thickness of 0.4 μm.

Next, as shown in FIG. 1(f), a titanium film 12 of 0.05 to 0.0
．． Deposit to a thickness of 5 μm.

Next, as shown in FIG. 1(g), the titanium film 12 and the silicon film 11 are caused to react with each other by heat treatment to form a titanium silicide film 13.
After forming, the unreacted titanium film 12 is removed.

Next, as shown in FIG. 1(h), a PSG film 14 is deposited as an interlayer insulating film over the entire surface, and an aluminum film 15 is deposited on the surface including the zero-order contact hole to selectively form a contact hole. Then, a wiring is formed which connects to the titanium silicide film 13 in the contact hole and extends over the PSG film 14.

FIGS. 2(a) to 2(d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the manufacturing method of the second embodiment of the present invention.

As shown in FIG. 2(a), after forming up to the gate oxide film 3 through the same steps as in the first embodiment, a polycrystalline silicon film 4 and a silicon oxide film 6 are sequentially formed on the gate oxide film 3. The silicon oxide film 6 and the polycrystalline silicon film 4 are selectively and sequentially etched to form a gate electrode. Next, using the gate electrode and field oxide film 2 as a mask, phosphorus ions are implanted at a low concentration into N- type diffusion layers 16 and 1.
form 7. Next, a silicon oxide film 10 is deposited on the surface including the gate electrode, and then etched back to form a side wall portion, leaving the silicon oxide film 1o only on the side surfaces of the gate electrode, and using the side wall portion and field oxide film 2 as a mask. N-type diffusion layer 16.17 by implanting arsenic ions at high concentration
An N+ type scattering layer 89 connected to the N+ type scattering layer 89 is formed. Next, a polycrystalline silicon film 18 doped with phosphorus is deposited by vapor phase growth, and a photoresist film 1 is deposited on the polycrystalline silicon film 18.
Apply No. 9 and butter it.

Next, as shown in FIG. 2(b), the photoresist film 19
The polycrystalline silicon film 18 is etched using as a mask.
A contact layer connected to the N+ type scattering layer 89 is provided.
Next, after removing the photoresist film 19, a molybdenum film 20 is formed over the entire surface.

It is deposited by the method.

Next, as shown in FIG. 2(c), a heat treatment is performed to cause the polycrystalline silicon film 18 and the molybdenum film 20 to react to form a molybdenum silicide film 21, and the unreacted molybdenum film 20 is removed.

Next, as shown in FIG. 2(d), a contact hole is formed by depositing a PSG film 14 on the entire surface as in the first embodiment, and the PSG film 14 is connected to the molybdenum silicide film 21 in the contact hole. A semiconductor device having an LDD structure is constructed by providing wiring made of an aluminum film 15 extending over the semiconductor device.

Note that the N+ type scattering layer 89 may be formed by diffusing phosphorus from the polycrystalline silicon film 18.

〔Effect of the invention〕

As explained above, the present invention involves forming a silicon film on the surface of a source/drain diffusion layer formed on a silicon substrate, and causing a high melting point metal film formed on the surface of the silicon film to react with the upper surface of the silicon film. By forming a high melting point metal silicide film, it has the effect of alleviating current concentration at the interface between the high melting point metal silicide film and the source/drain diffusion layer at the end of the gate electrode, and improving resistance to electrostatic discharge damage. .

[Brief explanation of drawings]

FIGS. 1(a) to (h) and FIGS. 2(a) to (d) show semiconductor chips in the order of steps for explaining the manufacturing method of the first and second embodiments of the present invention. 3 is a cross-sectional view showing an example of a conventional semiconductor device. 1... P-type silicon M plate, 2... Field oxide film, 3... Gate oxide film, 4...
...Polycrystalline silicon film, 5...Tungsten silicide film, 6...Silicon oxide film, 7...
・Photoresist film, 8, 9...N"1 diffusion layer,
10...Silicon oxide film, 11...River silicon:
t7L12...Titanium film, 13...Titanium silicideffl, 14...PSGffl, 15
・・Group・Aluminum film, 16.17・・・・・・N-
Type diffusion layer, 18... Polycrystalline silicon film, 19.
... Photoresist film, 20 ... Molybdenum film, 21 ... Molybdenum silicide film.

Claims (1)

[Claims] an element formation region partitioned by a field oxide film provided on one main surface of a semiconductor substrate of one conductivity type; a gate electrode provided on a gate insulating film provided on the surface of the element formation region;
In a semiconductor device having source/drain regions of opposite conductivity type provided in the element formation region in alignment with the gate electrode, an insulating side wall portion provided on a side surface of the gate electrode, and an insulating side wall portion adjacent to the side wall portion. A semiconductor device comprising: a silicon film provided on the surface of the source/drain region; and a high melting point metal silicide film provided on the upper surface of the silicon film.