JPS6050063B2 - Complementary MOS semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a complementary MOS semiconductor device and a method for manufacturing the same.

[Technical background of the invention]

A conventional complementary MOS semiconductor device, such as a CMSO inverter, has a structure as shown in FIG.

That is, 1 in the figure is a p-type silicon substrate, and an n-well region 2 is selectively provided in this substrate 1. N+ type source and drain regions 3 and 4 electrically isolated from each other are provided on the surface of the substrate 1 other than the n well region 2, and gate oxide is formed on the substrate 1 between these source and drain regions 3 and 4. A gate electrode 6 is provided with the film 5 interposed therebetween. An n-channel MOS transistor is constituted by the type-resistant source and drain regions 3 and 4, gate oxide film 5, gate electrode 6, and the like. On the other hand, p+ type source and drain regions 7 and 8 which are electrically isolated from each other are provided on the surface of the n well region 2, and a gate oxide is formed on the well region 2 between these p+ type source and drain regions 7 and 8. Ge. via membrane 9. A gate electrode 10 is provided. These p+
A p-channel MOS transistor is constituted by source and drain regions 7 and 8, a gate oxide film 9, a gate electrode 10, and the like. In addition, the gate region 6 of each transistor
, 10 is aluminum wiring, etc. The input is connected by a wire to become an input ``In'', and the n+ type and p+ type drain regions 4 and 8 are also connected by aluminum wiring or the like to become an output ``0ut''. Furthermore,
The P+ type source region 7 is connected to the power source by aluminum wiring, etc.
DD, and the n+ type source region 3 is connected to a reference power source Ss by aluminum wiring or the like.
[Problems of Background Art] While the above-described CMOS inverter has various advantages such as low power consumption, it has the following problems in terms of structure and manufacturing method.

(1) Since each transistor is configured in a planar manner, it is difficult to significantly improve the degree of integration.

(Ii) When miniaturization is attempted, there is a drawback that punch-through occurs due to the short channel effect.

(Since an IiO parasitic bipolar transistor is formed, a latch-up phenomenon may occur during operation, and the device may be destroyed.

(Iv) Since the gate electrode protrudes from the substrate surface and is not flat, it is difficult to form fine wiring.

(V) The channel length of each transistor is determined by the width of the gate electrode in the case of a polycrystalline silicon gate, but in the case of a fine element, variations in channel length tend to occur due to the relationship with the junction depth.

[Purpose of the invention]

The present invention provides a complementary MOS semiconductor device which is free from punch-through phenomenon and latch-up phenomenon and can dramatically improve the degree of integration, and which facilitates the formation of fine wiring for such a complementary MOS semiconductor device and has a good channel length. The purpose of this invention is to provide a manufacturing method that can be controlled in a controlled manner.

[Summary of the invention]

A complementary MOS semiconductor device according to a first aspect of the present invention includes a semiconductor substrate of a first conductivity type (for example, a p-type silicon substrate) and a well region of a second conductivity type selectively provided on the surface of the substrate (
an n-type well region), a first conductivity type (p+
a second conductivity type (type) formed in a stacked manner by sandwiching source and drain regions of the substrate surface and an insulating film thereon;
n+ type) source and drain regions, and a semiconductor serving as a channel region formed on both sides of a recess located between the first conductivity type source and drain regions and the second conductivity type source and drain regions. The method is characterized by comprising a layer, a gate insulating film coated on the surface thereof, and a gate electrode embedded in the recess via the gate insulating film and insulated from the substrate and well region. .

With such a structure, it is possible to dramatically increase integration, and punch-through and latch-up phenomena are eliminated. Further, in the method for manufacturing a complementary MOS semiconductor device according to the second invention of the present application, a well region of a second conductivity type (an n-type well region) is selectively formed on the surface of a semiconductor substrate of a first conductivity type (for example, a p-type silicon substrate). forming an impurity region of the first conductivity type 9 (for example, a p+ type drain region) in the well region of the second conductivity type, and forming an impurity region of the second conductivity type (for example, a p+ type drain region) on the surface of the substrate.
For example, after forming an insulating film on the entire surface (for example, forming a dowel-shaped drain region) and depositing an insulating film on the entire surface, a semiconductor film is further formed on the insulating film 1 corresponding to at least a portion of the first and second conductivity types. step, and a first conductivity type impurity region (p+ type drain region) is formed in a stacked manner in this semiconductor film, facing the first conductivity type impurity region (p+ type drain region).
forming a conductivity type region (p+ type source region) and a second conductivity type region (n+ type source region) in a stacked manner so as to face the second conductivity type impurity region (n+ type drain region); a step of sequentially etching away the semiconductor film between the p+ type and n+ type source regions, the insulating film, and the substrate surface deeper than the depth of the well region to form a recess; and a step of forming a recess in the recess. a step of embedding an insulator so that at least the p+ type and shochu-type drain regions on two surfaces of the substrate are exposed; 2 on the other side of the recess where the n+ type source and drain regions are exposed.
The method is characterized by comprising the steps of forming a gate insulating film on the surface of the semiconductor layer after forming channel regions each made of a semiconductor layer, and embedding a gate electrode in the recess via the gate insulating film. There are things to do.

According to this method, the channel length of each of the p-channel and n-channel transistors is determined by the thickness of the insulating film, and the channel length can be controlled extremely well, and fine wiring formats can be easily formed.

[Embodiments of the Invention] Hereinafter, embodiments of the present invention will be described with reference to the manufacturing method shown in FIGS. 2a-n.

(1) First, an n-type well region 12 with an impurity concentration of 2.times.10@16 cm@-3 was selectively formed on the surface of a p-type silicon substrate 11 (as shown in FIG. 2a).

Next, after forming a first isolation oxide film 13 according to a selective oxidation method, ions are implanted into the n-type well regions 12 using separate photoresist patterns (not shown).
A double-shaped drain region 14 was formed on the substrate 11 other than the n-type well region 12 (see FIG. 2b).
(Illustrated). A first CV with a thickness of 0.5 μm is applied to the entire surface.
After sequentially depositing a D-SiO2 film 16 and a 1 μm thick polycrystalline silicon film 17, laser annealing was performed to improve the crystallinity of the polycrystalline silicon film 17 (Fig. 2c).
(Illustrated). Subsequently, the p of the polycrystalline silicon film 17 is
A silicon nitride film pattern 18 was formed as an oxidation-resistant film on a region corresponding to at least part of the +-type and n+-type drain regions 14 and 15. Subsequently, the exposed polycrystalline silicon film 17 was oxidized according to a selective oxidation method to form a second isolation oxide film 19 and a polycrystalline silicon film pattern 20 surrounded by the second isolation oxide film 19 ( Second
Figure d shown). Next, the silicon nitride film pattern 1
8, a p+ type source region 21 is formed in a region corresponding to the p+ type drain region 14 of the polycrystalline silicon film pattern 20 by ion implantation using a separate photoresist pattern (not shown). N+ type source regions 22 are formed in regions corresponding to the drain region 15, and these p+ type and n+ type source regions 21, 22 are formed.
The polycrystalline silicon film pattern 2'' sandwiched between the two layers was left (as shown in FIG. 2e). 11) Next, after depositing a silicon nitride film 23 on the entire surface, a photoresist pattern 24 is formed, and the silicon nitride film 23,p is etched by reactive ion etching using this photoresist pattern 24 as a mask.
The first CVD-SlO2 film 16 is sequentially etched with a polycrystalline silicon film pattern 2' that includes a portion of the + type and resistive type source regions 21 and 22, and a polycrystalline silicon film pattern 2' that includes a portion of the p+ type drain region 14. The substrate 11 including a portion of the type well 12 and a portion of the n+ type drain region 15 was etched away until at least the junction depth of the n type well region 12 was reached.

As a result, the first CVD-SlO2 film 1
6 and the substrate 11 deeper than the junction depth of the n-type well region 12.
A recess 25 was formed over the surface (as shown in FIG. 2 f).
Subsequently, after removing the photoresist pattern 24, a second CVD film having a thickness equal to or larger than the width of the recess 25 is applied to the entire surface.
A SlO2 film 26 was deposited (as shown in FIG. 2g). Subsequently, this second CVD-SlO2 film 26 is etched by reactive ion etching, so that at least the p+ type and bulge-type drain regions 14 and 15 are exposed in the recess 25, and the n-type well region is exposed. 12 and the remaining CVD-SiO2 film 26' was buried to a thickness such that the substrate 11 was not exposed.

Subsequently, the silicon nitride film 23 was removed by etching (as shown in FIG. 2h). (Iiii) Next, the entire surface has a thickness of 8
After forming the 00A polycrystalline silicon layer 27, laser annealing was performed to improve the crystallinity of the polycrystalline silicon layer 27 (as shown in FIG. 2).

Subsequently, the polycrystalline silicon layer 27 was etched away by the thickness thereof by anisotropic etching such as reactive ion etching, leaving the polycrystalline silicon layer only on the side surfaces inside the recess 25. Subsequently, a photoresist pattern (not shown) is formed, and the polycrystalline polycrystal remains on the side surface of the recess 25 where the p+ type drain region 14 and source region 21 and the n+ type drain region 15 and source region 22 are not exposed. By selectively etching and removing only the silicon layer in its depth direction by plasma etching or the like, one side surface in the recess 25 where the p+ type drain region 14 and source region 21 are exposed, and one side surface facing this one side are removed. , residual polycrystalline silicon layers 281 and 282, which will become channel regions, are formed on the other side of the recess 25 where the n+ type drain region 15 and source region 22 are exposed (
(Illustrated in Figure 2j). Subsequently, thermal oxidation treatment is performed to reduce the thickness of the surfaces of the remaining polycrystalline silicon layers 281 and 282 and the exposed p+ type and resistive type source regions 21 and 22 by 6.
00A thermal oxide film (part becomes gate oxide film) 291
, ;29. was formed. At the same time, p-type impurities are transferred from the p+ type drain region 14 and source region 21 to the remaining polycrystalline silicon layer 281, and from the n+ type drain region 15 and source region 22 to the remaining polycrystalline silicon layer 281.
8. The n-type impurities were diffused into each layer (as shown in Figure 2k).
(1v) Next, after depositing a polycrystalline silicon film 30 with a thickness of 1h or more, which is the width of the recess 25, on the entire surface, 31p+ type ions were implanted into this polycrystalline silicon film 30 in order to lower the resistance ( (See Figure 2 1).

Subsequently, the polycrystalline silicon film 3 is etched back using an etch-back method.
The thermal oxide film (gate oxide film ) 291, 292 (as shown in FIG. 2m). After depositing a third CVD-SlO2 film 32 on the entire surface, contact holes 33... - Holes were opened. Next, after depositing an A1 film on the entire surface, patterning was performed to form N wirings 34, 35, 36, 37, 38,
A CMOS inverter was manufactured.

Note that the A1 wiring 34 is the input, and the N wiring 34 is the power supply ■
The N wiring 36 is connected to the DDD and the reference power source ■s, respectively.
Furthermore, the N wirings 37 and 38 are connected and become outputs (
(shown in Figure 2n). The CMOS inverter shown in FIG. An n+ drain region 15 provided on the substrate 11 and a first C
An n+ type source region 22 formed through the VD-SlO2 film 16, these p+ type drain region 14 and source region 21, and a cup-shaped drain region 15 and source region 2
Residual polycrystalline silicon layers 281 and 2 that will become channel regions provided on both sides of the recess 25 bored between the remaining polycrystalline silicon layers 281 and 2
8.

, thermal oxide films 291 and 292 that become gate oxide films coated on the surfaces thereof, and thermal oxide films 291 and 292 in the recess 25.
29. The gate electrode 31 (this gate electrode 31 is insulated from the substrate 11 and the well region 12 by the remaining CVD-SlO2 film 26'') is the main part. That is, p-channel MOS transistors are formed on the n-type well region 12 and n-channel MOS transistors on the p-type silicon substrate 11 in a stacked manner in the thickness direction of the substrate 11. Therefore, the device area is extremely small. Moreover, each transistor can be operated with one gate electrode 31, and the degree of integration can be dramatically improved.
Since the +-type and half-shaped source regions 21 and 22 are separated by the insulating film, latch-up phenomenon during operation can be prevented, and there is no risk of element breakdown. Furthermore,
A first CVD-SlO2 film 16 is interposed between the drain regions 14, 15 and the source regions 21, 22 of each transistor, so that no depletion layer spreads between them, and no punch-through occurs. Further, according to the manufacturing method of the above embodiment, in the step shown in FIG.
, 282 are formed, and thermal oxide films 291 and 29 which become gate oxide films in the step shown in FIG.

During the thermal oxidation treatment to form p-type impurities from the p+ type drain region 14 and source region 21 to the remaining polycrystalline silicon layer 281, the p-type impurity flows from the p+ type drain region 15 and source region 22 to the remaining polycrystalline silicon layer 281. Since n-type impurities are diffused into the layer 282, the channel length of each transistor is determined by the thickness of the first CVD-SiO2 film 16. Therefore, the channel length of each transistor can be well controlled. Furthermore, since the gate electrode 31 formed in the process shown in FIG.
8 can be easily formed. Moreover, as shown in FIG. 2d, if the polycrystalline silicon pattern 20 (which becomes the p+ type and breakdown type source regions 21 and 22) is formed by selective oxidation, the surface can be made almost flat, and a good source layer can be formed. It becomes possible to form highly reliable N wiring. Furthermore, this polycrystalline silicon pattern 20 may be formed by photolithography, and even with this method, the flatness is better than that of conventional CMOS inverters, so it is easy to form fine wiring. In the above embodiment, a polycrystalline silicon film formed on an insulating film such as a CVD-SiO2 film was subjected to laser annealing to improve crystallinity, but electron beam annealing may also be performed. [Effects of the Invention] As detailed above, according to the present invention, the punch-through phenomenon,
Provided is a complementary MOS semiconductor device that is free from latch-up phenomenon and can dramatically improve the degree of integration, and a manufacturing method that facilitates the formation of fine wiring for such a complementary MOS semiconductor device and allows good control of channel length. It is possible.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of a conventional CMOS inverter;
Figures a to n are cross-sectional views showing a CMOS inverter according to an embodiment of the present invention in the order of its manufacturing process. 11...p-type silicon substrate, 12...n-type well region, 13...first isolation oxide film, 14...
...p+ type drain region, 15...n+ type drain region, 16...first CVD-SiO2 film,
19... second isolation oxide film, 21...
p+ type source region, 22...n+ type source region,
25... recess, 26... second CVD-SlO
2 films, 26″...Residual CVD-SlO2 film, 28,,
282...Remaining polycrystalline silicon layer (channel region),
291,292...Thermal oxide film (gate oxide film), 3
1...Gate electrode, 32...Third C
VD-SiO2 film, 33... contact hole,
34, 35, 36, 37, 38...N wiring.

Claims (1)

[Claims] 1. A semiconductor substrate of a first conductivity type, a well region of a second conductivity type selectively provided on the surface of this semiconductor substrate, and a well region of a first conductivity type provided within this well region. an impurity region;
an impurity region of a second conductivity type provided on the surface of the substrate at a predetermined distance from the impurity region; and an impurity region of the first conductivity type arranged on the well region in a stacked manner opposite to the impurity region of the first conductivity type with an insulating film interposed therebetween. a semiconductor film of a first conductivity type; a semiconductor film of a second conductivity type disposed on the substrate in a stacked manner opposite to the impurity region of the second conductivity type with an insulating film interposed therebetween; a recess located and drilled across the substrate surface deeper than the depth of the insulating film and the well region; and a recess formed in the recess so as to be in contact with a portion of the first and second conductivity type impurity regions on the substrate surface. The buried insulator, one side surface in the recess where the first conductivity type impurity region and the first conductivity type semiconductor film are exposed, and the second conductivity type impurity region opposite to this one side surface. A channel region made of a semiconductor layer is provided on the other side of the recess where a conductive type semiconductor film is exposed, and a channel region formed of a semiconductor layer is embedded in the recess via a gate insulating film coated on the semiconductor layer, and the substrate and A complementary MOS semiconductor device comprising a gate electrode insulated with respect to a well region. 2 selectively forming a well region of a second conductivity type on the surface of a semiconductor substrate of a first conductivity type; forming an impurity region of a second conductivity type at a predetermined distance from the impurity region; depositing an insulating film over the entire surface;
forming a semiconductor film on the insulating film corresponding to at least a portion of the impurity regions of the first and second conductivity types; a step of forming regions of a first conductivity type in a stacked manner so as to face the impurity region of the second conductivity type, and a semiconductor film between the regions of the first conductivity type and the second conductivity type;
a step of sequentially etching away the substrate surface deeper than the depth of the insulating film and the well region to form a recess, and exposing at least a portion of the first and second conductivity type impurity regions on the substrate surface in the recess; a step of embedding an insulator so that the first conductivity type impurity region and the first conductivity type semiconductor film are exposed, and a second conductivity type impurity region opposite to this one side; forming a channel region made of a semiconductor layer on the other side surface of the recess where the semiconductor film and the semiconductor film of the second conductivity type are exposed; 1. A method for manufacturing a complementary MOS semiconductor device, comprising the step of burying a gate electrode insulated with respect to a well region. 3. A method for manufacturing a complementary MOS semiconductor device according to claim 2, characterized in that the semiconductor film and the semiconductor layer are subjected to laser annealing or electron beam annealing. 4. A method for manufacturing a complementary MOS semiconductor device according to claim 2, characterized in that a CVD method or an epitaxial method is used to form the semiconductor film or semiconductor layer. 5. In order to embed the gate electrode in the recess, a gate electrode material having a thickness of 1/2 or more of the width of the recess is deposited on the entire surface, and then a photolithography method or an etch-back method is used. A method for manufacturing a complementary MOS semiconductor device according to scope 2.