JPH0215651A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To precisely form a diffusion layer using the self-alignment technique by a method wherein a second conductor film is formed on the side-walls of a laminate of a first and second insulating films and a first conductor film through the intermediary of a third insulating film and then an impurity same as a semiconductor substrate in conductivity type is caused to be diffused from the second conductor film into the semiconductor substrate. CONSTITUTION:On the surface of a silicon substrate 1, an insulating film 2, a conductor film 3, and an insulating film 4 are formed. An oxide film 6 is formed on the surface where the silicon is exposed, and the oxide film 6 is retained on the sidewalls of the three-film laminate. A polycrystalline silicon layer doped overall with boron is deposited. The polycrystalline silicon layer is subjected to anisotropic etching and a sidewall 7 is formed on the patterned three-layer laminate. Next, heat treatment is accomplished for the formation of an insulating film 8 on the surface of the sidewall 7 and on the surface of element forming regions 10 on both sides thereof. Simultaneously, with boron being diffused from the sidewall 7 into the substrate 1, a P<+> inversion preventive layer 9 is formed by self-alignment. This method results in the inversion preventive layer 9 positioned just under the element isolation region, realizing excellent isolation characteristics.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a method for manufacturing a semiconductor device,
In particular, it relates to a method of forming element isolation regions.

[Conventional technology]

FIG. 2 is a sectional view of the element valve l111 region using a conventional shield plate l- conductor film. Element formation regions 10 are separated and present on the surface of a silicon substrate 1 that is lightly doped with P type. Further, each inversion prevention layer 9 is well formed on the surface of the silicon substrate 1 between the element forming regions 10°10.

Further, above it is a shield plate 1 covered with an insulating film 8.
- A conductor film 3 is formed.

FIG. 3 is a process cross-sectional view showing a method of forming the element isolation region shown in FIG. 2. In FIG. 3(a), a resist 5 is applied onto the silicon substrate 1 and patterned. In FIG. 3(b), with resist 5 as a mask, 1
1. Boron ions 11 are implanted to form the anti-inversion layer 9. In FIG. 3(C), the resist 5 is removed and the insulating film 2. A conductive film 3 for a shield plate and an insulating film 4 are laminated in sequence to form a three-layer film. In FIG. 3Cd), the three-layer film is patterned so that only the element isolation region remains. In FIG. 3(Q), the element formation region l! i10 is formed on both sides of the patterned three-layer film. In FIG. 3([), heat treatment is performed to form an insulating film 8 so as to cover the surface of the three-layer film and the element formation region 10, and further, boron ions 11 are diffused and activated to form a P+ inversion prevention layer 9. The position of the so-called P'inversion prevention W layer 9 is at the bottom of the three-layer film, but deviations may occur depending on the precision of mask alignment.

During operation, by fixing the potential of the shield plate conductor film 3 to the same potential as that of the silicon substrate 1 or a lower potential, adjacent element forming regions 10 that become the source and drain of the N-channel transistor are separated.

[Problem to be solved by the invention]

Since the conventional method of forming an element isolation region using the conductor film 3 for the shield plate 1 is configured as described above, P
It was not possible to use Selfa Line Men i technology to form the + inversion prevention layer 9, and it was not possible to form the P+ inversion prevention layer 9 with precision in the isolation region (below the shield plate conductor film 3) due to mask misalignment, etc. .

This invention was made in order to solve the above-mentioned problems. For example, in a method for forming an element isolation region, it is possible to form a diffusion layer such as an anti-inversion layer with high precision using self-alignment technology. The purpose of the present invention is to obtain a method for manufacturing a semiconductor device that can be manufactured using the following methods.

[Means to solve the problem]

A method for manufacturing a semiconductor device according to the present invention includes a step of forming a first insulating film on a main surface of a semiconductor substrate, a step of forming a first conductive film on the first insulating film, and a step of forming a first conductive film on the first insulating film. forming a second insulating film on the first conductor film; a step of patterning the second insulating film and the first conductor film; a step of forming a third insulating film on the side wall portion of the patterned first conductor 119; and a step of patterning the patterned first and second conductor films. forming a second conductive film into which impurities of the same conductivity type as the semiconductor substrate are introduced into the sidewalls of the insulating film and the first conductive film through the third insulating film; This method includes the step of diffusing impurities of the same conductive type as the semiconductor substrate from the conductive film of No. 2 to the semicircular substrate.

[Effect]

In the method of manufacturing a semiconductor device according to the present invention, a patterned first . After the step of forming a second conductive film on the sidewalls of the second insulating film and the first conductive film via the third insulating film, a second conductive film of the same conductivity type as the semiconductor substrate is formed from the second conductive film. Since the step of diffusing impurities into the semiconductor substrate is performed, the diffusion layer can be formed using self-alignment technology.

[Actual IMVA] An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a process sectional view showing a method of forming an element isolation region using a conductor film for a shield plate according to an embodiment of the present invention.

In FIG. 1(a), the surface of a silicon substrate 1 is thermally oxidized to form an insulating film 2, and then arsenic or phosphorus is doped to lower the resistance of the polycrystalline silicon substrate 1, which becomes a conductor film 3. A silicon film is laminated by the cVD method, and an insulator 14 is formed thereon. Further, a resist 5 is applied thereon and patterned.

In FIG. 1(b), an insulation layer is applied to the element isolation region using the resist 5 as a mask. 2. Seam film 3 for shield plate
and patterning to leave a 3m film of the insulating film 4,
After that, the resist 5 is removed.

In FIG. 1(C), oxidized ntA is present on the exposed silicon surface.
6 and patterned by etching 3
The oxide film 6 is left only on the side surfaces of the layer film.

In FIG. 1(d), boron-doped polycrystalline silicon doped with boron is deposited over the entire surface.

Furthermore, anisotropic etching was performed on the boron-doped polycrystalline silicon, resulting in a pattern of 31!111! A side wall 7 is formed on the side wall of the.

In FIG. 1(e), an insulating film 8 is formed on the surface of the side wall 4-lua and the element formation region 10 on both sides thereof by heat treatment, and at the same time, an insulating film 8 is formed in the silicon substrate 1.
By diffusing boron therein, the P+ inversion prevention layer 9 is formed by self-alignment. In the above manner, the structure shown in the figure is obtained.

As in the conventional case, during operation, the potential of the shield plate conductor film 3 is fixed at the same potential as that of the silicon substrate 1 or a lower potential, thereby separating and covering the adjacent element forming regions 10 that become the source and drain of the N-channel transistor. .

In addition, since the P+ inversion prevention layer 9 is formed by boron diffusion by the self-alignment [-] from the sidewall 7, the P+ inversion prevention layer 9 can be formed directly under the element isolation region, providing deeper isolation characteristics. Obtainable.

In the above embodiment, P-type silicon substrate 1 is used, but N-type silicon substrate 1 may also be used. In that case, arsenic or phosphorus is doped instead of boron in sidewall 7, and these are diffused into silicon substrate 1. By doing so, an N+ inversion prevention layer is formed.

Furthermore, during operation, by fixing the shield plate conductor film 3 to the same potential as the substrate or higher potential,
Adjacent element formation regions are separated.

[Effects of the Invention] As described above, according to the present invention, the patterned first . After the step of forming a second conductive film on the sidewalls of the second insulating film and the first conductive film via the third insulating film, a second conductor film of the same conductivity type as the semiconductor substrate is formed from the second conductor n9. Since a step of diffusing impurities into a semiconductor substrate is performed, a method for manufacturing a semiconductor device is provided in which a diffusion layer such as an anti-inversion layer can be formed with high accuracy using self-alignment technology, for example, in a method for forming an element isolation region. You can do it.

[Brief explanation of the drawing]

FIG. 1 is a process cross-sectional view of a method for forming an element isolation region according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of a conventional element force M region, and FIG. 3 is a process cross-sectional view of a conventional element isolation region forming method shown in FIG. FIG. 3 is a process cross-sectional view of a region forming method. In the figures, 1 is a silicon substrate, 2, 4 and 6 are insulating films, 3 is a conductive film for a shield plate, 7 is a night wall, and 9 is a P"inversion prevention layer. In addition, the same reference numerals in each figure are the same number or equivalent. Figure 1 agent person Iwa Masu Yudai] Figure (C) (d) Sidewall diagram Figure (e) Father rainbow proboscis layer diagram (a) / (b) (C) Figure Diagram

Claims (1)

[Claims] (1) A method for manufacturing a semiconductor device, comprising: forming a first insulating film on the main surface of a semiconductor substrate; forming a first conductive film on the first insulating film; forming a second insulating film on the first conductive film; patterning the first and second insulating films and the first conductive film; and sidewalls of the patterned first conductive film. forming a third insulating film on the patterned first and second insulating films and the first insulating film;
forming a second conductor film into which an impurity of the same conductivity type as that of the semiconductor substrate is introduced via the third insulating film on a side wall of the conductor film; A method for manufacturing a semiconductor device, comprising the step of diffusing impurities of the same conductivity type as the semiconductor substrate into the semiconductor substrate.