JPH0369137A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To restrain a channel stopper from being spread in the transverse direction, to reduce the effective channel width of a transistor and to prevent the operating current from being reduced and the breakdown strength of one isolated element from being lowered by a method wherein impurities for the channel stopper are ion- implanted by making use of the silicon oxide film on the sidewall of an opening as a mask. CONSTITUTION:A silicon nitride film 3 is deposited on a semiconductor substrate 1 of one conductivity type; the silicon nitride film 3 in an element formation region is etched selectively to form an opening part. Then, a silicon oxide film 4 is deposited on the surface including said opening part; impurities of one conductivity type are ion-implanted by making use of the silicon nitride film 3 and the silicon oxide film 4 on the sidewall of the opening part as a mask; a region 5 of one conductivity type is formed on the semiconductor substrate 1 in the opening part. Then, the silicon oxide film 4 is removed; after that, an element-isolation oxide film 6 is formed by making use of the silicon nitride film 3 as a mask by means of a thermal oxidation method. After that, e.g. the silicon nitride film 3 is removed, then, an N<+> type diffusion layer 7 for a source and a drain is formed so as to be aligned with the silicon oxide film 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor integrated circuit, and particularly to a method of manufacturing a semiconductor integrated circuit including a channel stopper.

[Conventional technology]

In conventional semiconductor device manufacturing methods, a method of forming an element isolation oxide film by selective oxidation is widely used as an example of forming an element isolation region.

FIGS. 2(a) to 2(d) are cross-sectional views of a semiconductor chip shown around step j for explaining a conventional method of manufacturing a semiconductor integrated circuit.

First, as shown in FIG.
A 0n silicon nitride film 3 is sequentially deposited.

Next, as shown in FIG. 2(b), the silicon nitride film 3 in the element isolation region is selectively etched to form an opening, and the silicon nitride film 3 is used as a mask to form a P-type channel stopper. Impurity ions are implanted to form P+ type region 5.

Next, as shown in FIG. 2(c), by utilizing the oxidation resistance of the silicon nitride film 3, a silicon oxide film 6 for element isolation is formed only in the element isolation region by a thermal oxidation method. Remove M3. At this time, in order to form the silicon oxide film 6 with a thickness of several 1100 nanometers, it is necessary to carry out thermal oxidation at high temperature for a long time, and the P+ type region 5 becomes more dense than before the silicon oxide film 6 is formed due to thermal diffusion of impurities. It has a horizontally spread distribution.

Next, as shown in FIG. 2(d), impurity ions are implanted using the silicon oxide film 6 as a mask to form N+ type scattered layers of the source and drain. At this time, the P+ type region 15 that has spread in the lateral direction comes into direct contact with the N+ type scattering layer 7.

[Problem to be solved by the invention]

In the conventional semiconductor integrated circuit manufacturing method described above, when an element isolation silicon oxide film is formed by thermal oxidation, the high concentration impurity implanted region introduced as a channel stopper in the previous step spreads laterally due to thermal diffusion. In the channel region of the transistor, the effective channel width is reduced and the operating current is reduced, and in the source/drain region of the transistor, the N++ source/drain diffusion layer and the P+ type channel/stopper implantation region are in direct contact. Therefore, there is a drawback that a high electric field is generated at the junction surface of the PN junction, and the element isolation withstand voltage is lowered.

[Means to solve the problem]

The method for manufacturing a semiconductor integrated circuit of the present invention includes the following steps: - depositing a silicon nitride film on a conductive type semiconductor substrate and selectively etching the silicon nitride film in an element formation region to form an opening; a step of depositing a silicon oxide film on the surface including the opening, and ion implantation of one conductivity type impurity into the semiconductor substrate in the opening using the silicon nitride film and the silicon oxide film on the side wall of the opening as a mask. The method includes a step of forming a region of one conductivity type, and a step of forming an element isolation oxide film using the silicon nitride film as a mask by a thermal oxidation method after removing the silicon oxide film.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1A to 1E are cross-sectional views of a semiconductor chip shown in order of steps for explaining an embodiment of the present invention.

First, as shown in FIG. 1(a), a silicon oxide film 2 with a thickness of several tens of nm and a silicon oxide film 2 with a thickness of several
00n silicon nitride film 3 is sequentially deposited and provided.

Next, as shown in FIG. 1(b), the silicon nitride film 3 in the element isolation formation region is selectively etched to form an opening.

Next, as shown in FIG. 1(c), a silicon oxide film 4 is uniformly formed on the surface including the openings by high temperature and low pressure chemical vapor deposition.
A P type impurity for forming a channel stopper is ion-implanted using the silicon nitride film 3 and the silicon oxide film 4 on the side wall of the opening as a mask to form a P1 type region 5. At this time, the P+ type region 5 is recessed from the end of the silicon nitride film 3 to the inside of the element isolation formation region by the thickness of the side wall of the silicon oxide film 4.

Next, as shown in FIG. 1(d), after removing the silicon oxide film 4, by using the oxidation resistance of the silicon nitride film 3, oxidation is applied only to the element isolation region by thermal oxidation. A silicon film 6 is formed and silicon nitride M3 is removed.

At this time, the P+ type region 5 expands laterally due to the thermal diffusion of the impurity compared to before forming the silicon oxide M6, but by making the thickness of the silicon oxide film 4 thicker than the diffusion distance of the impurity, A decrease in effective channel width can be prevented.

Next, as shown in FIG. 1(e), source/drain N+ type diffusions M7 are formed in alignment with the silicon oxide film 6. Here, since the P+ type region 5 is formed inside the end of the silicon oxide film 6, it is possible to prevent the N" type diffusion layer 7 from coming into direct contact with it.

Note that a silicon oxide film may be laminated on the silicon nitride film 3 in order to enhance the mask effect when implanting impurity ions for forming a channel stopper.

〔Effect of the invention〕

As explained above, the present invention deposits a silicon oxide film on the surface including the opening formed by selectively etching the silicon nitride film in the element isolation formation region, and removes the silicon oxide film on the sidewall of the opening. By using the mask as a mask and ion-implanting impurities for the channel stopper, the lateral spread of the channel stopper is suppressed, reducing the effective channel width of the transistor and reducing the operating current. This has the effect of preventing the device isolation breakdown voltage from decreasing due to direct contact with the device.

FIG. 3 is a cross-sectional view of a semiconductor chip shown in order of steps for explaining a method for manufacturing a semiconductor chip.

1... P-type silicon substrate, 2... silicon oxide film,
3... Silicon nitride film, 4... Silicon oxide film, 5
... P+ type region, 6... silicon oxide film, 7...
N+ type nuclear diffusion layer 8... silicon oxide film.

Claims (1)

[Claims] Depositing a silicon nitride film on a semiconductor substrate of one conductivity type, selectively etching the silicon nitride film in an element formation region to form an opening, and depositing a silicon oxide film on the surface including the opening. a step of ion-implanting one conductivity type impurity using the silicon nitride film and the silicon oxide film on the side wall of the opening as a mask to form a one conductivity type region in the semiconductor substrate in the opening; 1. A method of manufacturing a semiconductor integrated circuit, comprising the step of removing a silicon oxide film and then forming an element isolation oxide film by a thermal oxidation method using the silicon nitride film as a mask.