JP2707536B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device. SUMMARY OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device having a transistor and a capacitor on a semiconductor substrate, wherein a gate electrode is formed first, and a capacitor and a contact hole are formed in a self-aligned manner. In addition, the present invention provides a method for forming an element which can be adapted to a high degree of miniaturization by setting the alignment margin between the gate electrode and the contact hole to zero. [Prior art] A conventional semiconductor device, in particular, a method of manufacturing a semiconductor memory device using a capacitor is known in the art after forming an element isolation region.
After forming a capacitor region by trenching, stacking, or the like, a gate electrode is formed, and a contact hole is formed. [Problems to be Solved by the Invention] However, in the above-described prior art, the device must be arranged in consideration of the alignment margin of the gate electrode with respect to the capacitor region and the alignment margin of the contact hole with respect to the gate electrode. Was a factor that hindered the advancement of miniaturization. Therefore, the present invention solves such a problem, and an object of the present invention is to reduce the alignment allowance between the capacitor region and the gate electrode and the alignment allowance between the gate electrode and the contact hole so that the element can be highly miniaturized. To provide a method of manufacturing a semiconductor device which facilitates the above. [Technique for Solving the Problem] The method of manufacturing a semiconductor device according to the present invention includes a step of forming an element isolation film and a gate insulating film on a semiconductor substrate, and a step of forming a first insulating film on the gate insulating film. Forming a first impurity region and a second impurity region in the semiconductor substrate using the gate electrode, the first insulating film, and the element isolation film as a mask; Forming a sidewall insulating film on an insulating film and a side wall of the gate electrode, masking at least the first impurity region with a resist pattern, removing the resist pattern, the sidewall insulating film, the first insulating film, and the element isolation film; Forming a trench to be a capacitor region in a part of the second impurity region as a mask; removing the resist pattern; and forming a capacitor insulating film and a trench in the trench. Forming an element insulating film, the first insulating film, the side wall insulating film, the first impurity region, and an interlayer insulating film on the capacitor electrode; and forming the first insulating film and the capacitor electrode. Etching the interlayer insulating film on the first impurity region so as to be self-aligned with the sidewall insulating film, and forming a wiring contacting the first impurity region. Embodiment An embodiment will be described below in detail with reference to FIG. Step 1 FIG. 1 (a) After forming an isolation oxide film 102 on a P-type semiconductor substrate 101, a gate oxide film 103 is formed by a thermal oxidation method, and a first polycrystalline silicon 104 is formed thereon. 2000-4000Å Formed by chemical vapor deposition and thermally diffuses phosphorus at 800-1000 ° C. Next, after forming the first nitride film 105 of 2000 to 4000 ° by chemical vapor deposition, a thermal oxide film 106 of 100 to 200 ° is formed on the surface of the first nitride film 105 at 1000 to 1200 ° C. . Step 2 FIG. 1 (b) The thermal oxide film 106 is etched using the resist pattern as a mask, the first nitride film 105 is etched using the thermal oxide film 106 as a mask, and the first nitride film 105 is etched. After the first polycrystalline silicon 106 is etched using the mask as a mask, N-type impurities are ion-implanted and thermal annealing is performed to thereby form an N-type impurity layer.
107 (first impurity region) and 108 (second impurity region) are formed. Step 3 FIG. 1 (c) After a second nitride film is formed over the entire surface of 2000 to 4000 ° by chemical vapor deposition, the entire surface is etched with reactive ions to form a nitride film sidewall 109. Step 4 FIG. 1 (d) After masking the N-type diffusion layer 107 with a resist pattern 110, a part of the gate oxide film 103 is removed with dilute hydrofluoric acid. Step 5: FIG. 1 (e) The resist pattern 110 and the element isolation oxide film 102,
Using the first nitride film 105 and the nitride film sidewall 109 as a mask, the P-type semiconductor substrate 101 is exposed to reactive ions for 3 to 3 minutes.
Etching is performed by 5 μ to form a capacitor region 111. Step 6: FIG. 1 (f) After removing the resist pattern 110, the capacitor region 111 is thermally oxidized to form a capacitor oxide film 112, and then a second polycrystalline silicon 113 is formed by chemical vapor deposition. The second polycrystalline silicon 113 is formed using the resist pattern as a mask.
To form a capacitor electrode. Step 7 FIG. 1 (g) The oxide film 114 for interlayer insulation was formed by a chemical vapor deposition method for 3000 times.
Forming ~ 6000mm. Step 8: FIG. 1 (h) The interlayer insulating oxide film 114 using the resist pattern as a mask.
After forming a contact hole, Al for wiring material is formed by a sputter method. [Effects of the Invention] As described above, according to the method of manufacturing a semiconductor device of the present invention, a capacitor region can be formed in a self-aligned manner with respect to an element isolation film and a gate electrode side wall insulating film, and the same gate electrode can be formed. On the other hand, since the contact hole adjacent to the gate electrode can be formed in a self-aligned manner via the insulating film on the gate electrode and the insulating film on the side wall of the gate electrode, the semiconductor device can be highly miniaturized.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 (a) to 1 (h) are main cross-sectional views showing steps of a semiconductor device of the present invention. 101 P-type semiconductor substrate 102 Element isolation oxide film 103 Gate oxide film 104 First polycrystalline silicon film 105 First nitride film 106 Thermal oxide films 107 and 108 N-type Diffusion layer 109 Nitride film sidewall 110 Resist pattern 111 Capacitor region 112 Capacitor oxide film 113 Second polycrystalline silicon 114 Interlayer insulating oxide film 115 Al wiring material

Claims (1)

(57) [Claims] Forming an element isolation film and a gate insulating film on a semiconductor substrate; forming a gate electrode on which a first insulating film is provided on the gate insulating film; the gate electrode and the first insulating film Forming a first impurity region and a second impurity region in the semiconductor substrate using the element isolation film as a mask; forming a side wall insulating film on the side wall of the first insulating film and the gate electrode; Masking one impurity region with a resist pattern; forming a trench portion to be a capacitor region in a part of the second impurity region using the resist pattern, the sidewall insulating film, the first insulating film, and the element isolation film as a mask; Removing the resist pattern and forming a capacitor insulating film and a capacitor electrode in the groove portion; the element isolation film, the first Forming an interlayer insulating film on the insulating film, the sidewall insulating film, the first impurity region, and the capacitor electrode; forming the first insulating film and the first insulating film so as to be self-aligned with the sidewall insulating film; Etching the interlayer insulating film on the impurity region to form a wiring contacting the first impurity region.