JPH088208A - Formation method of contact hole in semiconductor element - Google Patents
Formation method of contact hole in semiconductor elementInfo
- Publication number
- JPH088208A JPH088208A JP6325101A JP32510194A JPH088208A JP H088208 A JPH088208 A JP H088208A JP 6325101 A JP6325101 A JP 6325101A JP 32510194 A JP32510194 A JP 32510194A JP H088208 A JPH088208 A JP H088208A
- Authority
- JP
- Japan
- Prior art keywords
- contact hole
- protective film
- forming
- film
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体素子のコンタクト
ホ−ル形成方法に関するものであって、特に絶縁酸化膜
（Interpoly Oxide Film）形成の前に保護膜を接合領域
の上部にのみ形成し、コンタクトホ−ルの形成の時発生
する接合領域のエッチングを防止し、コンタクト抵抗を
減少させることの出来る半導体素子のコンタクトホ−ル
の形成方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole of a semiconductor device, and in particular, a protective film is formed only on an upper portion of a junction region before forming an insulating oxide film (Interpoly Oxide Film). The present invention relates to a method of forming a contact hole of a semiconductor device capable of preventing the contact region from being etched when the contact hole is formed and reducing the contact resistance.
【０００２】[0002]
【従来の技術】一般に半導体素子が高集積化されている
ことによって接合の大きさ及び深さが減少し、またコン
タクトホ−ルの大きさも減少する。コンタクトホ−ルの
形成のためのエッチング工程時、接合領域のシリコン基
板はエッチング損傷を受けるようになり、そのため素子
の特性が低下する。特に低い接合の深さを有する素子か
らはもっと激しくなる。2. Description of the Related Art Generally, as semiconductor devices are highly integrated, the size and depth of junctions are reduced and the size of contact holes is also reduced. During the etching process for forming the contact holes, the silicon substrate in the bonding area is damaged by etching, which deteriorates the characteristics of the device. It is even more severe from devices with particularly low junction depths.
【０００３】[0003]
【発明が解決しようとする課題】このようなシリコン基
板の接合領域のエッチングを減少させるためには酸化膜
とシリコン基板とのエッチング選択比が大きいガスを用
いてコンタクトを形成するなどの多くの研究が進行中で
あるものの、シリコン基板のエッチングは不可避な状況
である。In order to reduce the etching of the junction region of the silicon substrate, many studies have been conducted such as forming a contact using a gas having a large etching selection ratio between the oxide film and the silicon substrate. However, the etching of the silicon substrate is inevitable.
【０００４】また、コンタクトホ−ルの大きさが減少す
ると、コンタクト抵抗が増加する。このようなコンタク
ト抵抗を減少させるためには、接合領域の大きさに対応
するコンタクトホールを形成しなければならないが、コ
ンタクトホ−ル形成時にミスアライン（misalign）が発
生するため正確なコンタクトホ−ルの形成をすることが
難しい。Further, when the size of the contact hole is reduced, the contact resistance is increased. In order to reduce such contact resistance, it is necessary to form a contact hole corresponding to the size of the junction region. However, since a misalignment occurs when forming the contact hole, an accurate contact hole is formed. Is difficult to form.
【０００５】また、コンタクトホ−ルの大きさが大きけ
ればウェットまたはドライ（wet または dry）エッチン
グ方法によって形成されたコンタクトホ−ルに金属配線
を形成した時、電気的な信号を伝達する他の配線との電
気的な攪乱と段落を誘発する。In addition, if the contact hole is large in size, when a metal wire is formed on the contact hole formed by a wet or dry etching method, another type of signal for transmitting an electrical signal is formed. Induces electrical perturbations and paragraphs with wiring.
【０００６】そのため、接合領域の上にコンタクトホ−
ルを形成する時にはコンタクトホ−ルの上部の直角面を
所定の傾斜面で形成し、一定距離の工程マ−ジン（marg
in）を置いてコンタクトホ−ルを形成しなければならな
い。Therefore, a contact hole is formed on the bonding area.
When forming the contact hole, the right-angled surface of the upper portion of the contact hole is formed with a predetermined inclined surface, and the process margin (marg
in) to form the contact hole.
【０００７】コンタクト抵抗減少の一つの方法として接
合領域上の全面にTiSi2 を形成したセルフアラインジャ
ンクション（self-aligned junction ）工程が多く研究
されているものの、これはセルフアラインジャンクショ
ンの形成時にシリコン基板を消耗し実際の接合の深さが
低くなり、TiSi2 の熱的な不安定性によってたくさんの
問題点が発生している。As a method of reducing the contact resistance, many studies have been made on a self-aligned junction process in which TiSi2 is formed on the entire surface of the junction region. It consumes and reduces the actual junction depth, and many problems are caused by the thermal instability of TiSi2.
【０００８】従って、本発明は絶縁酸化膜の形成前に保
護膜を接合領域の上部にのみ形成し、コンタクトホ−ル
の形成の後、保護膜を除去することによって、コンタク
トホ−ルの基底部での金属と接合領域との間の接触面積
を増加させ、また接合領域のシリコン基板のエッチング
を防止することが出来る半導体素子のコンタクトホ−ル
の形成方法を提供することにその目的がある。Therefore, according to the present invention, the protective film is formed only on the junction region before the insulating oxide film is formed, and after the contact hole is formed, the protective film is removed to form the base of the contact hole. It is an object of the present invention to provide a method for forming a contact hole of a semiconductor device, which can increase a contact area between a metal and a junction region in a contact portion and prevent etching of a silicon substrate in the junction region. .
【０００９】[0009]
【課題を解決するための手段】前記した目的を達成する
ための本発明のコンタクトホ−ル形成工程はシリコン基
板に接合領域を形成する段階と、前記接合領域を含む前
記シリコン基板上に保護膜を形成する段階と、前記保護
膜を予定されたコンタクトホ−ルの大きさより大きく前
記接合領域上に残留させるために前記保護膜の所定部分
をエッチングする段階と、前記接合領域上に残留させた
前記保護膜を含む全体構造の上部に絶縁酸化膜を形成す
る段階と、前記保護膜がある程度エッチングされるよう
に絶縁酸化膜を所定部分エッチングし第１コンタクトホ
−ルを形成する段階と、前記接合領域上に残留させた前
記保護膜を除去し第２コンタクトホ−ルを形成する段階
とからなることを特徴とする。The contact hole forming process of the present invention for achieving the above object comprises the steps of forming a bonding region on a silicon substrate and a protective film on the silicon substrate including the bonding region. Forming a protective layer, etching a predetermined portion of the protective layer to leave the protective layer larger than a predetermined size of the contact hole on the junction area, and leaving the protective layer on the junction area. Forming an insulating oxide film on the entire structure including the protective film; forming a first contact hole by etching a predetermined portion of the insulating oxide film so that the protective film is etched to some extent; And removing the protective film remaining on the bonding region to form a second contact hole.
【００１０】[0010]
【作用】前記手段によれば、コンタクトホールが形成さ
れる部分に保護膜を形成しコンタクトホール形成工程
時、シリコン基板のエッチングを防止し、その後保護膜
を除去し、コンタクト接触面積を増加させる。According to the above-mentioned means, the protective film is formed on the portion where the contact hole is formed, the etching of the silicon substrate is prevented during the step of forming the contact hole, and then the protective film is removed to increase the contact contact area.
【００１１】[0011]
【実施例】以下、添付された図面を参照して本発明を詳
細に説明する。図１Ａ乃至図１Ｆは保護膜による半導体
素子のコンタクトホ−ルを形成する段階を説明するため
に示した素子の断面図である。DETAILED DESCRIPTION OF THE INVENTION The present invention will now be described in detail with reference to the accompanying drawings. 1A to 1F are cross-sectional views of an element shown for explaining a step of forming a contact hole of a semiconductor element using a protective film.
【００１２】図１Ａはシリコン基板１上にフィ−ルド酸
化膜２を形成し、アクティブ領域（Active Region ）に
ゲ−ト電極３を形成し、ゲ−ト電極３の側壁にスペ−サ
酸化膜９を形成し、その後ｎまたはｐ不純物のイオン注
入工程によってジャンクション（Junction）領域４を形
成したのち、接合領域４の上部に保護膜５を全体的に形
成した状態の断面図である。In FIG. 1A, a field oxide film 2 is formed on a silicon substrate 1, a gate electrode 3 is formed in an active region, and a spacer oxide film is formed on a side wall of the gate electrode 3. 9 is a cross-sectional view of a state in which a junction region 4 is formed by an ion implantation process of n or p impurities after that, and then a protective film 5 is entirely formed on the junction region 4.
【００１３】保護膜５はシリコン基板１と後続工程によ
って形成される絶縁酸化膜に対してエッチング選択比が
大きい物質例えば、シリコンナイトライド（SixNy ）を
蒸着し形成する。The protective film 5 is formed by depositing a material having a large etching selection ratio with respect to the silicon substrate 1 and an insulating oxide film formed in a subsequent process, for example, silicon nitride (SixNy).
【００１４】図１Ｂは保護膜５をリソグラフィ及びエッ
チング工程によってコンタクトホ−ルが形成される領域
である接合領域４上に予定された大きさで残留させた状
態の断面図である。FIG. 1B is a sectional view showing a state in which the protective film 5 is left in a predetermined size on the junction region 4 which is a region where the contact holes are formed by the lithography and etching processes.
【００１５】予定された大きさで残留させた保護膜５は
金属配線と接合領域間の接触面積を増加させるための後
続工程によって形成されるコンタクトホ−ルの大きさよ
り大きく残留させる。そして保護膜５はコンタクトホ−
ルの形成時に発生するシリコン基板のエッチングを防止
する役割をする。The protective film 5 left with a predetermined size is left larger than the size of the contact hole formed in the subsequent process for increasing the contact area between the metal wiring and the junction region. The protective film 5 is a contact hole.
The silicon substrate has a role of preventing etching of the silicon substrate that occurs at the time of forming the film.
【００１６】図１Ｃは全体構造の上部に絶縁酸化膜６を
蒸着したのち、リソグラフィ及びエッチング工程によっ
て残留させた保護膜５がある程度エッチングされるよう
に絶縁酸化膜６を所定部分エッチングして第１コンタク
トホ−ル７Ａを形成した状態の断面図である。In FIG. 1C, an insulating oxide film 6 is deposited on the entire structure, and then the insulating oxide film 6 is partially etched so that the protective film 5 left by the lithography and etching process is etched to a certain extent. It is sectional drawing in the state which formed the contact hole 7A.
【００１７】第１コンタクトホ−ル７Ａは絶縁酸化膜６
をウェット及びドライエッチング工程によって順次にエ
ッチングし、第１コンタクトホ−ル７Ａの上部が傾斜し
た形状（Profile ）となるように形成する。そして第１
コンタクトホ−ル７Ａの形成のためのエッチング工程
時、残留させた保護膜５はシリコン基板１に形成された
接合領域４のエッチングを防止する役割をする。The first contact hole 7A is an insulating oxide film 6
Are sequentially etched by wet and dry etching processes to form an upper portion of the first contact hole 7A having an inclined profile. And the first
During the etching process for forming the contact hole 7A, the remaining protective film 5 serves to prevent the bonding region 4 formed on the silicon substrate 1 from being etched.
【００１８】図１Ｄは第１コンタクトホ−ル７Ａの接合
領域４上に残留させた保護膜５を除去し第２コンタクト
ホ−ル７Ｂを形成した状態の断面図である。FIG. 1D is a sectional view showing a state in which the protective film 5 left on the bonding region 4 of the first contact hole 7A is removed to form the second contact hole 7B.
【００１９】残留させた保護膜５を選択的にエッチング
する時用いられるエッチング溶液はシリコン基板１と絶
縁酸化膜６に対して保護膜５のエッチング選択比が大き
い化学溶液（例えば、保護膜がシリコンナイトライドで
ある場合燐酸（H3PO4 ））を用いて残留させた保護膜５
を除去する。The etching solution used for selectively etching the remaining protective film 5 is a chemical solution having a large etching selection ratio of the protective film 5 to the silicon substrate 1 and the insulating oxide film 6 (for example, the protective film is silicon. In the case of nitride, protective film 5 left with phosphoric acid (H3PO4)
Is removed.
【００２０】図１Ｅはタングステン10を選択的に蒸着し
第２コンタクトホ−ル７Ｂ内部を完全に埋めこんだ状態
の断面図であり、図１Ｆはアルミニウムスパッタリング
蒸着法を用いて金属配線８を形成した状態の断面図であ
る。FIG. 1E is a sectional view showing a state in which tungsten 10 is selectively vapor-deposited to completely fill the inside of the second contact hole 7B, and FIG. 1F shows the metal wiring 8 formed by the aluminum sputtering vapor deposition method. It is sectional drawing of the state.
【００２１】[0021]
【発明の効果】前述のように本発明によればコンタクト
ホ−ルの形成時、発生する接合領域のエッチングを防止
し、コンタクトホ−ル内で金属と接合領域の接触面積が
蒸着させられるためコンタクト抵抗を減少させることが
出来る卓越な効果がある。As described above, according to the present invention, the contact area between the metal and the contact area is vapor-deposited in the contact hole by preventing the etching of the contact area that occurs when the contact hole is formed. It has an outstanding effect of reducing the contact resistance.
【図１】本発明による半導体素子のコンタクトホ−ルを
形成する段階を説明するために示した素子の断面図であ
る。FIG. 1 is a cross-sectional view of an element shown for explaining a step of forming a contact hole of a semiconductor element according to the present invention.
１…シリコン基板 ２…フィ−ルド酸化膜 ３…ゲ−ト電極 ４…接合領域 ５…保護膜 ６…絶縁酸化膜 ７Ａ…第１コンタクトホ−ル ７Ｂ…第２コンタクトホ−ル ８…金属配線 ９…スペ−サ酸化膜 10…タングステン DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2 ... Field oxide film 3 ... Gate electrode 4 ... Junction area 5 ... Protective film 6 ... Insulating oxide film 7A ... 1st contact hole 7B ... 2nd contact hole 8 ... Metal wiring 9 ... Spacer oxide film 10 ... Tungsten
Claims (5)
法に於いて、シリコン基板に接合領域を形成する段階
と、前記接合領域を含む前記シリコン基板上に保護膜を
形成する段階と、前記保護膜を予定されたコンタクトホ
−ルの大きさより大きく前記接合領域上に残留させるた
めに前記保護膜の所定部分をエッチングする段階と、前
記接合領域上に残留させた前記保護膜を含む全体構造の
上部に絶縁酸化膜を形成する段階と、前記保護膜がある
程度エッチングされるように絶縁酸化膜を所定部分エッ
チングして第１コンタクトホ−ルを形成する段階と、前
記接合領域上に残留させた前記保護膜を除去し、第２コ
ンタクトホ−ルを形成する段階とからなることを特徴と
する半導体素子のコンタクトホ−ル形成方法。1. A method of forming a contact hole of a semiconductor device, comprising: forming a bonding region on a silicon substrate; forming a protective film on the silicon substrate including the bonding region; Etching a predetermined portion of the protective film to leave a film larger than a predetermined size of the contact hole on the junction region, and an overall structure including the protective film left on the junction region. A step of forming an insulating oxide film on the upper surface, a step of forming a first contact hole by etching a predetermined portion of the insulating oxide film so that the protective film is etched to some extent, and leaving the insulating film on the bonding region. And a step of forming a second contact hole by removing the protective film, a method of forming a contact hole of a semiconductor device.
コンナイトライドを蒸着し形成されることを特徴とする
半導体素子のコンタクトホ−ル形成方法。2. The method for forming a contact hole of a semiconductor device according to claim 1, wherein the protective film is formed by depositing silicon nitride.
トホ−ルは前記絶縁酸化膜をウェット及びドライエッチ
ング工程によって順次にエッチングして形成することを
特徴とする半導体素子のコンタクトホ−ル形成方法。3. The contact hole of a semiconductor device according to claim 1, wherein the first contact hole is formed by sequentially etching the insulating oxide film by wet and dry etching processes. Forming method.
トホ−ルはシリコン基板と絶縁酸化膜に対して保護膜の
エッチング選択比が大きい化学溶液によって保護膜を除
去して形成することを特徴とする半導体素子のコンタク
トホ−ル形成方法。4. The first contact hole according to claim 1, wherein the second contact hole is formed by removing the protective film with a chemical solution having a large etching selection ratio of the protective film to the silicon substrate and the insulating oxide film. A method for forming a contact hole of a semiconductor device, comprising:
コンナイトライドである場合、前記第２コンタクトホ−
ルはリン酸溶液によって前記残留された保護膜を除去し
て形成することを特徴とする半導体素子のコンタクトホ
−ル形成方法。5. The second contact hole according to claim 1, wherein the protective film is silicon nitride.
A method of forming a contact hole for a semiconductor device, wherein the residual protective film is removed with a phosphoric acid solution.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR93-29780 | 1993-12-27 | ||
| KR1019930029780A KR100187672B1 (en) | 1993-12-27 | 1993-12-27 | Method of forming contact hole in semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH088208A true JPH088208A (en) | 1996-01-12 |
Family
ID=19372786
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6325101A Pending JPH088208A (en) | 1993-12-27 | 1994-12-27 | Formation method of contact hole in semiconductor element |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH088208A (en) |
| KR (1) | KR100187672B1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9209087B2 (en) | 2010-10-13 | 2015-12-08 | Samsung Electronics Co., Ltd. | Semiconductor devices including etching stop films |
| WO2020262584A1 (en) * | 2019-06-26 | 2020-12-30 | ソニーセミコンダクタソリューションズ株式会社 | Semiconductor device and manufacturing method for same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0547700A (en) * | 1991-08-20 | 1993-02-26 | Sony Corp | Method of forming wiring |
| JPH05251404A (en) * | 1992-03-04 | 1993-09-28 | Nec Corp | Dry etching method for dielectric layer |
-
1993
- 1993-12-27 KR KR1019930029780A patent/KR100187672B1/en not_active IP Right Cessation
-
1994
- 1994-12-27 JP JP6325101A patent/JPH088208A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0547700A (en) * | 1991-08-20 | 1993-02-26 | Sony Corp | Method of forming wiring |
| JPH05251404A (en) * | 1992-03-04 | 1993-09-28 | Nec Corp | Dry etching method for dielectric layer |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9209087B2 (en) | 2010-10-13 | 2015-12-08 | Samsung Electronics Co., Ltd. | Semiconductor devices including etching stop films |
| US9401360B2 (en) | 2010-10-13 | 2016-07-26 | Samsung Electronics Co., Ltd. | Semiconductor devices including etching stop films |
| WO2020262584A1 (en) * | 2019-06-26 | 2020-12-30 | ソニーセミコンダクタソリューションズ株式会社 | Semiconductor device and manufacturing method for same |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100187672B1 (en) | 1999-06-01 |
| KR950021090A (en) | 1995-07-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6307226B1 (en) | Contact openings to electronic components having recessed sidewall structures | |
| KR100338413B1 (en) | Method for providing dual work function doping and protective insulating cap | |
| EP0076942B1 (en) | Method of making integrated circuit device comprising dielectric isolation regions | |
| US5482869A (en) | Gettering of unwanted metal impurity introduced into semiconductor substrate during trench formation | |
| KR940010564B1 (en) | Mosfet and manufacturing method thereof | |
| US5897359A (en) | Method of manufacturing a silicon/silicon germanium heterojunction bipolar transistor | |
| JPH0521338B2 (en) | ||
| US7301207B2 (en) | Semiconductor device capable of threshold voltage adjustment by applying an external voltage | |
| US6351038B1 (en) | Integrated circuitry | |
| JPH088208A (en) | Formation method of contact hole in semiconductor element | |
| JPH08255828A (en) | Semiconductor device and manufacture thereof | |
| KR100273320B1 (en) | Silicide Formation Method of Semiconductor Device_ | |
| US6261948B1 (en) | Method of forming contact openings | |
| US6303491B1 (en) | Method for fabricating self-aligned contact hole | |
| US6521517B1 (en) | Method of fabricating a gate electrode using a second conductive layer as a mask in the formation of an insulating layer by oxidation of a first conductive layer | |
| JP2707536B2 (en) | Method for manufacturing semiconductor device | |
| JP2604021B2 (en) | Method for manufacturing semiconductor device | |
| JPH05226466A (en) | Manufacture of semiconductor device | |
| JPH09213949A (en) | Semiconductor device manufacturing method | |
| JP2876612B2 (en) | Method for manufacturing semiconductor device | |
| JPH03163832A (en) | Semiconductor device | |
| KR930009476B1 (en) | Manufacturing method of self-aligned contact in semiconductor device | |
| JP3298183B2 (en) | Method for manufacturing semiconductor device | |
| KR19980082614A (en) | Method for manufacturing isolation structure of semiconductor device | |
| JPH08181312A (en) | Semiconductor device and its manufacture |