JPH08181312A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE: To obtain a self-aligned contact in which a gate electrode is not short-circuited with an interconnection layer even when the film thickness of a cap nitride film formed on the gate electrode for a MOS transistor is made small. CONSTITUTION: A cap nitride film 5 is made to protrude from side faces of a gate electrode 4, and parts under its protruding parts are filled with a sidewall oxide film 7. As a result, the isolation distance between the gate electrode 4 and a polycrystal silicon interconnection 9 becomes large, and the film thickness of the cap nitride film 5 can be made small. Consequently, the difference in level on the surface of a substrate 1 becomes small, and the step coverage of the polycrystal silicon interconnection 9 is enhanced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method, and is suitable for use in a semiconductor device such as a MOS transistor having a self-aligned source / drain contact.

[0002]

2. Description of the Related Art A method for forming a contact hole for forming a wiring layer connected to a source / drain diffusion layer of a MOS transistor in a self-aligning manner to prevent a short circuit between a gate electrode and the wiring layer is disclosed in, for example, Japanese Patent Application Laid-Open A method as described in JP-A-62-45069 is known. The wiring layer forming method described in the above publication will be described below with reference to FIG.

First, as shown in FIG. 5A, after a field oxide film 102 is formed on the surface of a P-type silicon substrate 101 by the LOCOS method, the field oxide film 102 is formed.
A thermal oxide film 103 is formed on the surface of the element formation region surrounded by. Then, a phosphorus-doped polycrystalline silicon film and a silicon nitride film are formed on the entire surface, and these are selectively removed by etching to remove the gate electrode 104 and the cap insulating film 105.
To form. Further, phosphorus is ion-implanted using the gate electrode 104 as a mask, so that the silicon substrate 10
An N-type source / drain 106 is formed on the surface portion 1.

Next, as shown in FIG. 5B, a contact hole 108 is formed in the interlayer insulating film 107 formed on the entire surface so as to reach the source / drain 106 and expose the sidewall of the gate electrode 104. Then, a silicon oxide film 109 is formed on the entire surface.

Next, as shown in FIG. 5C, the silicon oxide film 109 is anisotropically etched to form the interlayer insulating film 107, the gate electrode 104 and the cap insulating film 10.
A side wall oxide film 110 is formed at 5.

Next, as shown in FIG.
An aluminum electrode 111, which is a wiring layer connected to the drain 106, is formed so as to fill the contact hole 108.

According to the above means, the sidewall oxide film 110 is used to form the gate electrode 104 and the aluminum electrode 1.
A short circuit with 11 can be avoided, and the contact hole 10
It is not necessary to take sufficient design margin 8 and the element can be miniaturized.

[0008]

However, in the means disclosed in the above publication, the sidewall oxide film 1 for separating the gate electrode 104 and the aluminum electrode 111 from each other.
When the width of 10 is narrow, it was difficult to maintain the insulation between them. In particular, when the film thickness of the cap insulating film 105 is small, the gate electrode 104 and the aluminum electrode 11
1 and the gate electrode 10 are separated from each other via the extremely narrow portion of the tip end portion of the sidewall oxide film 110.
4 and the aluminum electrode 111 were short-circuited, and the reliability of the device was lost.

On the other hand, in order to prevent a short circuit between the gate electrode 104 and the aluminum electrode 111, the cap insulating film 10 is formed.
When the film thickness of No. 5 is increased, the step difference on the surface of the silicon substrate 101 is increased, the step coverage of the aluminum electrode 111 is deteriorated, and the aluminum electrode 111 and the source / drain 106 are not reliably connected. Was there. Therefore, the aluminum electrode must be formed after the contact portion is filled with a refractory metal such as tungsten, which inevitably increases the number of steps.

Therefore, an object of the present invention is to improve the reliability of the connection between the impurity diffusion layer and the wiring layer connected thereto by reducing the film thickness of the cap insulating film, and to improve the reliability of the connection between the gate electrode and the wiring layer. It is an object of the present invention to provide a semiconductor device having a self-aligned contact capable of surely preventing a short circuit of the semiconductor device and a manufacturing method thereof.

[0011]

In order to achieve the above object, the present invention provides a gate electrode formed on a semiconductor substrate via a gate insulating film, and impurity diffusion formed on the surface of the semiconductor substrate. In a semiconductor device having a layer and a wiring layer connected to the impurity diffusion layer, a cap insulating film is formed on the gate electrode so as to project from a side surface of the gate electrode, and the gate electrode and the wiring. The cap insulating film and the sidewall insulating film of the gate electrode separating the layer are formed so as to fill the void below the protruding portion of the cap insulating film.

In one aspect of the present invention, the cap insulating film is a silicon nitride film and the sidewall insulating film is a silicon oxide film.

A method of manufacturing a semiconductor device according to the present invention is
Selected by sequentially forming a first insulating film, a first conductive film, and a second insulating film on a semiconductor substrate, and anisotropically etching the second insulating film and the first conductive film. And removing each of them to form a cap insulating film and a gate electrode respectively, a step of isotropically etching the gate electrode by using the cap insulating film as a mask to side-etch the gate electrode, and the gate electrode By embedding the side-etched part of
A step of forming a third insulating film made of a material different from that of the cap insulating film on the entire surface, and a step of forming an impurity diffusion layer on the surface portion of the semiconductor substrate by performing ion implantation using the cap insulating film as a mask. And anisotropically etching the third insulating film using the cap insulating film as an etching stopper to expose the impurity diffusion layer and form a sidewall insulating film on the side surfaces of the cap insulating film and the gate electrode. And a step of forming a wiring layer connected to the impurity diffusion layer.

[0014]

In the semiconductor device of the present invention, the cap insulating film is formed so as to project from the side surface of the gate electrode, and the sidewall insulating film is formed so as to fill the void below the cap insulating film. Even when the thickness of the insulating film is small, the distance between the gate electrode and the wiring layer becomes longer than in the conventional case. Therefore, a short circuit between the gate electrode and the wiring layer can be surely prevented regardless of the width of the sidewall insulating film. Further, since it is not necessary to form the cap insulating film with a large film thickness, the step on the surface of the semiconductor substrate can be reduced and the step coverage of the wiring layer is improved, so that the wiring layer and the impurity diffusion layer can be reliably connected. To be done.

Further, in the method of manufacturing a semiconductor device of the present invention, since the sidewall insulating film is formed by anisotropic etching using the cap insulating film as an etching stopper, the sidewall insulating film is formed on the side-etched portion of the gate electrode. The film can be surely left. Therefore, the semiconductor device of the present invention can be obtained easily and with a small number of steps.

[0016]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

FIG. 1 is a sectional view of a semiconductor device including a MOS transistor according to this embodiment. In FIG. 1, a P-type silicon substrate 1 is element-isolated by a field oxide film 2, and a gate oxide film 3 having a thickness of about 20 nm is formed on the silicon substrate 1 in an element region surrounded by the field oxide film 2. A gate electrode 4 made of phosphorus-doped polycrystal silicon and having a film thickness of about 200 nm is formed through. Source / drain 8 which is an impurity diffusion layer doped with N-type impurities such as phosphorus is formed on the surface of the silicon substrate 1 on both sides of the gate electrode 4. The polycrystalline silicon wiring 9 having a film thickness of about 200 nm doped with N-type impurities such as phosphorus is used to connect the source / drain 8 and an external power source or the like to keep the source / drain 8 at a predetermined potential. It is connected to the drain 8.

A cap nitride film 5 having a film thickness of about 150 nm is formed on the gate electrode 4 so as to project laterally from the side surface of the gate electrode 4 by about 50 nm in the lateral direction. Then, sidewalls are formed on the side surfaces of the gate electrode 4 and the cap nitride film 5 so as to fill a void below the cap nitride film 5, that is, a recess surrounded by the cap nitride film 5, the gate electrode 4, and the gate insulating film 3. Oxide film 7 is formed. The sidewall oxide film 7 ensures the insulation between the gate electrode 4 and the polycrystalline silicon wiring 9.

Interlayer insulating film 1 formed so as to cover the entire surface
0, an aluminum wiring 11 is formed, and an interlayer insulating film 12 is formed so as to cover the aluminum wiring 11.
Are formed.

In the MOS transistor shown in FIG. 1, the cap nitride film 5 is formed so as to project from the side surface of the gate electrode 4, and the sidewall oxide film 7 is formed so as to fill the void under the cap nitride film 5. Therefore, the gate electrode 4 and the polycrystalline silicon wiring 9 are separated by a sufficient distance to prevent a short circuit between them. Therefore, the short circuit between the gate electrode 4 and the polycrystalline silicon wiring 9 is surely prevented.

Further, by reducing the film thickness of the cap nitride film 5, the step difference on the surface of the silicon substrate 1 is reduced. Therefore, the step coverage of the polycrystalline silicon wiring 9 is good, and the polycrystalline silicon wiring 9 and the source / drain 8 are reliably connected.

Next, a method of manufacturing the semiconductor device of FIG. 1 will be described with reference to FIGS. First, FIG. 2 (a)
As shown in, the LOCO is formed on the surface of the P-type silicon substrate 1.
After forming the field oxide film 2 by the S method, the gate oxide film 3 having a film thickness of about 20 nm is formed on the surface of the element region surrounded by the field oxide film 2 by the thermal oxidation method. Thereafter, the phosphorus-doped polycrystalline silicon film 14 having a film thickness of about 200 nm and the silicon nitride film 1 having a film thickness of about 150 nm are formed on the entire surface.
5 is formed into a film.

Next, as shown in FIG. 2B, the silicon nitride film 15 is selectively removed by etching using the photoresist 6 processed into a predetermined shape as a mask.
A cap nitride film 5 is formed on the polycrystalline silicon film 14.

Next, as shown in FIG. 2C, after the photoresist 6 is removed, anisotropic etching is performed using the cap nitride film 5 as a mask to selectively remove the polycrystalline silicon film 14. Then, the gate electrode 4 is formed under the cap nitride film 5. Incidentally, the gate oxide film 3 in the portion not covered with the gate electrode 4 may be removed by further etching.

Next, as shown in FIG. 3A, isotropic etching is performed using the cap nitride film 5 as a mask. By this etching, the gate electrode 4 is side-etched, and as a result, the cap nitride film 5 has a shape protruding laterally from the side surface of the gate electrode 4 by about 50 nm on each side. That is, the gate electrode 4 and the cap nitride film 5
Has a substantially T-shaped cross section.

Next, as shown in FIG. 3B, a silicon oxide film 17 having a film thickness of about 200 nm is formed on the entire surface by a CVD method. The silicon oxide film 17 fills the space under the protruding portion of the cap nitride film 5, which is the side-etched portion of the gate electrode 4. Thereafter, N-type impurities such as phosphorus are ion-implanted using the cap nitride film 5 as a mask and heat treatment is performed to form the source / drain 8 that is an N-type impurity diffusion layer on the surface portion of the silicon substrate 1. The ion implantation may be performed before the silicon oxide film 17 is formed or before the isotropic etching of the gate electrode 4.

Next, as shown in FIG. 3C, the silicon nitride film 17 and the gate oxide film 3 are anisotropically etched using the cap nitride film 5 as an etching stopper to expose the source / drain 8. Further, as a result of this anisotropic etching, a sidewall oxide film 7 is formed on the side surfaces of the gate electrode 4 and the cap nitride film 5 so as to fill the void under the protruding portion of the cap nitride film 5. As described above, in this embodiment, since the sidewall oxide film 7 is formed by anisotropically etching the cap nitride film 5 as an etching stopper, the silicon oxide film 17 is not over-etched, and the side of the gate electrode 4 is not etched. The sidewall oxide film 7 can be surely left in the etched portion.

Next, as shown in FIG. 4, the film thickness is 200 nm.
A pattern of the phosphorus-doped polycrystalline silicon wiring 9 is formed so as to be connected to each of the source / drain 8. Thereafter, the interlayer insulating film 10, the aluminum wiring 11 and the interlayer insulating film 12 are sequentially formed to obtain a semiconductor device as shown in FIG.

As described above, in this embodiment, the cap nitride film 5 is formed so as to project from the side surface of the gate electrode 4, and the sidewall oxide film 7 fills the void under the cap nitride film 5. Since it is formed, the gate electrode 4 and the polycrystalline silicon wiring 9 can be separated by a sufficient distance to prevent a short circuit between them. Therefore, it is possible to reliably prevent a short circuit between the gate electrode 4 and the polycrystalline silicon wiring 9. Further, since it is not necessary to increase the film thickness of the cap nitride film 5 in order to prevent a short circuit between the gate electrode 4 and the polycrystalline silicon wiring 9, it is possible to reduce the step difference on the surface of the silicon substrate 1, so that the polycrystalline film is formed. The step coverage of the silicon wiring 9 is improved, and the polycrystalline silicon wiring 9 and the source / drain 8 are reliably connected.

Further, since the side wall oxide film 7 is formed by anisotropic etching using the cap nitride film 5 as an etching stopper, the silicon oxide film 17 is not over-etched, and the side-etched portion of the gate electrode 4 is not etched. Further, the sidewall oxide film 7 can be surely left. Therefore, the semiconductor device can be manufactured easily and in a small number of steps.

Although the present invention has been described with reference to the embodiments, the present invention is not limited to the above-mentioned embodiments, and various design changes can be made to materials, numerical values and the like. For example, instead of the polycrystalline silicon wiring 9, a wiring made of a metal such as aluminum or an alloy thereof, a silicide or a polycide wiring can be used. Also, the silicon substrate 1
May be an SOI substrate or a gallium arsenide substrate. Furthermore, the present invention can be applied not only to MOS transistors but also to field shield element isolation structures.

Further, similarly to the conventional example shown in FIG. 5, after the step shown in FIG. 2C, an interlayer insulating film is formed on the entire surface,
After the contact hole reaching the source / drain 8 is opened, the step of FIG.
May be formed into a film.

[0033]

According to the semiconductor device of the present invention, the gate electrode and the wiring layer can be sufficiently separated by the sidewall insulating film, so that they are not short-circuited. Further, since the film thickness of the cap insulating film can be reduced to reduce the step difference on the substrate surface, the step coverage of the wiring layer is good and the connection failure between the wiring layer and the impurity diffusion layer does not occur. Therefore, a highly reliable semiconductor device can be obtained. Further, according to the method of manufacturing a semiconductor device of the present invention, the semiconductor device can be manufactured easily and in a small number of steps.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

FIG. 3 is a cross-sectional view showing the method of manufacturing the semiconductor device of the embodiment of the present invention in the order of steps.

FIG. 4 is a cross-sectional view showing the method of manufacturing the semiconductor device of the embodiment of the present invention in the order of steps.

FIG. 5 is a cross-sectional view showing a method of manufacturing a conventional semiconductor device in the order of steps.

[Explanation of symbols]

 1 Silicon Substrate 2 Field Oxide Film 3 Gate Oxide Film 4 Gate Electrode 5 Cap Nitride Film 6 Photoresist 7 Sidewall Oxide Film 8 Source / Drain 9 Polycrystalline Silicon Wiring 10, 12 Interlayer Insulation Film 11 Aluminum Wiring

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/90 J

Claims (3)

[Claims] 1. A gate electrode formed on a semiconductor substrate via a gate insulating film, an impurity diffusion layer formed on a surface of the semiconductor substrate, and a wiring layer connected to the impurity diffusion layer. In the semiconductor device, a cap insulating film is formed on the gate electrode so as to protrude from a side surface of the gate electrode, and the cap insulating film and the sidewall of the gate electrode that separate the gate electrode and the wiring layer from each other. The insulation film
A semiconductor device, wherein the semiconductor device is formed so as to fill a void below the protruding portion of the cap insulating film. 2. The semiconductor device according to claim 1, wherein the cap insulating film is a silicon nitride film, and the sidewall insulating film is a silicon oxide film. 3. A step of sequentially forming a first insulating film, a first conductive film, and a second insulating film on a semiconductor substrate; and anisotropy of the second insulating film and the first conductive film. A step of selectively removing by etching to form a cap insulating film and a gate electrode respectively; and a step of isotropically etching the gate electrode using the cap insulating film as a mask to side-etch the gate electrode. And a step of forming a third insulating film made of a material different from that of the cap insulating film over the entire surface so as to fill the side-etched portion of the gate electrode, and ion implantation is performed using the cap insulating film as a mask. Thereby forming an impurity diffusion layer on the surface of the semiconductor substrate, and using the cap insulating film as an etching stopper to form the third insulating film. A step of exposing the impurity diffusion layer and forming a sidewall insulation film on the side surfaces of the cap insulating film and the gate electrode by means of isotropic etching; and a step of forming a wiring layer connected to the impurity diffusion layer. And a method for manufacturing a semiconductor device.