JP2907112B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device.
Method , especially the source / drain of MOS transistor
The present invention relates to a method for forming an electrode .

[0002]

2. Description of the Related Art A conventional method for manufacturing a MOS transistor (Tr) will be described with reference to FIG.

First, P-type and N-type impurities are introduced on a silicon substrate 1 to form a P-well 3a and an N-well 3b, and then a field oxide film 2 is formed by a selective oxidation method.
Next, after the gate oxide film 4 and the gate electrode 5 made of polysilicon are formed, N-type impurities are ion-implanted, for example, to form an N ^- region 6a in the P well 3a. Next, after forming an oxide film on the entire surface, anisotropic etching is performed to form sidewalls 8 on the side surfaces of the gate electrode 5. Next is N again
Type impurities are ion-implanted to form an N ⁺ region 6b, which is used as a source / drain having a lightly doped drain (LDD) structure.

Next, a polysilicon film is grown and then patterned to form a polysilicon electrode 9A connected to the source / drain. Next, a BPSG film 10A is grown as an insulating film on the entire surface, and is flattened by applying a photoresist, etching back by dry etching, or the like. Next, after forming a contact hole on the polysilicon electrode 9A,
A film 14A is grown, etched back and buried. Then A
1 is sputtered and patterned to form a metal electrode 11A connected to the W film 14A.

In the above conventional example, since a polysilicon film is grown on a surface having a step due to the gate electrode 5, patterning is performed. Therefore, the gate electrode 5 and the polysilicon electrode 9A for extracting the source / drain are formed due to misalignment during patterning. Are patterned at intervals of about 0.5 μm from the sidewalls 8 on the side surfaces of the gate electrode 5 so as not to cause a short circuit and to reduce a step due to the polysilicon electrode 9A.

[0006]

In the conventional method of forming a source / drain lead electrode by patterning a polysilicon film, the distance between the gate electrode and the source / drain lead electrode is 0.6 to 0.7 μm. Therefore, there is a problem that miniaturization of the transistor is hindered.

In order to improve the coverage of the metal electrode 11A, when the contact hole is buried with a W film or the like,
After forming the contact hole, a W film is grown, and the W film other than the inside of the contact hole is removed by dry etching. In this case, the steps between the gate electrode 5 and the source / drain extraction electrodes must be flattened in order to prevent the W film from being left unetched. For this reason, there is a problem that the process is complicated and the reliability and the manufacturing yield of the semiconductor device are reduced.

An object of the present invention allows the miniaturization of semiconductor devices, yet with improved reliability and manufacturing yield semiconductors
An object of the present invention is to provide a method for manufacturing a body device .

[0009]

[0010]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a field oxide film for separating an element region on a semiconductor substrate; and forming a gate electrode on the element region via a gate oxide film. Forming an impurity region using the gate electrode as a mask to form an impurity region serving as a source / drain on the substrate surface, and forming a first insulating film on the entire surface including the surface of the impurity region. Forming a sidewall made of a first insulating film on the side surface of the gate electrode by anisotropic etching, and exposing the surface of the gate electrode after forming a polysilicon film on the entire surface including the surface of the sidewall; Polishing and flattening the substrate, performing a heat treatment after ion-implanting impurities into the polysilicon film on the impurity region, After forming the grooves the polysilicon film on the monolayer is selectively removed and is characterized in that it comprises a step of filling the second insulating film is formed the groove on the whole surface.

A method of manufacturing a semiconductor device according to a second aspect of the present invention includes a step of forming a field oxide film for separating an element region on a semiconductor substrate, and then forming a gate electrode in the element region via a gate oxide film; Using the gate electrode as a mask to introduce an impurity to form an impurity region serving as a source / drain on the surface of the substrate; forming a first insulating film on the entire surface including the surface of the impurity region; Forming a sidewall made of a first insulating film on a side surface of the gate electrode; and ion-implanting an impurity into the impurity region using the sidewall and the gate electrode as a mask to form an impurity region having an LDD structure. Forming a barrier metal film and a refractory metal film sequentially on the entire surface including the surface of the impurity region, and polishing the surface until the surface of the gate electrode is exposed. After the step of planarizing and selectively removing the high melting point metal film and the barrier metal film on the field oxide film to form a groove, a second insulating film is formed on the entire surface to form the groove. And a filling step.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIGS. 1A to 1D are cross-sectional views of a semiconductor chip for explaining a first embodiment of the present invention.

First, as shown in FIG. 1A, a P-type (P, As) and an N-type impurity (B) are introduced into a silicon substrate 1, and a P well 3a is formed in an N-channel transistor (Tr) region.
To form an N well 3b in the P channel Tr region. Next, after the field oxide film 2 is formed by the selective oxidation method, the gate oxide film 4 is formed. Next, after forming a polysilicon film (or a polysilicon film and a silicide film of a refractory metal) into which the impurity is introduced, the gate electrode 5 is formed by patterning. Next, the N-channel Tr region is covered with a photoresist film, and a P-type impurity is ion-implanted into the P-channel Tr region to form a P ⁻ region 7 a having a low impurity concentration. Similarly, an N-type impurity is ion-implanted to form an N ⁻ region 6a in the N channel Tr region.

Next, as shown in FIG. 1B, an oxide film (or a nitride film) is formed to a thickness of about 0.1 μm on the entire surface, and then anisotropically etched, and a side surface of the gate electrode 5 is formed. The wall 8 is formed. Next, a polysilicon film 9 is formed on the entire surface.
And fill the space between the gate electrodes.

Next, as shown in FIG. 1C, the polysilicon film 8 is polished and flattened until the surface of the gate electrode 5 is exposed. Next, the region other than the source / drain extraction electrode formation region of the N-channel Tr region is masked with a photoresist film,
N-type impurities are ion-implanted. Subsequently, similarly, a region other than the source / drain extraction electrode formation region in the P channel region is masked with a photoresist film, and P-type impurities are ion-implanted. Next, N ⁺ regions 6b and P ⁺ regions 7b with a high impurity concentration are formed by injecting impurities by heat treatment to form LDD.
The source / drain of the structure is formed.

Next, after the polysilicon film 9 in the electrode isolation region on the field oxide film 2 is selectively removed to form a groove, a silicon oxide film 10 is formed to a thickness of about 0.5 μm on the entire surface by CVD or the like. And fill this groove. Next, the silicon oxide film 10 is polished until the surfaces of the gate electrode 5 and the polysilicon film 9 are exposed, so that the source / drain extraction polysilicon isolated from the silicon oxide film 10 and the side walls 8 is separated. The electrode 9a is completed.

As shown in FIG. 1D, an Al (or a barrier metal such as TiN and a metal such as Al) film is formed by a sputtering method and then patterned to form a gate electrode 5.
Then, the metal electrode 11 is formed on the polysilicon electrode 9a.

As described above, according to the first embodiment, since the gate electrode 5 and the polysilicon electrode 9a as the source / drain lead-out electrode are adjacent to each other via the side wall 8, the MOS transistor can be miniaturized. Can be For example, while the distance between the gate electrode 5 and the polysilicon electrode 9A in the conventional example described with reference to FIG. 3 is 0.6 μm, in the first embodiment, the gate electrode 5 and the polysilicon electrode 9a are Can be reduced to 0.1 μm, which is the thickness of the side wall 8.

Further, since the surfaces of the gate electrode and the polysilicon electrode are exposed without covering the surfaces of the gate electrode and the polysilicon electrode with an insulating film as in the conventional example, the formation of the metal electrode 11 is easy. In addition, complicated steps such as forming a contact hole and filling the inside of the contact hole with a W film or the like are not required, so that the reliability and manufacturing yield of the semiconductor device can be improved.

FIGS. 2A to 2C are sectional views of a semiconductor chip for explaining a second embodiment of the present invention.

First, as shown in FIG.
After a P-well 3a and an N-well 3b are formed in the silicon substrate 1 by the same operation as in (a) and (b), the field oxide film 2, the gate oxide film 4, the gate electrode 5, and the N ⁻ region 6a are formed on the substrate surface. , P ^- region 7a. Next, P
Masking the channel Tr region with a photoresist film 12;
N-type impurities (B) are ion-implanted to form an N ⁺ region 6b.

Next, as shown in FIG. 2B, after removing the photoresist film 12, the N-channel Tr region is covered with a photoresist film, and P-type impurities (P, As) are ion-implanted to form P ⁺ The region 7b is formed. Next, after removing the photoresist film used as the mask, a laminated film 13 of Ti—TiN is formed as a barrier metal film to a thickness of about 0.1 μm on the entire surface by a sputtering method. Next, this Ti-
On the TiN film 13, W having a thickness of about 0.5 μm is formed by CVD.
A film 14 is formed to fill the space between the gate electrodes.

Next, as shown in FIG. 2C, the W film 14 and the Ti--TiN film 13 are polished and flattened until the surface of the gate electrode 5 is exposed. Next, after selectively etching the W film 14 and the Ti-TiN film 13 in the electrode isolation region on the field oxide film 2 to form a groove, a silicon oxide film 10A is formed to a thickness of about 0.5 μm over the entire surface by a CVD method or the like. It is formed to a thickness to fill this groove. Next, the silicon oxide film 10A is polished until the surfaces of the gate electrode 5 and the W film 14 and the like are exposed, so that the source / drain extraction W electrode isolated by the silicon oxide film 10A and the sidewall 8 is separated. 14a is completed. Hereinafter, the metal electrode 11 made of Al or the like is formed on the gate electrode 5 and the W electrode 14a.

In the second embodiment, as in the first embodiment, the source / drain lead electrode W
Since the width of the electrode 14a can be reduced, the MOS transistor can be miniaturized. Further, in the second embodiment, since the source / drain lead electrodes are formed of the W film, there is an advantage that the resistance of the electrodes can be reduced as compared with the first embodiment using the polysilicon film.

In each of the above embodiments, the CMOS
Although the transistor has been described, the present invention is not limited to this, and an N-channel MOS transistor or a P-channel MOS transistor alone may be used. Also, the case where W is used as the high melting point metal has been described,
Mo or Ti can be used.

[0026]

As described above, according to the present invention, since the gate electrode and the source / drain extraction electrode are adjacent to each other via the side wall made of a thin insulating film on the side surface of the gate electrode, the electrode interval is reduced, and the MOS transistor There is an effect that miniaturization is achieved and high integration is possible. Further, when the source / drain extraction electrodes are formed of a high melting point metal such as tungsten, the resistance of the electrode portion of the element can be reduced, so that the speed of the element can be increased.

Further, in the present invention, since the metal electrode is formed immediately above the gate electrode and the source / drain electrodes,
Since it does not include complicated processes such as forming a contact hole and embedding tungsten in the hole as in the past, abnormal etching of the contact hole, poor coverage of the upper aluminum electrode due to abnormal shape of the tungsten buried in the hole, etc. There is also an effect that a semiconductor device which can avoid defects and has improved reliability and yield can be obtained.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor chip for explaining a first embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor chip for explaining a second embodiment of the present invention.

FIG. 3 is a cross-sectional view of a semiconductor chip for describing a conventional semiconductor device.

[Explanation of symbols]

Reference Signs List 1 silicon substrate 2 field oxide film 3a P well 3b N well 4 gate oxide film 5 gate electrode 6a N ⁻ region 6b N ⁺ region 7a P ⁻ region 7b P ⁺ region 8 sidewall 9 polysilicon film 9a, 9A polysilicon electrode 10 , 10A silicon oxide film 10a BPSG film 11, 11A metal electrode 12 photoresist film 13 Ti-TiN film 14, 14A W film 14a W electrode

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/8238 H01L 21/283 H01L 21/3205 H01L 27/092

Claims (2)

(57) [Claims] 1. A step of forming a field oxide film for isolating an element region on a semiconductor substrate, forming a gate electrode in the element region via a gate oxide film, and introducing impurities using the gate electrode as a mask. Forming an impurity region serving as a source / drain on the surface of the substrate; forming a first insulating film on the entire surface including the surface of the impurity region; and performing anisotropic etching to form a first insulating film on the side surface of the gate electrode. Forming a sidewall made of a film, forming a polysilicon film on the entire surface including the surface of the sidewall, and polishing and flattening until a surface of the gate electrode is exposed; Performing a heat treatment after ion-implanting impurities into the polysilicon film; and selectively removing the polysilicon film on the field oxide film to form a groove. Forming a second insulating film over the entire surface and filling the trench. 2. A step of forming a field oxide film for isolating an element region on a semiconductor substrate, forming a gate electrode in the element region via a gate oxide film, and introducing impurities using the gate electrode as a mask. Forming an impurity region serving as a source / drain on the surface of the substrate; forming a first insulating film on the entire surface including the surface of the impurity region; and performing anisotropic etching to form a first insulating film on a side surface of the gate electrode. A step of forming a sidewall made of a film, a step of ion-implanting an impurity into the impurity region using the sidewall and the gate electrode as a mask to form an impurity region of an LDD structure, and an entire surface including a surface of the impurity region. Forming a barrier metal film and a refractory metal film sequentially, and polishing and flattening until a surface of the gate electrode is exposed; After selectively removing the refractory metal film and the barrier metal film on the oxide film to form a groove,
Forming a second insulating film on the entire surface and filling the trench.