JPH1117129A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize higher integration and higher performance of a logic hybrid DRAM. SOLUTION: After a gate electrode FG1n of an n-channel MISFET Qn and a gate electrode FG1 P of a p-channel MISFET Qp of a logic part are formed, a silicide layer 14 is formed on the surfaces of source regions and drain regions of the n-channel MISFET Qn and the p-channel MISFET Qp of the logic part. Then, after a gate electrode FG2n of a memory cell selection MISFET of a DRAM part memory cell is formed, first contact holes 20 extended to a source region and a drain region of the memory cell selection MISFET of the DRAM part memory cell are formed. Then, a silicide layer 21 is formed on the surfaces of the source region and the drain region of the memory cell selection MISFET exposed at the bottoms of the first contact holes 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for manufacturing a semiconductor integrated circuit device, and more particularly, to a logic (logic circuit) and a D (logic circuit).
The present invention relates to a technology effective when applied to a highly integrated semiconductor integrated circuit device in which a RAM (Dynamic Random Access Memory) or an electrically rewritable nonvolatile memory is mounted.

[0002]

2. Description of the Related Art In recent years, there has been an increasing demand for an image similar to a natural image using computer graphics. However, in order to realize a natural image, the data transfer speed of the DRAM used as the main storage device is set to the current 135M.
It is necessary to increase the data rate from 100 bytes / second to 100 GB / second or more, which is difficult to achieve with a single DRAM.

In order to improve the performance, a DRAM and a logic are mixed in one semiconductor chip to form one system, and the data transmission time is reduced by shortening the bus signal propagation time and avoiding the propagation delay. Methods for increasing the transfer speed have been proposed.

Incidentally, a semiconductor integrated circuit device in which a DRAM and a logic are mixed (hereinafter referred to as a logic embedded DRAM)
Are described in, for example, "Nikkei Micro Device", published March 31, 1996, Nikkei McGraw-Hill, p.
5.

[0005]

The inventor of the present invention has found the following problems in developing the logic-embedded DRAM.

That is, in the memory cell of the DRAM section, it is important how to form an information storage capacitor capable of holding stored charge for a long time with a small memory cell area. On the other hand, in the logic section, the MISFE
T (Field Insulator Semiconductor Field Effect Tra
The current drive capability of the MISFET is improved by reducing the threshold voltage by shortening the gate electrode length (gate length) of the nsistor). It is important to operate the circuit. Therefore, in the logic section and the DRAM section memory cell, the integration degree of the MISFET, the gate length of the MISFET,
The thickness of the gate insulating film provided between the gate electrode of the MISFET and the semiconductor substrate differs.

However, the MI of the memory cell of the DRAM section in which the long and repeated pattern is densely laid out.
The gate electrode of the SFET and the MISF of the logic part that is a short, relatively low-density pattern or an isolated pattern
It is difficult with the current optical photolithography technology to simultaneously resolve the gate electrodes of the ET so as to have the minimum size in the photolithography process. If an electron beam lithography apparatus is used, the MIS of the DRAM memory cell
Although it is possible to form a gate electrode having a gate length suitable for the FET and a gate electrode having a gate length suitable for the MISFET in the logic portion, there is a problem in throughput or cost.

In the logic section, the source and drain regions of the MISFET need to be silicided in order to increase the current driving capability of the MISFET. On the other hand, in the memory cell of the DRAM section, the MISFE is used in order to suppress the short channel effect and ease the drain electric field.
Since the impurity concentration of the source region and the drain region of T is made low, the junction of the source region and the drain region of the MISFET is shallow, and the leakage current may increase due to silicidation. For this reason, it is difficult to silicide the source region and the drain region of the MISFET of the DRAM memory cell.

An object of the present invention is to provide a technology capable of realizing high integration and high performance of a logic embedded DRAM.

Another object of the present invention is to provide a logic embedded DRA.
An object of the present invention is to provide a technology capable of realizing high reliability of M.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the method of manufacturing a semiconductor integrated circuit device according to the present invention is directed to a method of manufacturing a logic integrated circuit of a logic embedded DRAM.
A method of manufacturing an SFET and a memory cell selection MISFET of a DRAM memory cell, comprising first forming a gate electrode of a MISFET of a logic part, and then forming a source region and a drain region of the MISFET of the logic part;
Next, a silicide layer for reducing parasitic resistance is formed on the surfaces of the source region and the drain region of the MISFET in the logic section. Next, after forming the gate electrode of the memory cell selecting MISFET of the DRAM section memory cell,
The source region and the drain region of the memory cell selection MISFET of the AM memory cell are formed, and then the DRA
A first contact hole is formed to reach the source region and the drain region of the memory cell selection MISFET of the M part memory cell. Next, the memory cell selecting MISF of the DRAM memory cell exposed at the bottom of the first contact hole.
After a silicide layer for reducing contact resistance is formed on the surface of the source region and the drain region of the ET, a conductive film is buried in the first contact hole provided in the DRAM memory cell.

According to the above means, the logic unit MI
By forming the gate electrode of the SFET and the gate electrode of the MISFET for selecting the memory cell of the DRAM part memory cell in different manufacturing steps, the MISFET of the logic part or the MISFET for selecting the memory cell of the DRAM part memory cell is formed.
The processing of the gate electrode conforming to the characteristics of each layout of the ET becomes possible, and the dimensional accuracy can be improved. Therefore,
In the logic section, since the variation in the operating characteristics of the MISFET can be reduced, the variation in the threshold voltage can be reduced, the current driving capability can be improved, and the offset current can be reduced.
More room for circuit design. In the DRAM memory cell, the memory cell can be miniaturized.

Further, the current drive capability of the MISFET can be improved by forming a silicide layer on the surface of the source and drain regions of the MISFET in the logic section to reduce the parasitic resistance of the source and drain regions. Also, the memory cell selection M
By forming a silicide layer on the surface of the source region and the drain region of the ISFET, the contact resistance between the conductive film embedded in the first contact hole and the source region and the drain region of the MISFET for selecting a memory cell can be reduced. . Further, a silicide layer formed on the surface of the source region and the drain region of the MISFET in the logic portion;
MISFET for memory cell selection of DRAM section memory cell
By forming the silicide layers formed on the surfaces of the source region and the drain region in different manufacturing steps, DR
It is possible to form a thin silicide layer in consideration of the junction depth of the source and drain regions of the memory cell selection MISFET of the AM memory cell, and to form the source region of the memory cell selection MISFET by forming the silicide layer,
Junction breakdown of the drain region can be prevented.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and their repeated description will be omitted.

The logic part in the logic-embedded DRAM is a CMOS (Complementary Metal Oxide Semicon).
Since the semiconductor substrate of the peripheral circuit of the logic part and the DRAM part has almost the same cross-sectional structure,
In the present embodiment, description of the peripheral circuits of the DRAM section is omitted. In the present embodiment, steps up to formation of a bit line of a memory cell in a DRAM unit and a first-layer metal wiring of a logic unit in the same layer will be described with reference to the drawings.

In the figure, Qn is an n-channel type MISFET in the logic section, and Qp is a p-channel type MISFET in the logic section.
ISFET.

(Embodiment 1) An n-channel MISFET Qn and a p-channel MISFE of a logic portion in a logic-embedded DRAM according to an embodiment of the present invention.
A method of manufacturing TQp and a MISFET for selecting a memory cell of a DRAM memory cell will be described with reference to cross-sectional views of main parts of a semiconductor substrate shown in FIGS.

First, as shown in FIG. 1, p ^- type silicon single crystal is formed on a main surface of a semiconductor substrate 1 by a known method.
A type well 2, an n-type well 3, a field insulating film 4, and a gate insulating film 5 are sequentially formed. Field insulating film 4
Means, for example, LOCOS (Local Oxidation of Silicon)
The isolation or the buried shallow trench isolation is configured, and the thickness of the gate insulating film 5 of the memory cell in the DRAM section is, for example, about 7 nm, and the thickness of the gate insulating film 5 in the logic section is, for example, about 4 nm. It is.

Next, after a polycrystalline silicon film 6 into which phosphorus (P) is introduced and a silicon nitride film 7 are sequentially deposited on the semiconductor substrate 1, a photoresist 8 is applied on the semiconductor substrate 1 and then a pattern 8 is formed. The photoresist 8 is patterned by performing exposure using an edge emphasizing type mask which has a short length and is excellent in resolving a low-density line pattern. When the area of the logic portion is small, the photoresist 8 may be patterned by electron beam lithography. Thereafter, the silicon nitride film 7 in the logic area is etched using the patterned photoresist 8 as a mask.

Next, as shown in FIG. 2, after the photoresist 8 is removed, the polycrystalline silicon film 6 is etched using the silicon nitride film 7 as a mask, and the gate electrode FG _1n of the n-channel MISFET Qn in the logic part is formed. And a gate electrode FG _1p of the p-channel type MISFET Qp is formed.

Next, using a photoresist (not shown) and a laminated film composed of the silicon nitride film 7 and the polycrystalline silicon film 6 as a mask, a low concentration n-type impurity, for example, P is ion-implanted, and the low-concentration n ⁻ -type semiconductor region 9 constituting a part of the source region and the drain region of the n-channel type MISFET Qn is
G _1n is formed by self-alignment.

Similarly, a p-type impurity, for example, boron fluoride (BF2) is ion-implanted into the n-type well 3 of the logic portion, and a low-concentration p-type impurity forming a part of the source region and the drain region of the p-channel MISFET Qp. ^- -type semiconductor region 1
0 is formed in self-alignment with the gate electrode _FG1p .

Next, as shown in FIG. 3, the silicon nitride film deposited on the semiconductor substrate 1 is subjected to RIE (Reactive Ion E
The sidewall spacers 11 are formed on the side walls of the gate electrodes FG _1n and FG _{1p in} the logic portion by processing by anisotropic etching such as a tching method. afterwards,
High-concentration n-type impurities, for example, arsenic (As) are ion-implanted into the p-type well 2 of the logic portion to form an n-channel type MISF.
A high-concentration n ⁺ -type semiconductor region 12 constituting another part of the source region and the drain region of the ETQn is formed. That is, the source region and the drain region of the n-channel MISFET Qn have an LDD (Lightly Doped Drain) structure.

Similarly, a high-concentration p-type impurity, for example, BF2 is ion-implanted into the n-type well 3 of the logic portion, and a high-concentration p-type impurity that forms another part of the source region and the drain region of the p-channel MISFET Qp. ^{The +} type semiconductor region 13 is formed. That is, the source region and the drain region of the p-channel type MISFET Qp have an LDD structure.

Next, as shown in FIG. 4, a metal film (not shown), for example, a titanium film, a cobalt film or the like is formed on the semiconductor substrate 1 by sputtering or CVD (Chemical Vapor Depth).
osition) method, and thereafter, the semiconductor substrate 1 is subjected to a heat treatment, whereby the surface of the n ⁺ -type semiconductor region 12 of the n-channel MISFET Qn of the logic portion and the p ⁺ -type semiconductor region 13 of the p-channel MISFET Qp
A silicide layer 14 for reducing the parasitic resistance of the source region and the drain region. Next, after removing the unreacted metal film by washing or the like, a thin silicon nitride film 15 is deposited on the semiconductor substrate 1.

Next, as shown in FIG. 5, a photoresist 16 is applied on the semiconductor substrate 1 and then exposed using a Levenson-type mask which is excellent in resolving a line and space pattern having a long facing length. With this, the photoresist 16 is patterned. Thereafter, DR is performed using the patterned photoresist 16 as a mask.
The silicon nitride film 15 and the silicon nitride film 7 of the AM memory cell are sequentially etched.

Next, as shown in FIG. 6, after the photoresist 16 is removed, the polycrystalline silicon film 6 is etched using the silicon nitride film 15 and the silicon nitride film 7 as a mask, and the memory cell of the DRAM section memory cell is removed. MIS for selection
The gate electrode FG _{2n of the} FET is formed.

Next, a photoresist (not shown) and a laminated film including the silicon nitride film 15, the silicon nitride film 7, and the polycrystalline silicon film 6 are used as masks to lower the p-type well 2 of the DRAM memory cell. An n-type impurity having a high concentration, for example, P is ion-implanted to form a low-concentration n ⁻ -type semiconductor region 17 constituting a source region and a drain region of the MISFET for memory cell selection by self-alignment with the gate electrode FG _2n . .

Next, as shown in FIG. 7, after a silicon nitride film 18 is deposited on the semiconductor substrate 1, as shown in FIG.
For example, TEOS (Tetra Ethyl Ortho Silicate; Si
(OC ₂ H ₅ ) ₄ ) A silicon oxide film 19 having a planarized surface is formed on the semiconductor substrate 1 by a plasma CVD method using a gas as a raw material.

Next, as shown in FIG. 9, using the patterned photoresist (not shown) as a mask, the silicon oxide film 19 is first etched to obtain n ^{− of the} MISFET for selecting the memory cell of the DRAM memory cell. After forming the upper portion of the first contact hole 20 reaching the mold semiconductor region 17, the silicon nitride film 18 is subsequently etched to form the lower portion of the first contact hole 20.

At this time, the gate electrode FG _2n of the memory cell selecting MISFET is covered with a cap composed of the silicon nitride film 15 and the silicon nitride film 7 and a spacer composed of the silicon nitride film 18. Since the surface of the field insulating film 4 which is an element isolation region is also covered with the silicon nitride film 18,
The first contact hole 20 has a memory cell selecting MI.
It can be formed in self-alignment with the gate electrode FG _{2n of the} SFET and the element isolation region.

The silicon oxide film 19 is formed, for example, on the narrow electrode R
Etching is performed using the C ₄ F ₈ + CO ₂ gas system in the IE apparatus. When this etching method is used, the etching of the silicon oxide film 19 is almost stopped at the silicon nitride film 18 due to a difference in etching selectivity. Also, the silicon nitride film 18
Isotropic etching using a CHF ₃ + O ₂ gas system in a down flow type low damage ashing apparatus, or CHF ₃ + O in a narrow electrode RIE etching apparatus.
Etching is performed by anisotropic etching using a _two- gas system.

Next, as shown in FIG.
A metal film (not shown), for example, a titanium film, a cobalt film or the like is deposited thereon by a sputtering method or a CVD method,
Thereafter, by subjecting the semiconductor substrate 1 to a heat treatment, D
A silicide layer 21 for reducing contact resistance is formed on the exposed surface of the n ⁻ -type semiconductor region 17 of the MISFET for selecting a memory cell of the RAM section memory cell. Next, the unreacted metal film is removed by washing or the like. The silicide layer 21 provided in the memory cell of the DRAM section is not formed to be thicker than the junction depth of the n ⁻ type semiconductor region 17 of the MISFET for selecting a memory cell, and is smaller than the silicide layer 14 provided in the logic section. It is formed thin.

Next, as shown in FIG.
A polycrystalline silicon film or a laminated film of a sputtered tungsten film and a CVD tungsten film,
After depositing a conductive film (not shown) such as a laminated film of an iN film and a CVD tungsten film, a CMP (Chemical Mechani
The conductive film is buried in the first contact hole 20 by planarizing the surface of the conductive film by a cal polishing (chemical mechanical polishing) method or an etch-back method, thereby forming a buried wiring 22.

Next, as shown in FIG. 12, after depositing a silicon oxide film 23 on the semiconductor substrate 1, as shown in FIG. 13, the silicon oxide film 23 in the region where the bit line of the DRAM memory cell is formed is removed. Remove.

Next, as shown in FIG. 14, using the patterned photoresist 24 as a mask, first, the silicon oxide film 23 and the silicon oxide film 19 are sequentially etched to obtain n ⁺ of the n-channel MISFET of the logic portion.
Layer 14 formed on the surface of type semiconductor region 12
And p ⁺ type semiconductor region 1 of p channel type MISFET
The upper part of the second contact hole 25 reaching the silicide layer 14 formed on the surface of No. 3 is formed. Subsequently, FIG.
As shown in FIG. 5, the silicon nitride film 18 and the silicon nitride film 15 are sequentially etched to form a lower portion of the second contact hole 25.

At this time, the n-channel MIS of the logic section
Gate electrode FG _1n of FET Qn and p-channel type MI
The gate electrode FG _{1p of the} SFET Qp is a silicon nitride film 1
8, the silicon nitride film 15, the silicon nitride film 7, and the side wall spacer 11 composed of the silicon nitride film. The surface of the field insulating film 4 which is an element isolation region is also covered with the silicon nitride film 18 and the silicon nitride film. Since the second contact hole 25 is covered with the film 15, the n-channel type M
Gate electrode FG _{1n of} ISFET Qn, p-channel type MI
It can be formed in self-alignment with the gate electrode FG _1p and the isolation regions of SFETQp.

The silicon oxide film 23 and the silicon oxide film 19 are formed by, for example, C ₄ F ₈ + CO ₂ using a narrow electrode RIE apparatus.
Etching is sequentially performed using a gas system. When this etching method is used, the etching of the silicon oxide film 19 is almost stopped at the silicon nitride film 18 due to a difference in etching selectivity. The silicon nitride film 18 and the silicon nitride film 1
Reference numeral 5 denotes, for example, isotropic etching using a CHF ₃ + O ₂ gas system in a down flow type low damage ashing apparatus, or CHF ₃ + in a narrow electrode RIE etching apparatus.
Etching is performed by anisotropic etching using an O ₂ gas system.

Next, as shown in FIG.
A titanium nitride film (or tungsten film) 26 is deposited thereon by a sputtering method, and then a tungsten film 27 is deposited by a CVD method. Then, as shown in FIG. 17, a patterned photoresist (not shown) is used as a mask. The tungsten film 27 and the titanium nitride film 26 are sequentially etched to form a bit line BL including the tungsten film 27 and the titanium nitride film 26 in the DRAM memory cell, and the tungsten film 27 and the titanium nitride film 26 in the logic portion. The first composed by
To form a metal wiring M ₁ of the layer first.

Thereafter, an information storage capacitive element is formed in the DRAM memory cell, and a metal wiring for connecting the DRAM memory cell to a peripheral circuit, a metal wiring for connecting a random logic circuit in the logic part, and the like are formed. The semiconductor substrate 1 is covered with a passivation film to complete the logic embedded DRAM of the first embodiment.

[0044] Thus, according to the first embodiment, the gate electrode FG _1p gate electrode FG _1n and p-channel type MISFETQp the n-channel type MISFETQn logic unit, MISFET for memory cell selection DRAM section memory cell _Are formed in different manufacturing steps, respectively, so that the n-channel MISFET Qn and the p-channel MISFET Q
p or M for selecting a memory cell of a DRAM section memory cell
The processing of the gate electrode conforming to the characteristics of each layout of the ISFET becomes possible, and the dimensional accuracy can be improved. Therefore, in the logic portion, since the variation in the operating characteristics of the MISFET can be reduced, the variation in the threshold voltage, the improvement in the current driving capability, and the reduction in the offset current can be realized, and the margin of circuit design is expanded. In the DRAM memory cell, the memory cell can be miniaturized.

The n-channel type MISF of the logic section
A silicide layer 1 is formed on the surface of each of the source region and the drain region of the ETQn and the p-channel type MISFET Qp.
By forming 4 to reduce the parasitic resistance of the source region and the drain region, the current drive capability of the n-channel MISFET Qn and the p-channel MISFET Qp can be improved. Further, a silicide layer 21 is formed on the surfaces of the source and drain regions of the memory cell selecting MISFET of the DRAM memory cell, and the embedded wiring 22 embedded in the first contact hole 20 and the memory cell selecting MISFET are formed. The contact resistance with the source region and the drain region can be reduced.

Further, the n-channel MIS of the logic section
A silicide layer 14 formed on the surface of the source region and drain region of each of the FET Qn and the p-channel MISFET Qp, and a silicide layer 21 formed on the surface of the source region and the drain region of the memory cell selection MISFET of the DRAM memory cell. Are formed in different manufacturing steps, thereby forming a thin silicide layer 21 on the surface of the source region and the drain region of the memory cell selecting MISFET of the DRAM cell memory cell in consideration of the junction depth of the source region and the drain region. It is possible to do. As a result, it is possible to prevent junction destruction of the source region and the drain region of the memory cell selection MISFET of the DRAM section memory cell.

The first contact hole 20 provided in the memory cell of the DRAM section and the second contact hole 25 provided in the logic section are self-aligned contacts. Therefore, in any layout, the first contact hole 20 and the second contact hole 25 are formed in the n-channel MISFET Q
n-gate electrode FG _1n and p-channel MISFET
The gate electrode FG _{1p of} Qp and the gate electrode FG _{2n of the} MISFET for selecting a memory cell of the memory cell of the DRAM section
Can be formed in a self-aligned manner, so that the layout margin can be improved.

Further, by forming the embedded wiring 22 provided in the memory cell of the DRAM section from a metal film such as a tungsten film, the series resistance of the embedded wiring 22 can be reduced, and the speed of the memory operation can be increased. it can.

[0049] In the first embodiment, the gate electrode FG _1p gate electrode FG _1n and p-channel type MISFET of the n-channel type MISFETQn logic unit, and MIS for memory cell selection DRAM section memory cell
Polycide gate electrode FG _2n of the FET is constituted by a polycrystalline silicon film, comprising a laminated film of a metal silicide film (e.g., molybdenum silicide (MoSi) film, a tungsten silicide (WSi ₂₎ film) and the polysilicon film A gate electrode or a metal film (for example, a stacked film of a tungsten (W) film, a stacked film of a tungsten (W) film and a tungsten nitride (WN) film, a stacked film of a tungsten (W) film and a titanium nitride (TiN) film), and A polymetal gate electrode made of a laminated film with a crystalline silicon film may be used.

(Embodiment 2) An n-channel MISFET Qn and a p-channel MISF of a logic section in a logic embedded DRAM according to another embodiment of the present invention.
The method of manufacturing the ETQp and the DRAM memory cell will be described with reference to the cross-sectional views of the main parts of the semiconductor substrate shown in FIGS.

First, according to the first embodiment,
Similarly to the manufacturing method described with reference to FIG. 3, a p-type well 2, an n-type well 3, a field insulating film 4, and a gate insulating film are formed on a main surface of a semiconductor substrate 1 made of p ^- type silicon single crystal by a known method. After the films 5 are sequentially formed, the gate electrodes FG _1n and p of the n-channel MISFET Qn in the logic section are formed.
The gate electrode FG _1p of the channel type MISFET Qp is formed. Next, a low-concentration n ⁻ -type semiconductor region 9 that forms part of the source and drain regions of the n-channel MISFET Qn and a low-concentration p ⁻ -type part that forms part of the source and drain regions of the p-channel MISFET Qp A semiconductor region 10 is formed. Thereafter, the silicon nitride film deposited on the semiconductor substrate 1 is processed by anisotropic etching such as RIE to form sidewall spacers 11 on the side walls of the gate electrodes FG _1n and FG _{1p in} the logic portion. Next, the n-channel type M of the logic section
A high-concentration n ⁺ -type semiconductor region 12 that forms another part of the source region and the drain region of the ISFET Qn, and a high-concentration p ⁺ -type semiconductor that forms another part of the source and drain regions of the p-channel MISFET Qp A region 13 is formed.

Next, as shown in FIG.
A metal film is deposited thereon by a sputtering method or a CVD method, and thereafter, the semiconductor substrate 1 is subjected to a heat treatment, so that n of the n-channel MISFET Qn in the logic portion is formed.
Surface of ⁺ type semiconductor region 12 and p-channel type MISF
On the surface of the p ⁺ type semiconductor region 13 of the ETQp, a silicide layer 14 for reducing the parasitic resistance of the source region and the drain region is formed. Next, the unreacted metal film is removed by washing or the like.

Next, as shown in FIG.
A photoresist 16 is applied thereon, and then the photoresist 16 is patterned by exposing using a Levenson-type mask. Thereafter, DRA is performed using the patterned photoresist 16 as a mask.
The silicon nitride film 7 of the M memory cell is etched, and then the polycrystalline silicon film 6 is etched to form the gate electrode FG _2n (6) of the memory cell selecting MISFET of the DRAM memory cell.

Next, after the photoresist 16 is removed,
Using a photoresist (not shown) and a laminated film composed of the silicon nitride film 7 and the polycrystalline silicon film 6 as a mask,
A low-concentration n-type impurity, for example, P is ion-implanted into the p-type well 2 of the DRAM section memory cell, and a memory cell selection MI is performed.
A low-concentration n ⁻ -type semiconductor region 17 constituting the source region and the drain region of the SFET is formed in self-alignment with the gate electrode FG _2n (6). Next, as shown in FIG. 20, a silicon nitride film 18 is deposited on the semiconductor substrate 1.

Next, as shown in FIG.
A silicon oxide film 19 having a planarized surface is deposited thereon.

Then, as shown in FIG. 22, the DRAM is self-aligned by the same manufacturing method as in the first embodiment.
A first contact hole 20 reaching the n ⁻ -type semiconductor region 17 of the memory cell selecting MISFET of the memory cell is formed. First, the silicon oxide film 19 is etched using a patterned photoresist (not shown) as a mask, and an M
After forming the upper portion of the first contact hole 20 reaching the n ⁻ type semiconductor region 17 of the ISFET, the silicon nitride film 18 is subsequently etched to form the lower portion of the first contact hole 20.

Next, as shown in FIG.
A polycrystalline silicon film or a laminated film of a sputtered tungsten film and a CVD tungsten film,
After depositing a conductive film such as a laminated film of an iN film and a CVD tungsten film, the conductive film is buried in the first contact hole 20 by planarizing the surface of the conductive film by a CMP method or an etch-back method. Then, the embedded wiring 22 is formed.

Thereafter, though not shown, silicide layers 14 and p formed on the surface of n ⁺ type semiconductor region 12 of n channel type MISFET Qn in the logic portion are formed by the same manufacturing method as in the first embodiment. Channel type MIS
Second contact hole 25 reaching silicide layer 14 formed on the surface of p ⁺ type semiconductor region 13 of FET Qp
Is formed, and then the bit line B of the DRAM section memory cell is formed.
Forming a metal wiring M ₁ of the first layer L and logic unit.

As described above, according to the second embodiment, similarly to the first embodiment, the n-channel type M
ISFET Qn and p-channel MISFET Qp,
Or MIS for selecting a memory cell of a DRAM section memory cell
Since the gate electrode can be processed in accordance with the layout characteristics of each FET, the n-channel MISFET Qn and the p-channel MISFET Q
Since the variation in the operating characteristics of p can be reduced, the variation in the threshold voltage can be reduced, the current driving capability can be improved, and the offset current can be reduced. In the DRAM memory cell, the memory cell can be miniaturized. Also, any layout can be DRA
First contact hole 2 provided in M section memory cell
0 and the second contact hole 2 provided in the logic section
5 is an n-channel type MISF of an element isolation region and a logic portion
ETQn gate electrode FG _1n and p-channel type MIS
Since the gate electrode FG _1p of the FET Qp and the gate electrode FG _{2n of the} MISFET for selecting a memory cell of the DRAM memory cell can be formed by self-alignment, the layout margin can be improved. In addition, when the embedded wiring 22 provided in the DRAM memory cell is formed of a metal film such as a tungsten film, the series resistance of the embedded wiring 22 can be reduced, and the speed of the memory operation can be increased.

Further, the n-channel MIS of the logic section
The current drive of the n-channel MISFET Qn and the p-channel MISFET Qp by forming a silicide layer 14 on the surface of the source region and the drain region of the FET Qn and the p-channel MISFET Qp to reduce the parasitic resistance of the source and drain regions. Although the performance has been improved, since the silicide layer is not formed on the surface of the source region and the drain region of the memory cell selection MISFET of the DRAM memory cell, the leakage current is increased due to metal contamination from the silicide layer. DR
It is possible to prevent the refresh characteristic of the AM section memory cell from deteriorating.

(Embodiment 3) An n-channel MISFET Qn and a p-channel MISF of a logic portion in a logic embedded DRAM according to another embodiment of the present invention.
The method of manufacturing the ETQp and the memory cell of the DRAM section will be described with reference to cross-sectional views of main parts of the semiconductor substrate shown in FIGS.

First, as shown in FIG. 24, a p-type well 2, an n-type well 3, a field insulating film 4, and a gate insulating film are formed on a main surface of a semiconductor substrate 1 made of p ^- type silicon single crystal by a known method. 5 are sequentially formed, and then the gate electrodes FG _1n and p of the n-channel type MISFET Qn in the logic section are formed.
A gate electrode FG _1p of the channel type MISFET Qp and a memory cell selecting MISF of a DRAM section memory cell
An ET gate electrode FG _2n is formed. Next, a low-concentration n ⁻ -type semiconductor region 9 constituting a part of the source region and the drain region of the n-channel MISFET Qn in the logic section
For selecting memory cell of memory cell of DRAM and DRAM section
After forming the n ⁻ -type semiconductor region 17 constituting the source region and the drain region of the FET, the low-concentration p ⁻ -type semiconductor region 10 constituting a part of the source region and the drain region of the p-channel MISFET Qp in the logic portion is formed. Form.

Next, as shown in FIG.
By processing the silicon nitride film deposited thereon by anisotropic etching such as RIE, sidewalls are formed on the side walls of the gate electrodes FG _1n and FG _{1p of the} logic section and the gate electrode FG _2n of the DRAM section memory cell. The spacer 11 is formed. Then, the p-type well 2 of the logic section
Is ion-implanted with a high concentration n-type impurity, for example, As.
High-concentration n ⁺ -type semiconductor region 12 constituting another part of the source region and drain region of channel type MISFET Qn
To form

Similarly, a high-concentration p-type impurity, for example, BF2, is ion-implanted into the n-type well 3 of the logic portion, and a high-concentration p-type impurity constituting another part of the source region and the drain region of the p-channel MISFET Qp is formed. ^{The +} type semiconductor region 13 is formed.

Next, as shown in FIG.
After depositing the silicon nitride film 28 thereon, as shown in FIG. 27, the silicon nitride film 28 in the logic portion is processed by anisotropic etching such as RIE using the patterned photoresist 29 as a mask, The surface of the n ⁺ -type semiconductor region 12 of the n-channel MISFET Qn of the logic portion and the p ^{+ of the} p-channel MISFET Qp
The surface of the mold semiconductor region 13 is exposed. At this time, the side walls of the sidewall spacers 11 in the side wall of the gate electrode FG _1p gate electrode FG _1n and p-channel type MISFETQp the n-channel type MISFET Qn, sidewall spacers are formed further by a silicon nitride film 28.

Next, after removing the photoresist 29,
A metal film is formed on a semiconductor substrate 1 by sputtering or CV.
Then, the semiconductor substrate 1 is subjected to a heat treatment so that the n-channel type MISF of the logic portion is formed.
On the surface of the n ⁺ type semiconductor region 12 of the ETQn and the surface of the p ⁺ type semiconductor region 13 of the p-channel MISFET Qp, a silicide layer 14 for reducing the parasitic resistance of the source region and the drain region is formed. Next, the unreacted metal film is removed by washing or the like.

Next, as shown in FIG.
A silicon oxide film 19 having a planarized surface is deposited thereon.

Then, as shown in FIG. 30, the DRAM is self-aligned by the same manufacturing method as in the first embodiment.
A first contact hole 20 reaching the n ⁻ -type semiconductor region 17 of the memory cell selecting MISFET of the memory cell is formed. First, the silicon oxide film 19 is etched using a patterned photoresist (not shown) as a mask, and an M
After forming the upper part of the first contact hole 20 reaching the n ⁻ type semiconductor region 17 of the ISFET, the silicon nitride film 28 is subsequently etched to form the lower part of the first contact hole 20.

Next, as shown in FIG.
By depositing a metal film on the semiconductor substrate 1 by a sputtering method or a CVD method, and then performing a heat treatment on the semiconductor substrate 1, a MIS for selecting a memory cell of a memory cell in a DRAM section is formed.
A silicide layer 21 for reducing contact resistance is formed on the surface of the n ⁻ type semiconductor region 17 of the FET. Next, the unreacted metal film is removed by washing or the like. The silicide layer 21 provided in the memory cell of the DRAM section is not formed to be thicker than the junction depth of the n ⁻ type semiconductor region 17 of the MISFET for selecting a memory cell, and is smaller than the silicide layer 14 provided in the logic section. It is formed thin.

Next, as shown in FIG.
A polycrystalline silicon film or a laminated film of a sputtered tungsten film and a CVD tungsten film,
After depositing a conductive film such as a laminated film of an iN film and a CVD tungsten film, the conductive film is buried in the first contact hole 20 by planarizing the surface of the conductive film by a CMP method or an etch-back method. Then, the embedded wiring 22 is formed.

Thereafter, although not shown, silicide layers 14 and p formed on the surface of n ⁺ type semiconductor region 12 of n channel type MISFET Qn of the logic portion are formed by the same manufacturing method as in the first embodiment. Channel type MIS
Second contact hole 25 reaching silicide layer 14 formed on the surface of p ⁺ type semiconductor region 13 of FET Qp
Is formed, and then the bit line B of the DRAM section memory cell is formed.
Forming a metal wiring M ₁ of the first layer L and logic unit.

As described above, according to the third embodiment, similarly to the first embodiment, the n-channel type M
By forming a silicide layer 14 on the surface of each of the source region and the drain region of the ISFET Qn and the p-channel MISFET Qp to reduce the parasitic resistance of the source region and the drain region, the n-channel MISFET Q
The current driving capability of the n- and p-channel MISFETs Qp can be improved. In addition, it becomes possible to form a thin silicide layer 21 on the surface of the source region and the drain region of the MISFET for selecting a memory cell of the DRAM part memory cell in consideration of the junction depth of the source region and the drain region. Junction destruction of the source region and the drain region of the MISFET can be prevented. In any layout, the first contact hole 20 provided in the memory cell of the DRAM section is provided with an element isolation region,
MISFET for memory cell selection of DRAM section memory cell
Can be formed in a self-aligned manner with respect to the gate electrode FG _2n , so that the layout margin of the DRAM memory cell can be improved. In addition, when the embedded wiring 22 provided in the DRAM memory cell is formed of a metal film such as a tungsten film, the series resistance of the embedded wiring 22 can be reduced, and the speed of the memory operation can be increased.

(Embodiment 4) An n-channel MISFET Qn and a p-channel MISF of a logic portion in a logic embedded DRAM according to another embodiment of the present invention.
ETQp and a method of manufacturing a memory cell in a DRAM section will be described with reference to cross-sectional views of main parts of a semiconductor substrate shown in FIGS.

First, as shown in FIG. 33, a p-type well 2, an n-type well 3, a field insulating film 4, and a gate insulating film are formed on a main surface of a semiconductor substrate 1 made of p ^- type silicon single crystal by a known method. 5 are sequentially formed, and then the gate electrodes FG _1n and p of the n-channel type MISFET Qn in the logic section are formed.
A gate electrode FG _1p of the channel type MISFET Qp and a memory cell selecting MISF of a DRAM section memory cell
An ET gate electrode FG _2n is formed. Next, a low-concentration n ⁻ -type semiconductor region 9 constituting a part of the source region and the drain region of the n-channel MISFET Qn in the logic section
For selecting memory cell of memory cell of DRAM and DRAM section
After forming the n ⁻ -type semiconductor region 17 constituting the source region and the drain region of the FET, the low-concentration p ⁻ -type semiconductor region 10 constituting a part of the source region and the drain region of the p-channel MISFET Qp in the logic portion is formed. Form.

Next, by processing the silicon nitride film deposited on the semiconductor substrate 1 by anisotropic etching such as RIE, the gate electrodes FG _1n and F
G _1p and the gate electrode FG of the memory cell in the DRAM section
A sidewall spacer 11 is formed on the side wall of _2n .

Next, as shown in FIG.
A metal film is deposited thereon by a sputtering method or a CVD method, and thereafter, the semiconductor substrate 1 is subjected to a heat treatment, so that n of the n-channel MISFET Qn in the logic portion is formed.
^- surface and the p-channel type semiconductor region 9 MISFET
Surface of p ^- type semiconductor region 10 of TQp and DRA
N ^{− of the} MISFET for selecting the memory cell of the M section memory cell
A thin silicide layer 30 is formed on the surface of the type semiconductor region 17. Next, the unreacted metal film is removed by washing or the like.

Next, as shown in FIG.
After depositing the silicon nitride film 28 thereon, as shown in FIG. 36, the silicon nitride film 28 in the logic portion is processed by anisotropic etching such as RIE using the patterned photoresist 29 as a mask. The surface of the n ⁻ -type semiconductor region 9 of the n-channel MISFET Qn and the surface of the p ⁻ -type semiconductor region 10 of the p-channel MISFET Qp in the logic portion are exposed. At this time, the surface of the n ⁻ -type semiconductor region 9 of the n-channel MISFET Qn and the p ⁻ -type semiconductor region 1 of the p-channel MISFET Qp
The silicide layer 30 formed on the surface of No. 0 is removed.

Next, as shown in FIG. 37, the photoresist 29 is removed, and if necessary, a cleaning for completely removing the silicide layer 30 remaining under the sidewall spacers 11 is performed. A high-concentration n-type impurity, for example, As is ion-implanted into the p-type well 2 of the portion to form a high-concentration n ⁺ -type semiconductor region 12 constituting another part of the source region and the drain region of the n-channel MISFET Qn. I do.

Similarly, a high-concentration p-type impurity, for example, BF2, is ion-implanted into the n-type well 3 of the logic portion, and a high-concentration p-type impurity forming another part of the source region and the drain region of the p-channel MISFET Qp is formed. ^{The +} type semiconductor region 13 is formed.

Next, a metal film is deposited on the semiconductor substrate 1 by a sputtering method or a CVD method, and thereafter, the semiconductor substrate 1 is subjected to a heat treatment to thereby form the n ⁺ -type semiconductor region 12 of the n-channel MISFET Qn in the logic portion.
And a p ⁺ -type semiconductor region 13 of the p-channel type MISFET Qp, a silicide layer 31 for reducing the parasitic resistance of the source region and the drain region is formed. Next, the unreacted metal film is removed by washing or the like.

Next, as shown in FIG. 38, a silicon oxide film 19 whose surface is flattened is deposited on the semiconductor substrate 1.

Next, as shown in FIG. 39, by the same manufacturing method as that in the first embodiment, the semiconductor device is formed on the surface of the n ⁻ type semiconductor region 17 of the memory cell selecting MISFET of the DRAM memory cell in a self-aligned manner. A first contact hole 20 reaching the silicide layer 30 is formed. First, the silicon oxide film 19 is etched using a patterned photoresist (not shown) as a mask, and the silicide layer 30 formed on the surface of the n ⁻ type semiconductor region 17 of the memory cell selecting MISFET of the DRAM memory cell is formed. After forming the upper part of the first contact hole 20 reaching
Subsequently, the silicon nitride film 28 is etched to form a lower portion of the first contact hole 20.

Next, as shown in FIG.
A polycrystalline silicon film or a laminated film of a sputtered tungsten film and a CVD tungsten film,
After depositing a conductive film such as a laminated film of an iN film and a CVD tungsten film, the conductive film is buried in the first contact hole 20 by planarizing the surface of the conductive film by a CMP method or an etch-back method. Then, the embedded wiring 22 is formed.

Thereafter, although not shown, silicide layers 31 and p formed on the surface of n ⁺ -type semiconductor region 12 of n-channel MISFET Qn in the logic portion are formed by the same manufacturing method as in the first embodiment. Channel type MIS
A second contact hole 25 is formed to reach the silicide layer 31 formed on the surface of the p ⁺ type semiconductor region 13 of the FET. Then, the bit line BL of the DRAM memory cell and the first metal wiring of the logic part are formed. to form the M _1.

As described above, according to the fourth embodiment, similarly to the first embodiment, the n-channel M
By forming a silicide layer 31 on the surface of each of the source and drain regions of the ISFET Qn and the p-channel MISFET Qp to reduce the parasitic resistance of the source and drain regions, the n-channel MISFET Q
The current driving capability of the n- and p-channel MISFETs Qp can be improved. In addition, it becomes possible to form a thin silicide layer 30 on the surface of the source and drain regions of the memory cell selecting MISFET of the DRAM memory cell, taking into account the junction depth of the source and drain regions. Junction destruction of the source region and the drain region of the MISFET can be prevented. In any layout, the first contact hole 20 provided in the memory cell of the DRAM section is provided with an element isolation region,
MISFET for memory cell selection of DRAM section memory cell
Can be formed in a self-aligned manner with respect to the gate electrode FG _2n , so that the layout margin of the DRAM memory cell can be improved. In addition, when the embedded wiring 22 provided in the DRAM memory cell is formed of a metal film such as a tungsten film, the series resistance of the embedded wiring 22 can be reduced, and the speed of the memory operation can be increased.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the above-described embodiment, a case has been described in which the present invention is applied to a method of manufacturing a semiconductor integrated circuit device in which a logic circuit and a DRAM are mounted, but a logic circuit and an electrically rewritable nonvolatile memory are mounted together. The present invention can be applied to a method of manufacturing a semiconductor integrated circuit device.

[0088]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, the memory cell of the DRAM section can be miniaturized, and the circuit design margin of the logic section and the current drive capability of the MISFET can be improved. And high performance can be realized.

Further, according to the present invention, the source region of the MISFET for selecting a memory cell of the memory cell of the DRAM section,
Since a silicide layer suitable for the junction depth of the drain region can be formed on the surfaces of the source region and the drain region of the MISFET for memory cell selection, the logic embedded DRA
High reliability of M can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a logic mixed DR according to an embodiment of the present invention;
FIG. 9 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing an AM.

FIG. 2 is a diagram showing a logic mixed DR according to an embodiment of the present invention;
FIG. 9 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing an AM.

FIG. 3 is a diagram showing a logic mixed DR according to an embodiment of the present invention;
FIG. 9 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing an AM.

FIG. 4 is a diagram showing a logic-mixed DR according to an embodiment of the present invention;
FIG. 9 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing an AM.

FIG. 5 is a diagram showing a logic mixed DR according to an embodiment of the present invention;
FIG. 9 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing an AM.

FIG. 6 is a diagram showing a logic mixed DR according to an embodiment of the present invention;
FIG. 9 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing an AM.

FIG. 7 is a diagram showing a logic mixed DR according to an embodiment of the present invention;
FIG. 9 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing an AM.

FIG. 8 shows a logic-mixed DR according to an embodiment of the present invention;
FIG. 9 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing an AM.

FIG. 9 shows a logic-mixed DR according to an embodiment of the present invention;
FIG. 9 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing an AM.

FIG. 10 shows a logic embedding D according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method for manufacturing a RAM.

FIG. 11 shows a logic mixed D according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method for manufacturing a RAM.

FIG. 12 shows a logic embedding D according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method for manufacturing a RAM.

FIG. 13 is a diagram illustrating a logic embedding D according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method for manufacturing a RAM.

FIG. 14 shows a logic embedding D according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method for manufacturing a RAM.

FIG. 15 shows a logic embedding D according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method for manufacturing a RAM.

FIG. 16 shows a logic embedding D according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method for manufacturing a RAM.

FIG. 17 is a diagram illustrating a logic embedding D according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method for manufacturing a RAM.

FIG. 18 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a logic-embedded DRAM according to another embodiment of the present invention;

FIG. 19 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method for manufacturing a logic-embedded DRAM according to another embodiment of the present invention;

FIG. 20 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a logic-embedded DRAM according to another embodiment of the present invention;

FIG. 21 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a logic-embedded DRAM according to another embodiment of the present invention;

FIG. 22 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method for manufacturing a logic-embedded DRAM according to another embodiment of the present invention;

FIG. 23 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method for manufacturing a logic-embedded DRAM according to another embodiment of the present invention;

FIG. 24 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a logic-embedded DRAM according to another embodiment of the present invention;

FIG. 25 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method for manufacturing a logic-embedded DRAM according to another embodiment of the present invention;

FIG. 26 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a logic-embedded DRAM according to another embodiment of the present invention;

FIG. 27 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a logic-embedded DRAM according to another embodiment of the present invention;

FIG. 28 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a logic-embedded DRAM according to another embodiment of the present invention;

FIG. 29 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method for manufacturing a logic-embedded DRAM according to another embodiment of the present invention;

FIG. 30 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method for manufacturing a logic-embedded DRAM according to another embodiment of the present invention;

FIG. 31 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a logic-embedded DRAM according to another embodiment of the present invention;

FIG. 32 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a logic-embedded DRAM according to another embodiment of the present invention;

FIG. 33 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method for manufacturing a logic-embedded DRAM according to another embodiment of the present invention;

FIG. 34 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a logic-embedded DRAM according to another embodiment of the present invention;

FIG. 35 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the logic-embedded DRAM according to another embodiment of the present invention;

FIG. 36 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method for manufacturing a logic-embedded DRAM according to another embodiment of the present invention;

FIG. 37 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a logic-embedded DRAM according to another embodiment of the present invention;

FIG. 38 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a logic-embedded DRAM according to another embodiment of the present invention;

FIG. 39 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method for manufacturing a logic-embedded DRAM according to another embodiment of the present invention;

FIG. 40 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the logic-embedded DRAM according to another embodiment of the present invention;

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 p-type well 3 n-type well 4 field insulating film 5 gate insulating film 6 polycrystalline silicon film 7 silicon nitride film 8 photoresist 9 n ^- type semiconductor region 10 p ^- type semiconductor region 11 sidewall spacer 12 n ⁺ Type semiconductor region 13 p ⁺ type semiconductor region 14 silicide layer 15 silicon nitride film 16 photoresist 17 n ⁻ type semiconductor region 18 silicon nitride film 19 silicon oxide film 20 first contact hole 21 silicide layer 22 buried wiring 23 silicon oxide film 24 Photoresist 25 Second contact hole 26 Titanium nitride film 27 Tungsten film 28 Silicon nitride film 29 Photoresist 30 Silicide layer 31 Silicide layer FG _1n gate electrode (n-channel MIS of logic part)
FET) FG _1p gate electrode (p channel type MIS of logic part)
FET) FG _2n gate electrode (memory cell selecting MISFET DRAM section memory cell) Qn n-channel type MISFET Qp p-channel type MISFET BL bit lines M ₁ first layer metal wirings

Claims (10)

[Claims] 1. A logic embedded DRAM in which a logic and a DRAM are mixed, wherein a MISFET of a logic part and a memory cell selecting MISF of a DRAM part memory cell are provided.
A method for manufacturing a semiconductor integrated circuit device for forming an ET, comprising: a gate electrode of a MISFET in a logic portion;
A method of manufacturing a semiconductor integrated circuit device, wherein the semiconductor memory device is formed in a manufacturing process different from that of a gate electrode of a memory cell selection MISFET of a memory cell. 2. A logic embedded DRAM in which a logic and a DRAM are mixed, wherein a MISFET in a logic part and a memory cell selection MISF in a DRAM part memory cell are provided.
A method for manufacturing a semiconductor integrated circuit device for forming an ET, comprising: a gate electrode of a MISFET in a logic portion;
Formed in a different manufacturing process from the gate electrode of the memory cell selecting MISFET of the
The silicide layer provided on the surface of the source region and the drain region of the SFET and the silicide layer provided on the surface of the source region and the drain region of the memory cell selection MISFET of the DRAM memory cell are formed in different manufacturing steps. Of manufacturing a semiconductor integrated circuit device. 3. A logic embedded DRAM in which a logic and a DRAM are embedded, wherein a MISFET in a logic part and a memory cell selection MISF in a DRAM part memory cell are provided.
A method of manufacturing a semiconductor integrated circuit device for forming an ET, comprising: (a) forming a gate electrode of a MISFET in a logic part; and (b) forming a source region and a drain region of the MISFET in a logic part. , MI of the logic unit
(C) forming a gate electrode of a MISFET for selecting a memory cell of a DRAM memory cell, and (d) forming a gate electrode of a MISFET for selecting a memory cell of the DRAM memory cell. M for memory cell selection
After forming the source and drain regions of the ISFET,
MISF for selecting a memory cell of the DRAM section memory cell
Forming a first contact hole reaching a source region and a drain region of the ET; and (e) a source region of a memory cell selecting MISFET of the DRAM portion memory cell exposed at a bottom of the first contact hole; A method for manufacturing a semiconductor integrated circuit device, comprising: a step of forming a silicide layer on a surface of a drain region; and (f) a step of burying a conductive film in the first contact hole. 4. A logic embedded DRAM in which a logic and a DRAM are mixed, wherein a MISFET in a logic part and a memory cell selection MISF in a DRAM part memory cell are provided.
A method of manufacturing a semiconductor integrated circuit device for forming an ET, comprising: (a) forming a gate electrode of a MISFET in a logic part; and (b) forming a source region and a drain region of the MISFET in a logic part. , MI of the logic unit
(C) forming a gate electrode of a MISFET for selecting a memory cell of a DRAM memory cell, and (d) forming a gate electrode of a MISFET for selecting a memory cell of the DRAM memory cell. M for memory cell selection
After forming the source and drain regions of the ISFET,
MISF for selecting a memory cell of the DRAM section memory cell
Forming a first contact hole reaching a source region and a drain region of the ET; and (e) burying a conductive film in the first contact hole. Production method. 5. A logic-loaded DRAM in which a logic and a DRAM are loaded, wherein a MISFET in a logic section and a MISFET for selecting a memory cell in a memory cell in the DRAM section are provided.
A method of manufacturing a semiconductor integrated circuit device for forming an ET, comprising the steps of:
Simultaneously forming a gate electrode of a memory cell selecting MISFET of the AM memory cell; and (b) a source region, a drain region and a DRA of the MISFET of the logic portion.
Forming a source region and a drain region of the memory cell selecting MISFET of the M-part memory cell, respectively, and (c).
Forming a silicide layer on the surface of the source region and the drain region of the MISFET of the logic unit; and (d) a MISFET for selecting a memory cell of the DRAM unit memory cell.
Forming a first contact hole reaching the source region and the drain region of the DRAM, and (e) a source region and a drain of a memory cell selecting MISFET of the DRAM portion memory cell exposed at the bottom of the first contact hole. A method of manufacturing a semiconductor integrated circuit device, comprising: a step of forming a silicide layer on a surface of a region; and (f) a step of burying a conductive film in the first contact hole. 6. In a logic embedded DRAM in which logic and a DRAM are mixed, a MISFET in a logic part and a memory cell selection MISF in a DRAM part memory cell.
A method of manufacturing a semiconductor integrated circuit device for forming an ET, comprising the steps of:
Simultaneously forming a gate electrode of a memory cell selecting MISFET of an AM memory cell; and (b) a low concentration semiconductor region and a DRAM memory cell which constitute a part of a source region and a drain region of the MISFET of a logic portion. Forming a source region and a drain region of the memory cell selecting MISFET of (c).
Forming a first silicide layer on the surface of the low-concentration semiconductor region forming a part of the source region and the drain region of T and on the surface of the source region and the drain region of the memory cell selecting MISFET of the DRAM unit memory cell; , (D).
After removing the first silicide layer formed on the surface of the low-concentration semiconductor region forming a part of the source region and the drain region of the MISFET of the logic unit, the other of the source region and the drain region of the MISFET of the logic unit is removed. Then, a high-concentration semiconductor region constituting a part of the first silicide layer is formed on the surface of the high-concentration semiconductor region constituting another part of the source and drain regions of the MISFET in the logic part. Forming a thick second silicide layer; and (e) a first silicide layer reaching the first silicide layer formed on the surface of the source and drain regions of the memory cell selecting MISFET of the DRAM unit memory cell. Forming a contact hole, and (f) embedding a conductive film in the first contact hole. Method of manufacturing an integrated circuit device. 7. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the gate insulating film of the MISFET in the logic unit is formed of a gate insulating film of a MISFET for selecting a memory cell in a memory cell in the DRAM unit. A method for manufacturing a semiconductor integrated circuit device, wherein the method is formed to be thinner than a film. 8. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said DRAM is
Wherein the first contact hole provided in the memory cell is a self-aligned contact. 9. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said silicide layer is provided on a surface of a source region and a drain region of a MISFET of said logic part. Is a MISFET for selecting a memory cell of the DRAM section memory cell.
A method of manufacturing a semiconductor integrated circuit device, wherein the method is formed thicker than the silicide layer provided on the surface of the source region and the drain region. 10. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said DRA
The method for manufacturing a semiconductor integrated circuit device, wherein the conductive film embedded in the first contact hole provided in the M-part memory cell is a metal film.