JP2001237421A - Semiconductor device, sram and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lower the parasitic resistance of a source/drain region by greatly improving a margin of junction leakage of an MOSFET, having an LDD structure and a salicide structure. SOLUTION: A semiconductor device is provided with a polysilicon gate electrode 116, a gate sidewall insulating film 118a formed at the side wall thereof on a gate protection insulating film 114 and on a gate-insulating film 113 on a semiconductor substrate 101, a comparatively thin extension part 117 formed in the surface layer of the semiconductor substrate, to sandwich a channel region below the gate electrode, a drain/source region consisting of a diffusion layer 120 with a comparatively high impurity concentration deeply formed, so as to sandwich the extension part in the surface layer part of the semiconductor substrate and to be partially overlapped with the extension part in the part closer to the channel region than to the lower part of an edge of the gate sidewall insulating film of the gate insulating film, and a metal silicide layer 121 formed on the impurity diffusion layer for drain/source.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a MOSFET (insulated gate field effect transistor), a semiconductor memory and a method of manufacturing the same, and more particularly to a lightly doped drain (LDD) of a MOSFET having a salicide structure. The present invention relates to a structure, a static semiconductor memory (SRAM) and a method of manufacturing the same.

[0002]

2. Description of the Related Art In order to achieve high integration and high performance of LSI devices, devices such as MOSFETs have been miniaturized. However, with the miniaturization, the influence of parasitic resistance components on MOSFETs cannot be ignored. ing.

In order to reduce the parasitic resistance of the gate electrode of the MOSFET, the impurity diffusion layer for source / drain, and the contact portion thereof, a silicide compound layer of a refractory metal such as Ti, Co, Ni, Pt, etc. is used. A salicide structure formed on an electrode and on an impurity diffusion layer for drain / source (hereinafter, referred to as an active area; AA) is employed. Further, in order to improve the characteristics of the MOSFET, an LDD structure is often adopted.

FIG. 11 shows an example of a conventional MOSFET employing an LDD structure and a Ti salicide structure.

In FIG. 11, reference numeral 201 denotes an Si substrate,
3 is a SiO ₂ film (gate insulating film), 204 is a gate electrode made of n + doped polycrystalline Si, 205
Is a protective insulating film (SiO ₂ film) for the gate electrode, 206 is a side wall insulating film (SiN film) formed on the side wall of the gate electrode,
Reference numeral 207 denotes an n-type shallow diffusion layer, 208 denotes an n + -type deep diffusion layer, and 209 denotes, for example, a Ti silicide compound layer.

In forming the MOSFET having the above structure, after forming the gate electrode 204, the gate electrode 205 is formed.
Diffusion layer (extension portion) 20 having a shallow drain / source region so as to have a low impurity concentration
7 is formed. Then, after forming the sidewall insulating film 206, a deep diffusion layer 208 of the drain / source region is formed using the gate electrode 204 and the sidewall insulating film 206 as a mask so as to have a high impurity concentration. Then, a Ti silicide compound layer 209 is formed on the surface of the gate electrode 204 and on the surface of the deep diffusion layer 208 in the drain / source region.

However, the MOSFE having the structure shown in FIG.
In a conventional semiconductor integrated circuit having T,
Diffusion layer (extension portion) 207 with shallow source region
Since the distance between the crossing point (A in the figure) of the deep diffusion layer 209 and the bottom of the Ti silicide compound layer formed on the surface of the deep diffusion layer 208 in the drain / source region is very short, -This is a factor that reduces the margin of the junction leakage current in the source region.

The length of the shallow diffusion layer (extension portion) 207 determined by the width of the sidewall insulating film 206 is mainly P
The parasitic resistance of the shallow diffusion layer (extension portion) 207 having a low impurity concentration increases because the length of the extension portion cannot be shortened in accordance with the gate length even if the gate length is shortened. However, this is one of the factors that degrade the performance of the MOSFET.

On the other hand, a data in which a logic part and a memory part are
In the device, the logic part is generally compared to the memory part.
All require high performance MOSFETs, so
Needs to reduce the sheet resistance of the MOSFET diffusion layer
Yes, TiSi_TwoAnd CoSi _TwoForm metal silicide such as
This has been achieved.

In the memory section, the depth of the source / drain diffusion layer of the MOSFET is formed shallower than that of the logic section. Therefore, when metal silicide is formed on the diffusion layer of the MOSFET in the memory section, spikes are formed at the bottom of the metal silicide. This may increase the possibility of a short circuit with the substrate, which may increase junction leakage in the source / drain diffusion layers.

Therefore, the applicant of the present application has proposed a method of manufacturing a semiconductor device or a memory cell array having a memory section and a logic section on the same chip and a semiconductor memory having a peripheral circuit thereof.
It has been proposed to realize a structure in which metal silicide is selectively formed only in a MOSFET of a logic part or a peripheral circuit without forming metal silicide in an FET (Japanese Patent Application No. 9-29).
No. 7119, and a semiconductor device and a method of manufacturing the same according to JP-A-11-135745). As a result, the characteristics of the MOSFETs of the memory unit or the memory cell array can be improved without impairing the characteristics of the MOSFETs of the logic unit or the peripheral circuit.

In addition, the applicant of the present application discloses that in a device in which a logic portion and, for example, a dynamic memory (DRAM) are mixed, a drain cell is provided in a memory cell transistor.
It has been proposed that metal silicide be formed only on the bit line connection node side of the source region, and that the metal MOS silicide be formed on the drain / source region for other MOS transistors (Japanese Patent Application No. 11-35299). Device and its manufacturing method). Thus, it is possible to prevent the charge retention characteristic from deteriorating due to the junction leak on the capacitor side of the memory cell transistor, and to reduce the resistance of the impurity diffusion layer on the bit line contact side.

In an SRAM having an array of memory cells using CMOS transistors, when an LI (local interconnection) or borderless contact structure is adopted for the cell array, an LDD structure and a salicide as in the conventional example are used as the cell transistors. When the structure is adopted, an inherent problem may occur.

That is, as shown in FIG. 12, the STI (Shallow Trench Isolation) is applied to the interlayer insulating film 301 of the cell array.
lation) the conductive contact plug 30 on the region 302
For example, consider a case where a contact hole is formed by RIE (reactive ion etching) or the like before W is embedded and formed. At the time of this RIE, the STI region 30
2 is etched, the silicide compound layer 30 on the surface of the diffusion layer 304 adjacent to the STI region 302 is etched.
5, the side surface (Si) of the diffusion layer 304 underneath tends to be slightly exposed. Thereafter, if a Ti film 306 is formed as a barrier film on the inner surface of the contact hole before W is embedded as a contact plug 303 in the contact hole, Ti silicide is formed on the slightly exposed Si side surface as described above. Since it is difficult, Ti diffuses along the defect layer in Si, and a junction leak occurs between the silicide compound layer 305 and the substrate (or a well region selectively formed in the surface layer portion of the substrate) 307. Cause you to

In order to avoid this problem, it is conceivable that a salicide structure is not used for the transistor of the memory cell. However, the resistance of the gate electrode of the charge transfer transistor of the memory cell and the resistance of the word line connected to the gate electrode increase, hindering the speeding up of the memory cell selection operation, and the number of points that short-circuit the upper metal wiring to the word line Must be increased, and the pattern area increases accordingly.

[0016]

As described above, in the conventional MOSFET and the method for forming the same, the distance between the substrate junction of the source / drain diffusion layer and the bottom surface of the silicide compound layer on the surface of the source / drain diffusion layer is extremely small. Is so short
There has been a problem that the margin of the junction leakage current is reduced.

If the length of the shallow diffusion layer (extension portion) having a correspondingly low impurity concentration cannot be shortened even if the gate length is shortened, the parasitic resistance increases, and the performance of the MOSFET deteriorates. There is a problem that it is one of the factors that cause this.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has been made by increasing the distance between the substrate junction of the source / drain diffusion layer and the bottom surface of the silicide compound layer on the source / drain diffusion layer. It is an object of the present invention to provide a semiconductor device capable of greatly improving a leakage margin and reducing a parasitic resistance of a source / drain diffusion region.

Further, the present invention has an array of memory cells using CMOS transistors, and is suitable for suppressing a junction leak of a cell transistor when employing an LI (local interconnection) and borderless contact structure. An object of the present invention is to provide an SRAM having a salicide structure and a method of manufacturing the same.

[0020]

According to the present invention, there is provided a semiconductor device comprising:
A semiconductor substrate, a gate insulating film of a MOSFET selectively formed on the surface of the semiconductor substrate, a gate electrode formed on the gate insulating film, and a protective insulating film formed on the surface of the gate electrode. A gate sidewall insulating film formed on the protective insulating film and on the gate insulating film at a sidewall portion of the gate electrode, and formed shallowly with a channel region under the gate electrode sandwiched at a surface layer portion of the semiconductor substrate; An extension portion having a relatively low impurity concentration and a surface layer portion of the semiconductor substrate sandwiching the extension portion, and being closer to the channel region than below an edge of the gate sidewall insulating film on the gate insulating film. A MOS formed of a diffusion layer having a relatively high impurity concentration formed deeply so as to partially overlap with the extension portion at a portion.
It is characterized by comprising a drain / source region of a FET and a metal silicide compound layer formed on the impurity diffusion layer for the drain / source.

According to the method of manufacturing a semiconductor device of the present invention, a step of forming a gate electrode of a MOSFET on a semiconductor substrate via a gate insulating film, and a step of selectively forming a MOSFET on a surface portion of the semiconductor substrate using the gate electrode as a mask. Forming an extension portion made of a shallow diffusion layer for drain / source, forming a sidewall insulating film on the gate insulating film and on a side wall of the gate electrode, and forming a part of a side surface portion of the sidewall insulating film. Removing, then, selectively forming a deep diffusion layer for a drain / source of a MOSFET in a surface layer portion of the semiconductor substrate using the gate electrode and the sidewall insulating film as a mask; Forming a metal silicide compound layer on the source impurity diffusion layer.

The SRAM of the present invention has an SR using a MOSFET in which metal silicide is formed only on the surface of the gate electrode among the gate electrode and the source / drain regions.
An array region of AM cells, a peripheral circuit region in which a MOSFET for a peripheral circuit in which metal silicide is formed on each surface of the gate electrode and the source / drain regions,
An element isolation region having a shallow trench structure formed adjacent to the MOSFET in the cell array region; a part of the cell array region on the source / drain region of the MOSFET and the source / drain formed on the element isolation region; A MOSFET in the cell array region, wherein a metal silicide compound layer is formed on the polysilicon gate electrode without forming a metal silicide compound layer on the source / drain region. It is characterized by having.

A first method of manufacturing an SRAM according to the present invention is a method of manufacturing an SRAM in a cell array region and a peripheral circuit region of a semiconductor substrate.
Forming a MOSFET having a polysilicon gate electrode by element isolation by regions, forming an SiO ₂ film for protecting the surface of the polysilicon gate electrode and the surface of the semiconductor substrate, and then forming a gate protection film Forming a first SiN layer on the entire surface, then removing the first SiN layer other than the cell array region, and then forming the first SiN layer on the gate electrode of the MOSFET in the peripheral circuit region. A step of forming a metal silicide layer on the drain / source diffusion layer, a step of forming a second SiN layer over the entire surface, and then forming an interlayer insulating film; Performing a planarization process until the insulating film on the upper portion of the SiN layer disappears, exposing the upper surface of the second SiN layer, and then etching away the exposed second SiN layer, Exposing a top surface of the polysilicon gate electrode of the serial cell array region, it will be characterized by comprising the step of forming a metal silicide layer on the polysilicon gate electrode of the cell array region.

In a second method of manufacturing an SRAM of the present invention, an STI is provided in a cell array region and a peripheral circuit region of a semiconductor substrate.
Forming a MOSFET having a polysilicon gate electrode by element isolation by regions, forming an SiO ₂ film for protecting the surface of the polysilicon gate electrode and the surface of the semiconductor substrate, Forming a layer, forming an interlayer insulating film, and then performing a flattening process until the SiN layer on the polysilicon gate electrode is exposed to expose an upper surface of the SiN layer; Removing the interlayer insulating film other than the cell array region, and then removing the SiN layer and the SiO ₂ film on the polysilicon gate electrode and on the drain / source diffusion layer of the MOSFET in the peripheral circuit region. To expose the upper surface of the polysilicon gate electrode and the upper surface of the drain / source diffusion layer of the MOSFET in the peripheral circuit region. Forming a metal silicide layer on the exposed polysilicon gate electrode and on the drain / source diffusion layer of the MOSFET in the peripheral circuit region.

According to a third method of manufacturing an SRAM of the present invention, an STI is applied to a cell array region and a peripheral circuit region of a semiconductor substrate.
Forming a polysilicon gate electrode by element isolation by regions, forming an SiO ₂ film for protecting the surface of the polysilicon gate electrode and the surface of the semiconductor substrate, and then forming the peripheral circuit MOSFET in area
Forming a drain / source diffusion layer, and then forming an SiO ₂ film on a polysilicon gate electrode of the MOSFET in the peripheral circuit region and an S ₂ film on the drain / source diffusion layer.
By removing the iO ₂ film, the M of the peripheral circuit region is reduced.
Exposing the upper surface of the polysilicon gate electrode and the upper surface of the drain / source diffusion layer of the OSFET;
Forming a metal silicide layer on the polysilicon gate electrode and the drain / source diffusion layer of the MOSFET in the exposed peripheral circuit region, and then forming an SiN layer on the entire surface and then forming an interlayer insulating film And then the Si on the polysilicon gate electrode in the peripheral circuit region.
Perform a flattening process until the insulating film on the N layer disappears,
Exposing the upper surface of the SiN layer, then etching away the exposed SiN layer to expose the upper surface of the polysilicon gate electrode, and then forming a metal silicide on the exposed polysilicon gate electrode. Forming a layer.

[0026]

Embodiments of the present invention will be described below in detail with reference to the drawings.

<First Embodiment of Method for Forming MOSFET> FIGS. 1 to 4 show an nMOS having a salicide structure.
1 shows an example of a FET forming process.

First, as shown in FIG.
SiO 2 on the substrate 101 by thermal oxidation _TwoForm film 102
And then a LP-CVD (Low Pressure Vapor Deposition) method
Crystalline Si103 is formed, and LP-CV
SiO method by D method_TwoA film 104 is formed. After this,
By etching method, a resist pattern is formed
105 is formed.

Next, as shown in FIG. 1B, using the resist pattern 105 as a mask, the SiO ₂ film 104 is etched by anisotropic dry etching having a selectivity with respect to the polycrystalline Si film 103. Then, the resist pattern 105 is removed while leaving the region of the SiO ₂ film 106.

After that, using the SiO ₂ film 106 as a mask, the polycrystalline Si film 1 is anisotropically dry-etched so as to have a sufficient selectivity with respect to the SiO ₂ film 102.
03 is etched to leave a region of the polycrystalline Si film 107. Further, the SiO ₂ film 102 is etched to
The region of the iO ₂ film 108 is left.

Next, as shown in FIG.
O selectivity with respect to ₂ film 108 is 0.5μm etching the Si substrate 101 by well take anisotropic dry etching to form a groove 109 of the STI region.

Next, as shown in FIG.
After depositing the SiO ₂ film 110 on the entire surface by the VD method, chemical mechanical polishing (CMP) that can obtain a selectivity with respect to the polycrystalline Si film 107.
The SiO ₂ film 110 is planarized by a method.

Next, the buried SiO ₂ film 110 is etched by etching the SiO ₂ film 106 and the SiO ₂ film 110 by NH ₄ F or dry etching until the polycrystalline Si film 107 is just exposed.
Leave.

Next, as shown in FIG.
After the polycrystalline Si film 107 is etched and removed by isotropic dry etching capable of obtaining a selectivity with respect to the O ₂ film 108, a heat treatment for reducing the film stress of the buried SiO ₂ film 110 is performed.

Next, the SiO ₂ film 1 on the surface of the Si substrate 101
After etching and removing 08 with NH ₄ F, an SiO ₂ film (sacrificial oxide film) 111 is formed by thermal oxidation.

Thereafter, B (boron) ions are implanted to form the p-well region 112. further,
B ions are implanted to control the threshold value of the nMOSFET. Then, in order to activate the introduced impurities, heat treatment is performed at a predetermined temperature for a predetermined time.

Next, after removing the SiO ₂ film (sacrificial oxide film) 111 on the surface of the Si substrate 101 on which the well region 112 has been formed as described above, FIG.
A gate insulating film 113 is formed as shown in FIG.

Thereafter, in order to form the gate electrode 116, polycrystalline Si is deposited by LP-CVD, and then a resist pattern 1 for forming the gate electrode is formed by photolithography.
15 is formed, and the polycrystalline Si is etched by anisotropic dry etching capable of obtaining a sufficient selectivity with respect to SiO ₂ 111, leaving the gate electrode 116, and the resist pattern 115 is stripped.

Next, as shown in FIG. 3A, a relatively thin portion serving as an extension portion of the source / drain diffusion layer of the nMOSFET is sandwiched between the surface region of the Si substrate 101 and the channel region below the gate electrode 116. A shallow diffusion layer (shallow extension) 117 having an impurity concentration is formed. At this time, the implantation of As ions is performed at a predetermined acceleration voltage,
Performed at a dose of conditions, heat treatment is performed for a predetermined time in N ₂ atmosphere at a predetermined temperature. Then, as a gate protection insulating film,
An SiO ₂ film (post-oxide film) 114 is formed by thermal oxidation.

Next, as shown in FIG.
A SiN film 118 is formed on the entire surface by VD or PVD.
Then, a TEOS film 119 is deposited thereon to a thickness of 100 nm.

Next, as shown in FIG. 3C, anisotropic etching (for example, RIE) is performed on the TEOS film 119 using the SiN film 118 as a stopper to form the gate electrode 1.
The TEOS film (TEOS side wall) 119a is left on the 16 side wall portion. Subsequently, in order to remove the exposed SiN film 118, RIE or wet etching (for example, H ₃ PO ₄ etching) for obtaining an etching selectivity with respect to the TEOS side wall 119a / SiO ₂ film (post-oxide film) 114 is performed. Do. As a result, the SiN film 118 on the gate protective insulating film 114 and the gate insulating film 113 on the side wall portion of the gate electrode 116 becomes a gate sidewall insulating film 118a.
Remains as.

Next, as shown in FIG. 4A, the TEOS side wall 119a is recessed by 40 to 50 nm by wet etching (for example, diluted hydrofluoric acid). Thereafter, for example, As ions are implanted under the conditions of a predetermined acceleration voltage and a dose, and a heat treatment is performed for a predetermined time in an N ₂ atmosphere at a predetermined temperature to obtain a deep diffusion layer 120 and to change the gate electrode 116 to an n + type Doping.

Accordingly, the extension portion 117 is sandwiched between the surface layer portion of the well region 112 and the extension portion 117 at a portion closer to the channel region than below the edge of the gate sidewall insulating film 118a on the gate insulating film 113. A deep diffusion layer (deep Extension) 120 having a relatively high impurity concentration and serving as a drain / source diffusion layer of the nMOSFET is formed so as to partially overlap.

Next, as shown in FIG. 4B, the exposed SiO ₂ film (post-oxide film) 114 is removed,
Ti (titanium) / T to form an salicide structure
iN (titanium nitride) is deposited in a thickness of 30/20 nm, respectively. At this time, the SiO ₂ film 114 on the gate side wall, TEOS
Since the side wall 119a and the SiN film 118a do not react with the high melting point metal when the silicide compound layer is formed, the Ti silicide compound layer can be selectively formed. After this,
A heat treatment is performed for a predetermined time in a N ₂ atmosphere at a predetermined temperature, and the T which is not reacted with Si in a mixed solution of sulfuric acid and hydrogen peroxide is used.
Remove i.

Further, a low-resistance Ti silicide compound layer 121 is formed on a part of the deep diffusion layer 120 and on the gate electrode 116 by performing a heat treatment for a predetermined time in an N ₂ atmosphere at a predetermined temperature.

Next, as an interlayer insulating film (not shown), for example, SiO ₂ / BPSG is deposited on the entire surface by LP-CVD.
Deposition is performed to a thickness of 00/900 nm, and planarization is performed by a CMP method. Thereafter, a resist pattern (not shown) for forming a contact hole is formed by photolithography, and the SiO ₂ / BPSG film is etched by anisotropic etching capable of obtaining an etching selectivity with respect to Si, thereby forming the contact hole. To form

Next, a Ti film (not shown) is deposited on the entire surface by sputtering, for example, Ti. Then, a heat treatment is performed for a predetermined time in an N ₂ atmosphere at a predetermined temperature, and the T
TiN is formed on the surface of the i film. Thereafter, in order to form a contact plug by, for example, burying W in the contact hole opening, W is deposited on the entire surface by the CVD method, and then unnecessary W, Ti on the interlayer insulating film is formed by the CMP method.
/ Remove TiN.

Thereafter, AlCu (aluminum copper) and Ti / TiN are deposited on the entire surface, a resist pattern (not shown) is formed by photolithography, and wiring is formed by anisotropic etching using this as a mask.

The nMOSF formed by the above steps
According to the ET, the source / drain diffusion layers 117, 120
Since the distance from the junction with the p-well region 112 to the bottom surface of the silicide compound layer 121 on the surface of the source / drain diffusion layer 120 can be set longer than before, the margin of junction leakage can be greatly improved. Can be.

Further, since a shallow diffusion layer (extension portion) 117 having a low impurity concentration has a structure in which a deep diffusion layer 120 having an impurity concentration is superimposed on a portion near the channel region, a shallow diffusion layer having a substantially low impurity concentration is provided. Since the length of the diffusion layer (extension portion) 117 can be made shorter than before, the parasitic resistance of the shallow diffusion layer (extension portion) 117 can be reduced, and the performance of the MOSFET can be improved.

The semiconductor device of the present invention can also be applied to a transistor having a salicide structure of a refractory metal such as Co, Pt, and Ni other than Ti. In addition,
The SiN side wall 118a is suitable for forming a Ti salicide structure, but when reacting with a high melting point metal when forming a silicide compound layer of a high melting point metal other than Ti,
Instead, it is desirable to form SiO ₂ side walls.

Further, during the CMOS process, the pMOS
The same effect can be expected even if a process similar to the above nMOSFET process is applied to the FET region.

<First Embodiment of SRAM and Manufacturing Method Thereof> FIGS. 5 and 6 show a cell transistor in a cell array area and a peripheral circuit area according to a first embodiment of an SRAM manufacturing method of the present invention. FIG. 4 is a cross-sectional view schematically showing a step of forming a peripheral transistor.

FIG. 6C is a sectional view showing a part of a cell transistor in a cell array region and a part of a peripheral circuit transistor in a peripheral circuit region in the SRAM according to the present invention.

In FIG. 6C, a p-type Si substrate 50 is formed.
Cell transistors are formed in the cell array region on the first line, and peripheral circuit transistors are formed in the peripheral circuit region. Note that the cell transistor and the peripheral transistor may be formed correspondingly on the memory cell array region and the peripheral circuit region on the p-type semiconductor layer (p-well region).

The cell transistor is located at S in the cell array region.
a gate insulating film 502 formed on a channel region of an i-substrate 501; a gate electrode 503 formed on the gate insulating film 502;
And a drain / source region 506 having an LDD structure selectively formed in a surface layer portion of the substrate 501. The gate electrode 503 is obtained by doping polycrystalline Si with an impurity, and has a Ti or Co silicide layer 510 formed on the upper surface thereof.

In the peripheral transistor, a gate insulating film 502 formed on the channel region of the Si substrate 501 in the peripheral circuit region and a gate electrode 503 formed on the gate insulating film 502 sandwich the channel region. And a drain / source region 506 having an LDD structure selectively formed in the surface layer portion of the Si substrate 501 as described above. The gate electrode 503 is obtained by doping impurities into polycrystalline Si, and a Ti or Co silicide layer 507 is formed on the upper surface thereof. A silicide layer 507 of Ti or Co is also formed on the upper surface of the drain / source region 506.

According to the SRAM described above, the peripheral transistor has good characteristics because the metal silicide compound is formed on the upper surface of the gate electrode 503 and the surface of the drain / source region 506 to reduce the resistance.

The cell transistor has a gate electrode 5
Since the metal silicide compound 507 is formed only on the upper surface of the substrate 03 (and also on the upper surface of the word line when the word line is connected to the upper surface) and the resistance is reduced, the speed of the cell selection operation can be increased. . Further, since the metal silicide compound is not formed on the surface of the drain / source region 506 of the cell transistor, when forming the LI structure and the borderless contact as described above with reference to FIG.
When a contact hole is opened in the interlayer insulating film on the STI region by the IE, the exposed area of the Si side surface of the drain / source region 506 of the cell transistor adjacent to the STI region becomes sufficiently large. Therefore, after forming Ti before embedding the W plug, Ti is formed on the side surface of the Si.
Silicide is easily formed, and the junction leak current between the W plug and the Si substrate is suppressed.

Next, a first method of manufacturing the SRAM of the present invention will be described.
An embodiment will be described.

First, as shown in FIG. 5A, a semiconductor substrate (or semiconductor layer) 401 is
Forming a TI region (not shown), after forming the gate electrode 503 of polysilicon with a gate insulating film 502, the SiO ₂ to form a gate protective film 504, further, made of SiN or SiO ₂ gate Sidewall 50
5 is formed, and the drain / source diffusion layer 5 of the MOSFET is formed.
06 is formed. At this time, if necessary, a drain / source diffusion layer is formed with an LDD structure. After this, FIG.
SiN layer 5 serving as an etching stopper when forming an LI contact hole as described above with reference to FIG.
After the formation of the SiN layer 51,
Remove 2.

Next, as shown in FIG. 5B, Ti or C is formed on the gate electrode and the drain / source diffusion layer of the peripheral transistor in the peripheral circuit region by the usual process.
An o silicide layer 507 is formed.

Next, as shown in FIG. 5C, a SiN layer 508 is formed, and a first interlayer insulating film 509 is formed using an LP-BPSG film or the like. Then, a planarization process is performed by CMP or etch back until the insulating film 509 on the SiN layer 508 on the gate electrode disappears, thereby exposing the upper surface of the SiN layer 508.

Next, as shown in FIG. 6A, the exposed SiN layer 508 is removed by an etching method (RIE or wet etching) having an etching selectivity to SiO ₂ , and the polysilicon in the cell array region is removed. The upper surface of the gate electrode 503 is exposed.

Next, as shown in FIG. 6B, Ti or Co is formed to a proper thickness on the polysilicon gate electrode in the cell array region by a sputtering method or a CVD method, and heat treatment is performed. As a result, a Ti or Co silicide layer 510 is formed on the polysilicon gate electrode in the cell array region.

Next, as shown in FIG.
Second interlayer insulating film 51 made of PSG film or TEOS film
After forming No. 1, a flattening process is performed.

According to the SRAM manufacturing method shown in FIGS. 5 and 6, Ti or Ti is formed on the gate electrode and the drain / source diffusion layer of the peripheral transistor in the peripheral circuit region with the cell array region covered with the SiN film 512. Co
Is formed, a Ti or Co silicide layer 510 is formed on the gate electrode of the transistor in the cell array region.

Therefore, the gate electrode 5 of the peripheral transistor
03 and the drain / source diffusion layer 506, the metal silicide exists on the gate electrode 503 of the transistor in the cell array region, but the metal silicide exists on the drain / source diffusion layer 506 of the transistor in the cell array region. A structure in which silicide does not exist can be realized.

As a result, for the peripheral transistors in the peripheral circuit region, the sheet resistance of the drain / source diffusion layer 506 can be reduced to improve the characteristics, and for the transistors in the cell array region, the drain / source diffusion layers can be improved. 5
It is possible to eliminate an increase in junction leakage due to the formation of a metal silicide on the substrate 06.

Further, as compared with the conventional manufacturing method, the number of lithography steps is increased by only one step of removing the SiN film 512 in areas other than the cell array region, and this lithography step does not require formation of a dense pattern. Therefore, it can be easily realized, and an increase in manufacturing cost is small.

<Second Embodiment of SRAM Manufacturing Method> FIGS. 7 and 8 show a second embodiment of the SRAM manufacturing method of the present invention.
FIG. 14 is a cross-sectional view showing a step of forming the cell transistors in the cell array region and the peripheral transistors in the peripheral circuit region according to the embodiment.

First, as shown in FIG. 7A, a semiconductor substrate (or semiconductor layer) 701 is
TI to form a region (not shown), after forming the gate electrode 703 of polysilicon with a gate insulating film 702, the SiO ₂ to form a gate protective film 704, further, made of SiN or SiO ₂ gate Side wall 70
5 and the MOSFET drain / source diffusion layer 70
6 is formed. At this time, if necessary, a drain / source diffusion layer is formed with an LDD structure. After this, FIG.
Layer 70 serving as an etching stopper when forming an LI contact hole as described above with reference to FIG.
7, the first interlayer insulating film 708 is formed using an LP-BPSG film or the like.

Next, as shown in FIG. 7B, a planarization process is performed by CMP until the SiN layer 707 on the gate electrode 703 is exposed, thereby exposing the upper surface of the SiN layer 707.

Next, as shown in FIG. 7C, a resist pattern (not shown) formed using a lithography method is used.
Is used as a mask, the first interlayer insulating film 7 other than the cell array region
08 is removed.

Next, as shown in FIG. 8A, the SiN layer 707 on the gate electrode 703 and the drain / source diffusion layer 706 of the transistor are
By removing the O ₂ film 702, the upper surface of the polysilicon gate electrode 703 and the upper surface of the drain / source diffusion layer 706 of the peripheral transistor are exposed.

Next, as shown in FIG. 8B, Ti or Co is formed to an appropriate thickness by a normal process using a sputtering method or a CVD method, and heat treatment is performed. Exposed polysilicon gate electrode 70
3 and a silicide layer 709 of Ti or Co is formed on the drain / source diffusion layer 706 of the peripheral transistor. After this, the LP-BPSG film or TEOS
After a second interlayer insulating film (not shown) is formed from the film, a planarization process is performed.

Also in the SRAM manufacturing method shown in FIGS. 7 and 8, metal silicide is present on the gate electrode 703 of the peripheral transistor and on the drain / source diffusion layer 706, and the gate electrode 703 of the transistor in the cell array region is formed. Metal silicide exists in the transistor, but the drain / source diffusion layer 706 of the transistor in the cell array region
A structure in which no metal silicide is present thereon can be realized.

In addition, as compared with the conventional manufacturing method, the lithography step is performed in the first interlayer insulating film 7 outside the cell array region.
Only the step of removing 08 is increased by one, and since this lithography step does not require the formation of a dense pattern, it can be easily realized, and the increase in manufacturing cost is small.

<Third Embodiment of SRAM Manufacturing Method> FIGS. 9 and 10 show a third embodiment of the SRAM manufacturing method according to the present invention. FIG. 4 is a cross-sectional view illustrating a step of forming a transistor.

First, as shown in FIG. 9A, a semiconductor substrate (or semiconductor layer) 901 is
TI to form a region (not shown), after forming the gate electrode 903 of polysilicon with a gate insulating film 902, the SiO ₂ to form a gate protective film 904, further, made of SiN or SiO ₂ gate Side wall 90
5 to form a drain / source diffusion layer 9 for the MOSFET.
06 is formed. At this time, if necessary, a drain / source diffusion layer is formed with an LDD structure.

Next, as shown in FIG. 9B, the gate electrode 903 of the peripheral transistor is formed by lithography.
SiO ₂ film 904 and drain / source diffusion layer 9
By removing the SiO ₂ film 902 on the substrate 06, the upper surface of the polysilicon gate electrode of the peripheral transistor and the upper surface of the drain / source diffusion layer 906 are exposed.

Next, as shown in FIG. 9C, Ti or Co is formed to have an appropriate film thickness by a normal process using a sputtering method or a CVD method, and is subjected to a heat treatment to expose the film. On the polysilicon gate electrode 903 and the drain / source diffusion layer 9 of the peripheral transistor
, A silicide layer 907 of Ti or Co is formed.

Next, as shown in FIG.
Layer 90 serving as an etching stopper when forming a contact hole for LI as described above with reference to FIG.
After forming No. 8, a first interlayer insulating film 909 is formed using an LP-BPSG film or the like. Thereafter, a planarization process is performed by CMP or etch back until the insulating film 909 on the SiN layer 908 on the gate electrode 903 disappears, and S
The upper surface of the iN layer 908 is exposed.

Next, as shown in FIG. 10B, the exposed SiN layer 908 is removed by an etching method (RIE or wet etching) having an etching selectivity to SiO ₂ , and the polysilicon gate electrode 90 is removed.
3 is exposed.

Next, as shown in FIG. 10C, Ti or Co is formed to have an appropriate film thickness by a normal process using a sputtering method or a CVD method, and is subjected to a heat treatment to expose the film. Polysilicon gate electrode 90
3, a Ti or Co silicide layer 910 is formed. After that, after the second interlayer insulating film 911 is formed using the LP-BPSG film or the TEOS film, a planarization process is performed.

Also in the method of manufacturing the SRAM shown in FIGS. 9 and 10, metal silicide exists on the gate electrode of the peripheral transistor and on the drain / source diffusion layer 906, and the gate electrode 9 of the transistor in the cell array region is formed.
A structure in which metal silicide is present on the transistor 03, but no metal silicide is present on the diffusion layer 906 of the transistor in the cell array region can be realized.

Further, as compared with the conventional manufacturing method, the lithography process is performed in the SiO ₂ film 902 outside the cell array region.
Is only added by one step, and since this lithography step does not require dense pattern formation,
It can be easily realized and the increase in manufacturing cost is small.

<Modification of SRAM Manufacturing Method> When a peripheral transistor having a metal salicide structure is formed as described in the first to third embodiments of the SRAM manufacturing method, an LDD structure is formed. Sometimes FIGS. 1-3
4A may be adopted to realize the structure shown in FIG.

[0089]

As described above, according to the semiconductor device of the present invention, the substrate junction of the source / drain diffusion layer is connected to the source / drain diffusion layer.
The distance from the bottom surface of the silicide compound layer on the drain diffusion layer can be increased to greatly improve the junction leakage margin, and the source / drain diffusion layer between the gate electrode and the source / drain / contact portion Can be reduced.

Further, the SRAM and the method of manufacturing the SRAM of the present invention have an array of memory cells using CMOS transistors, and when the LI (local interconnection) and borderless contact structure are employed, the junction leakage of the cell transistors is reduced. A salicide structure suitable for suppression can be provided.

[Brief description of the drawings]

FIG. 1 shows a MOS having a Ti salicide structure according to the present invention.
FIG. 4 is a cross-sectional view showing a part of the step of forming the FET.

FIG. 2 is a sectional view showing a step that follows the step of FIG. 1;

FIG. 3 is a sectional view showing a step that follows the step of FIG. 2;

FIG. 4 is a sectional view showing a step that follows the step of FIG. 3;

FIG. 5 is a cross-sectional view showing a part of the step of forming the cell transistors in the cell array area and the peripheral transistors in the peripheral circuit area according to the first embodiment of the SRAM manufacturing method of the present invention.

FIG. 6 is a sectional view showing a step that follows the step of FIG. 5;

FIG. 7 is a cross-sectional view showing a part of the step of forming the cell transistors in the cell array region and the peripheral transistors in the peripheral circuit region according to the second embodiment of the SRAM manufacturing method of the present invention.

FIG. 8 is a sectional view showing a step that follows the step of FIG. 7;

FIG. 9 is a cross-sectional view showing a part of the step of forming the cell transistors in the cell array region and the peripheral transistors in the peripheral circuit region according to the third embodiment of the SRAM manufacturing method of the present invention.

FIG. 10 is a sectional view showing a step that follows the step of FIG. 9;

FIG. 11 is a cross-sectional view showing an example of a conventional MOSFET employing an LDD structure and a Ti salicide structure.

FIG. 12 is a cross-sectional view for explaining a conventional manufacturing method.

[Explanation of symbols]

 Reference Signs List 101: semiconductor substrate, 112: well region, 113: gate insulating film, 114: gate protective insulating film, 116: gate electrode, 117: shallow diffusion layer (extension portion), 118a: gate side wall, 120: deep diffusion layer, 121 ... Ti silicide compound layer.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/10 481 H01L 29/78 301P 21/336 (72) Inventor Kunihiro Kasai Shinsugita, Isogo-ku, Yokohama-shi, Kanagawa Prefecture 8 Machi. Toshiba Yokohama Office F-term (reference) 4M104 BB01 BB14 BB20 BB25 BB40 CC05 DD08 DD09 DD16 DD43 DD78 DD84 EE09 EE17 FF06 FF14 GG09 GG10 GG14 GG16 HH04 HH16 5F040 DA00 DA10 EC01 EA08 EC01 EC01 EC02 EH07 EH08 EJ02 EJ03 EK05 FA04 FA05 FA07 FA10 FA12 FA16 FA19 FB02 FB04 FC00 FC10 FC16 FC19 5F048 AA08 AB01 AC01 BA01 BB06 BB08 BB12 BC01 BC05 BC06 BF01 BF02 BF06 BF07 BF12 BF16 BG14 DA18 BS21 GA25 JA53 MA03 MA06 MA19 NA01 NA08 PR03 PR05 PR09 PR21 PR22 PR29 PR33 PR39 PR40 PR43 PR44 PR45 PR53 PR54 PR55 Z A06

Claims (7)

[Claims] A semiconductor substrate; and a MOSF selectively formed on a surface of the semiconductor substrate.
A gate insulating film of ET; a gate electrode formed on the gate insulating film; a protective insulating film formed on a surface of the gate electrode; and a side wall of the gate electrode on the protective insulating film and the gate insulating film. A gate sidewall insulating film formed on the film; an extension portion having a relatively low impurity concentration formed shallowly across a channel region below the gate electrode in a surface layer portion of the semiconductor substrate; and a surface layer portion of the semiconductor substrate. An impurity formed with the extension portion interposed therebetween and deeply formed so as to partially overlap with the extension portion in a portion closer to the channel region than below an edge of the gate sidewall insulating film on the gate insulating film. Formed on a drain / source region of a MOSFET comprising a diffusion layer having a relatively high concentration and an impurity diffusion layer for the drain / source; The semiconductor device characterized by comprising a metal silicide compound layer. 2. A semiconductor device comprising: a semiconductor substrate having a gate insulating film interposed therebetween;
A step of forming a gate electrode of an OSFET; a step of selectively forming an extension part comprising a shallow diffusion layer for a drain and a source of a MOSFET in a surface layer part of the semiconductor substrate using the gate electrode as a mask; Forming a side wall insulating film on the upper side and on the side wall of the gate electrode; removing a part of the side surface of the side wall insulating film; and forming a surface layer of the semiconductor substrate using the gate electrode and the side wall insulating film as a mask. Selectively forming a deep diffusion layer for the drain and source of the MOSFET in a portion, and forming a metal silicide compound layer on the gate electrode and the impurity diffusion layer for the drain and source. A method for manufacturing a semiconductor device, comprising: 3. An array region of an SRAM cell using a MOSFET in which a metal silicide is formed only on the surface of the gate electrode among the gate electrode and the source / drain region; A peripheral circuit region in which a MOSFET for a peripheral circuit in which metal silicide is formed is formed; an element isolation region having a shallow trench structure formed adjacent to the MOSFET in the cell array region; and a source of the MOSFET in the cell array region. A conductor formed on a part of the drain region and on the element isolation region and in contact with the source / drain region;
A metal silicide compound layer is formed on a polysilicon gate electrode without forming a metal silicide compound layer on a drain region.
M. 4. The SRAM according to claim 3, wherein the MOSFET according to claim 1 is used as at least a part of the MOSFET for the peripheral circuit. 5. A step of forming a MOSFET having a polysilicon gate electrode by separating elements in a cell array region and a peripheral circuit region of a semiconductor substrate by an STI region, and protecting a surface of the polysilicon gate electrode and a surface of the semiconductor substrate. Forming a SiO ₂ film to be formed, then forming a gate protection film, and then forming a first SiN layer on the entire surface and then removing the first SiN layer other than the cell array region Forming a metal silicide layer on the gate electrode and the drain / source diffusion layer of the MOSFET in the peripheral circuit region; and forming a second SiN layer on the entire surface and then forming an interlayer insulating film. Next, a flattening process is performed until the insulating film above the second SiN layer on the gate electrode disappears, and the upper surface of the second SiN layer is exposed. And removing the exposed second SiN layer by etching to expose an upper surface of the polysilicon gate electrode in the cell array region. Next, a metal is formed on the polysilicon gate electrode in the cell array region. Forming a silicide layer. 6. A step of forming a MOSFET having a polysilicon gate electrode by separating elements in a cell array region and a peripheral circuit region of a semiconductor substrate by an STI region, and protecting a surface of the polysilicon gate electrode and a surface of the semiconductor substrate. Forming an SiO ₂ film to be formed, then forming an SiN layer on the entire surface, and then forming an interlayer insulating film, and then planarizing until the SiN layer on the polysilicon gate electrode is exposed. Performing a process to expose the upper surface of the SiN layer; then, removing an interlayer insulating film other than the cell array region; and then, draining a MOSFET on the polysilicon gate electrode and in a peripheral circuit region. The S on the source diffusion layer
By removing the iN layer and the SiO ₂ film, the MO on the upper surface of the polysilicon gate electrode and the peripheral circuit region are removed.
Exposing the upper surface of the drain / source diffusion layer of the SFET; and forming a metal silicide layer on the exposed polysilicon gate electrode and on the drain / source diffusion layer of the MOSFET in the peripheral circuit region. A method of manufacturing a RAM. 7. A cell array region and a periphery of a semiconductor substrate
Polysilicon separated by STI region in circuit region
Forming a gate electrode; and then forming a surface and a half of the polysilicon gate electrode.
SiO that protects the surface of the conductive substrate_TwoStep of forming a film
Next, the drain source of the MOSFET in the peripheral circuit region is
Forming a source diffusion layer; and then, forming polysilicon of the MOSFET in the peripheral circuit region.
SiO on the gate electrode _TwoFilm and drain-source diffusion
SiO on layer_TwoBy removing the film, the peripheral circuit
Top surface of the polysilicon gate electrode of the MOSFET in the region
For exposing the upper surface of the drain and source / drain diffusion layers
Next, the polysilicon of the MOSFET in the exposed peripheral circuit region is
On silicon gate electrode and on drain / source diffusion layer
Forming a metal silicide layer on the substrate, and then forming an SiN layer on the entire surface and then forming an interlayer insulating film.
And then, on the polysilicon gate electrode in the peripheral circuit region.
Flattening process until the insulating film on the SiN layer disappears
Performing a step of exposing the upper surface of the SiN layer. Next, the exposed SiN layer is removed by etching.
Exposing the upper surface of the polysilicon gate electrode; and forming a metal mask on the exposed polysilicon gate electrode.
Forming a re-side layer.
SRAM manufacturing method.