JP2001196461A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an integrated circuit for reducing the parasitic resistance of a CMOS transistor for composing a logic circuit to mixedly mount a large- capacity DRAM and the logic circuit. SOLUTION: This semiconductor device consists of a plurality of first transistors being formed at the first region (for example, a logic circuit region) of a semiconductor layer 10, and a plurality of second transistors being formed at the second region of the semiconductor layer 10. Each of the first and second transistors consists of gate electrodes 20A and 20B, channel formation regions 23A and 23B, and source/drain regions 22A and 22B, and the height of the gate electrode 20A in the first transistor is lower than that of the gate electrode 20B in the second transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same.

[0002]

2. Description of the Related Art To generate a high-resolution image in real time in a graphics LSI,
It is necessary to increase the bandwidth (bus width) between the memory and the pixel engine (constituted by a logic circuit) that generates the data to be finally displayed. Implemented by a logic LSI (for example, Nikkei Microdevice, April 1999
Monthly, p. 138). In particular, dynamic random access memory (DRAM) as embedded memory
Is advantageous to increase the capacity of the memory.

In order to achieve low power consumption and high speed of a transistor, a salicide (Self-Aligned Silic
ide) Technology and Dual Gate (Dual Gate, Dual W)
orkFunction Gate or surface channel type CMOS
(Also called FET) technology is often employed.

Here, the salicide technique refers to a technique in which a silicide layer is formed in a self-aligned manner on the top surface of a source / drain region and a gate electrode. Specifically, a gate electrode made of polysilicon is formed on a semiconductor substrate, and then,
After the source / drain regions are formed in the silicon semiconductor substrate, a refractory metal layer is formed on the entire surface and subjected to a heat treatment, whereby metal atoms constituting the refractory metal layer and atoms constituting the semiconductor substrate and the gate electrode (specifically, Specifically, it is a technique of forming a silicide layer by reacting with Si) and then removing an unreacted high melting point metal layer.

[0005] The dual gate technique is a technique in which a gate electrode of an n-channel MOS transistor is formed of a polysilicon layer containing an n-type impurity and a p-channel MOS transistor is formed.
By forming the gate electrode of the transistor from a polysilicon layer containing a p-type impurity,
This is a technique for forming a surface type channel also in a transistor.

A space between gate electrodes of a MOS transistor (hereinafter, sometimes referred to as a DRAM memory transistor) constituting a DRAM is limited by design rules.
Designed with values close to the minimum. When a contact plug is formed in the source / drain region, a technique of forming the contact plug in a self-aligned manner is generally used. Such a technique is called a self-aligned contact (SAC) technique. By the way, in order to apply the SAC technique, the gate electrode needs to have a multilayer structure of, for example, a conductive material layer and an insulating material layer also called an offset film made of silicon nitride (SiN). Further, in order to secure a distance between the gate electrode and the contact plug, it is necessary to provide a sidewall made of silicon nitride (SiN) on the side wall of the gate electrode. Specifically, the contact plug is formed by forming silicon oxide (Si) over the entire surface after a DRAM memory transistor is manufactured.
O ₂ ) is formed, and then the source /
An opening can be formed in a portion of the interlayer insulating layer located above the drain region, and a conductive material can be embedded in the opening. Even if an opening is also formed above the gate electrode due to so-called misalignment in the lithography method, silicon oxide (SiO ₂ ) and silicon nitride (SiO ₂ ) having an etching selectivity are formed on the top surface of the gate electrode. Since the insulating material layer made of SiN) is deposited and the sidewalls are formed, it is possible to prevent the occurrence of a phenomenon such as a short circuit between the contact hole and the gate electrode.

However, there is a technically difficult problem in mounting a large-capacity DRAM and a logic circuit together. That is, in order to form a large-capacity DRAM by miniaturizing the element, the wiring delay must not be increased.
Low resistance word line material is required. Further, since the word line also serves as the gate electrode of the DRAM memory transistor, it is required to have a heat resistance of about 1000 ° C. Furthermore, it is also required that the gate electrode does not deteriorate the characteristics of the DRAM memory transistor. From these demands, a polymetal structure in which a high melting point metal material layer made of tungsten (W) is laminated on a polysilicon layer as a material of a word line and a gate electrode in a DRAM memory transistor of the 0.13 μm generation is considered promising. . However, such a polymetal structure is
When applied to a logic circuit composed of MOS transistors, a problem arises in the current drive capability of a p-channel MOS transistor.

That is, the gate electrode of a p-channel MOS transistor has a polymetal structure in which a refractory metal material layer made of tungsten is laminated on a polysilicon layer in which boron as a p-type impurity is implanted at a high concentration. .
However, for such a polymetal structure, M
When heat treatment indispensable for manufacturing an OS transistor is performed, boron in the polysilicon layer diffuses into the silicon semiconductor substrate or the high-melting-point metal material layer, and the boron concentration in the polysilicon layer decreases. Such a decrease in the boron concentration causes an increase in the parasitic gate capacitance when a gate voltage is applied to the gate electrode, and reduces the effective gate insulating film capacitance. As a result, the channel carrier density induced when the gate voltage is applied is reduced, and the current driving capability of the p-channel MOS transistor is reduced.

Further, since the polysilicon layer containing the n-type impurity and the polysilicon layer containing the p-type impurity have different etching rates, a gate electrode for an n-channel MOS transistor having a desired shape is provided. It is difficult to simultaneously form a gate electrode for a p-channel MOS transistor having a shape, and the gate insulating film is becoming thinner, and the semiconductor substrate is damaged during etching for forming the gate electrode. There is a risk of doing so.

Hereinafter, an outline of a conventional semiconductor device manufacturing process will be described with reference to FIGS. 26 to 33 which are schematic partial sectional views of a silicon semiconductor substrate and the like. In the following description, it is assumed that the first transistor forms a logic circuit, and the second transistor forms a DRAM (more specifically, a DRAM memory transistor). Further, it is assumed that the first transistor is an n-channel transistor and a p-channel transistor, and the second transistor is an n-channel transistor. (A) of each drawing shows a manufacturing process of a p-channel first transistor, and (B) of each drawing shows a manufacturing process of an n-channel second transistor.

[Step-10] First, gate insulating films 12A and 12B are formed on a semiconductor substrate 10 made of a silicon semiconductor substrate having element isolation regions 11 formed thereon, and a gate electrode is formed on the gate insulating films 12A and 12B. Polysilicon layer 13 is deposited. Next, impurities for controlling the work function of the gate electrode are introduced into the polysilicon layer 13 (see FIG. 26). Specifically, phosphorus which is an n-type impurity is ion-implanted into a polysilicon layer in a region where an n-channel first transistor and an n-channel second transistor are to be formed. On the other hand, boron, which is a p-type impurity, is ion-implanted into a polysilicon layer in a region where a p-channel first transistor is to be formed. Thereafter, a refractory metal material layer 14 made of tungsten is formed on the entire surface to reduce the resistance of the gate electrode, and silicon nitride (SiN) is used to protect the gate electrode when a contact plug is formed in the source / drain region. ) Made of the high melting point metal material layer 1
4 (see FIG. 27).

High melting point metal material layer 14 and insulating material layer 15
Therefore, it is necessary to introduce impurities into the polysilicon layer 13 before forming the refractory metal material layer 14 as shown in FIG. That is, the polysilicon layer 13 passes through the refractory metal material layer 14 and the insulating material layer 15.
It is difficult to introduce impurities into the inside of the polysilicon layer 13 even if the impurities can be introduced.
Impurities are introduced into the semiconductor substrate 10 located below the semiconductor substrate 10. In addition, the amount of impurities introduced into the semiconductor substrate 10 at this time is not uniform. If impurities are introduced into the semiconductor substrate 10, the threshold voltage V _{th of the} transistor
Shifts from the design value, and the shift amount becomes non-uniform. As a result, the characteristics of the transistor deteriorate. For the above reasons, after introducing impurities, particularly boron, the high melting point metal material layer 14 and the insulating material layer 15 are deposited. The insulating material layer 15 made of silicon nitride (SiN) is deposited at a relatively high temperature. Therefore (at 700 ° C. or more), at this time, depending on the condition, there is a problem that boron which is easily thermally diffused diffuses into the semiconductor substrate 10 and the high melting point metal material layer 14.

[Step-20] Thereafter, the first transistor and the second transistor are patterned by patterning the insulating material layer 15, the refractory metal material layer 14, and the polysilicon layer 13 based on a lithography method and a dry etching method. Are formed (see FIG. 28). The polysilicon layer 13 containing an n-type impurity and the polysilicon layer 1 containing a p-type impurity
Since the etching rates of 3 are different, it is difficult to simultaneously form a gate electrode for an n-channel transistor having a desired shape and a gate electrode for a p-channel transistor having a desired shape.

[Step-30] Next, the gate electrode 20A,
Using 20B as an ion implantation mask, doping of impurities for forming source / drain regions 22B forming the second transistor, and LDD structure or extension region 21 forming the first transistor are performed.
Impurities for forming A are introduced (see FIG. 29). Specifically, arsenic, which is an n-type impurity, is ion-implanted into the semiconductor substrate 10 in a region where an n-channel first transistor is to be formed. The semiconductor substrate 10 is ion-implanted with phosphorus as an n-type impurity, and the region of the semiconductor substrate 10 where the p-channel first transistor is to be formed is
BF ₂ which is a p-type impurity is ion-implanted. Reference numeral 23B is a channel formation region.

[Step-40] Thereafter, an insulating layer 24 is formed on the entire surface by the CVD method. Next, while the region where the second transistor is to be formed is protected by the etching mask, the insulating layer 24 is dry-etched (etched back) to form a side wall on the side wall of the gate electrode 20A constituting the first transistor. Wall 224A
Is formed, the etching mask is removed (FIG. 30).
reference). Since the region where the second transistor is to be formed is protected by the etching mask, no damage occurs to the semiconductor substrate 10 in the region where the second transistor is to be formed. The insulating layer 24 is left on the top surface of the gate electrode 20B constituting the second transistor, and the insulating layer 24 is left on the side surface of the gate electrode 20B as a sidewall. Side wall 224
The insulating layer 24 constituting A is preferably made of silicon nitride (SiN) in order to protect the gate electrode at the time of forming a contact plug in the source / drain region, but is preferably made of silicon nitride (SiN). Since the deposition is performed at a relatively high temperature (700 ° C. or higher), there is a possibility that boron in the polysilicon layer 13 may diffuse into the semiconductor substrate 10 and the high melting point metal material layer 14 made of tungsten.

[Step-50] Next, the gate electrode 20A and the sidewall 224 constituting the first transistor
By using A as a mask, the source / drain region 2 is formed in the semiconductor substrate 10 in the region where the first transistor is to be formed.
Impurities for forming 2A are introduced (see FIG. 31). Specifically, an n-type impurity is ion-implanted into the semiconductor substrate 10 in the region where the n-channel first transistor is to be formed, and the semiconductor substrate 10 in the region where the p-channel first transistor is to be formed. Implants p-type impurities. After that, heat treatment for activating the introduced impurities is performed. The heat treatment at this time is performed by RTA of about 1000 ° C.
(Rapid Thermal Annealing) method. Reference numeral 23A is a channel formation region.

[Step-60] Subsequently, a refractory metal layer 25 is deposited on the entire surface (FIG. 32), and the silicide layer 26 is formed only on the source / drain region 22A constituting the first transistor based on the salicide technique. (Fig. 3
3).

[Step-70] After that, various semiconductor devices are completed by forming various wirings and capacitor portions constituting the DRAM based on a known method.

Incidentally, in an integrated circuit in which a large-capacity DRAM and a logic circuit are mixedly mounted, if both gate electrodes have a two-layer structure of a polysilicon layer and a silicide layer using salicide technology, the following problem occurs. . That is, ie, D
The data retention characteristic is degraded by a leak current caused by a junction generated between the source / drain region on the node side of the RAM memory transistor and the silicide layer. Also,
Generally, in a 0.25 μm generation DRAM, 256
In the DRAM of the 0.18 μm generation, 512 DRAM memory transistors are connected to one bit line, but occur between the source / drain region on the bit line side and the silicide layer. The increase in the leakage current to the bit line as the sum of the leakage currents caused by the junction causes a reduction or reduction of a low voltage margin due to a reduction in the amplitude of a signal flowing through the bit line, and a reduction in data retention characteristics (for example, refresh characteristics). .

[0020]

SUMMARY OF THE INVENTION In a logic circuit,
In order to reduce the parasitic resistance, it is necessary to form the silicide layer 26 in the source / drain region 22A constituting the first transistor. Incidentally, the sheet resistance of the silicide layer 26 is determined by the thickness of the high melting point metal layer 25 to be deposited, and the sheet resistance becomes lower as the thickness is increased. on the other hand,
Source / gate between gate electrode 20A and gate electrode 20A
Refractory metal layer 25 that can be deposited on drain region 22A
Is determined by an aspect ratio (gate electrode height / gate electrode interval) determined by the distance between the gate electrodes 20A and the height of the gate electrode 20A. That is, the deposition thickness of the refractory metal layer 25 in the region having a large aspect ratio is smaller than that in the region having a small aspect ratio (see reference numeral 25 'in FIG. 32), and as a result, the obtained silicide layer is obtained. The thickness of 26 is also reduced (see reference numeral 26 'in FIG. 33). The upper limit of the thickness of the refractory metal layer 25 to be deposited (the thickness of the refractory metal layer 25 formed in a region having a small aspect ratio) is:
Since it is determined based on the thickness of the source / drain region 22A that does not increase the junction leakage, the sheet resistance of the silicide layer 26 in the region having a large aspect ratio increases to a level that cannot be ignored. The silicide layer 2 to be formed
The thickness of 6 is proportional to the thickness of the deposited refractory metal layer 25. The sheet resistance of the source / drain region 22A is inversely proportional to the thickness of the formed silicide layer 26. On the other hand, when the thickness of the refractory metal layer 25 is increased, the thickness of the formed silicide layer 26 is also increased, and the junction leakage of the source / drain region 22A increases. Therefore, the source /
The thickness of the silicide layer 26 is determined in consideration of the sheet resistance of the drain region 22A and the junction leak of the source / drain region 22A.

In the prior art, in [Step-60], the gate electrode 20 constituting the first transistor is formed.
A also has a structure in which a polysilicon layer 13, a high-melting metal material layer 14, and an insulating material layer 15 are laminated, substantially in the same manner as the second transistor. Therefore, the structure is such that the height of the gate electrode 20A constituting the first transistor is high.
Therefore, in a logic circuit in which a plurality of first transistors are formed, a region where the distance between the gate electrodes 20A constituting the first transistor is small is a high melting point metal in [Step-60]. When the layer 25 is deposited, the structure has a large aspect ratio. As a result, the thickness of the refractory metal layer 25 deposited in the region where the distance between the gate electrodes 20A is small is smaller than that in the region where the distance is large (FIG. 3).
2 reference number 25 ').

Accordingly, an object of the present invention is to provide, for example, a DRAM having a large capacity and a logic circuit on a single chip.
The resistance of the gate electrode (word line) of the RAM memory transistor can be reduced, and the current driving capability of a logic circuit composed of CMOS transistors, particularly a p-channel MOS transistor, can be prevented from lowering. An object of the present invention is to provide an integrated circuit capable of reducing the parasitic resistance of a CMOS transistor constituting a logic circuit, and a method for manufacturing the same.

[0023]

In order to achieve the above object, a semiconductor device according to the present invention comprises a plurality of first transistors formed in a first region of a semiconductor layer and a second transistor formed in a first region of the semiconductor layer. A semiconductor device including a plurality of second transistors formed in a region, wherein each of the first and second transistors includes a gate electrode, a channel formation region, and a source / drain region; The height of the gate electrode in the first transistor is lower than the height of the gate electrode in the second transistor.

The gate electrode may be composed of only one or two or more conductive material layers.
It may be composed of a layer or two or more conductive material layers and one or two or more insulating material layers. The height of the gate electrode means the thickness of one conductive material layer when the gate electrode is formed of one conductive material layer, and the thickness of two or more conductive material layers when the gate electrode is formed of one or more conductive material layers. The total thickness of two or more conductive material layers, one layer or two or more conductive material layers, and one or two or more insulating material layers; It means the total thickness of the material layer.

The first object of the present invention for achieving the above object is as follows.
The method for manufacturing a semiconductor device according to the aspect is a method for manufacturing the first transistor in the semiconductor device of the present invention. That is, in the method for manufacturing a semiconductor device according to the first aspect of the present invention, the plurality of first transistors formed in the first region of the semiconductor layer and the plurality of first transistors formed in the second region of the semiconductor layer A plurality of second transistors, each of the first and second transistors having a gate electrode,
A method for manufacturing a first transistor in a semiconductor device including a channel formation region and a source / drain region, comprising: (A) forming a gate insulating film on a surface of a semiconductor layer; Forming a layer (polysilicon layer or amorphous silicon layer), then forming a cap layer on the silicon layer, and then patterning the cap layer and the silicon layer; and (B) the patterned silicon layer and the cap layer Forming a sidewall on the side wall of the laminate comprising: (C) removing the cap layer; and (D) introducing a impurity into the silicon layer and the semiconductor layer to form a gate comprising a silicon layer patterned. (E) forming an electrode and, at the same time, forming source / drain regions in the semiconductor layer;
A step of forming a silicide layer on a portion of the semiconductor layer forming the source / drain regions and on a surface of the silicon layer forming the gate electrode.

The gate electrode of the transistor manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention is formed from two layers, a silicon layer doped with impurities and a silicide layer formed thereon from below. Be composed.

The second object of the present invention to achieve the above object.
The method for manufacturing a semiconductor device according to the aspect is a method for manufacturing the semiconductor device of the present invention. That is, the first and second transistors include a plurality of first transistors formed in a first region of the semiconductor layer and a plurality of second transistors formed in a second region of the semiconductor layer. Each of the transistors is a method for manufacturing a semiconductor device including a gate electrode, a channel formation region, and a source / drain region, wherein (A) after forming a gate insulating film on a surface of a semiconductor layer, polycrystalline or amorphous. Quality silicon layer (polysilicon layer or amorphous silicon layer), and then
At least a step of introducing an impurity into a silicon layer in a region where a second transistor is to be formed, and (B) a step of sequentially stacking a high melting point metal material layer and an insulating material layer on the silicon layer, Removing the insulating material layer and the refractory metal material layer in the region where the second transistor is to be formed, and (C) removing the cap layer in the region where the second transistor is to be formed after forming the cap layer on the entire surface. (D) forming a gate electrode constituting the second transistor by patterning the insulating material layer, the refractory metal material layer and the silicon layer, and simultaneously patterning the cap layer and the silicon layer; A) forming a source / drain region forming the second transistor by introducing an impurity into a semiconductor layer in a region where the second transistor is to be formed; (G) a step of covering a region where a second transistor is to be formed with an insulating layer, and forming sidewalls on side walls of the stacked body including the patterned silicon layer and the cap layer; Removing the cap layer; and (H) introducing an impurity into the semiconductor layer and the silicon layer in a region where the first transistor is to be formed, so that the source / source constituting the first transistor is formed.
Forming a drain region and a gate electrode; and (I)
A step of forming a silicide layer on a portion of a semiconductor layer forming source / drain regions of the first transistor and a surface of a silicon layer forming a gate electrode of the first transistor.

The third object of the present invention for achieving the above object is as follows.
The method for manufacturing a semiconductor device according to the aspect is also a method for manufacturing the semiconductor device of the present invention. The method for manufacturing a semiconductor device according to the third aspect is characterized in that a cap layer is not formed.
This is different from the semiconductor device manufacturing method according to the second aspect. That is, the first and second transistors include a plurality of first transistors formed in a first region of the semiconductor layer and a plurality of second transistors formed in a second region of the semiconductor layer. Each of the transistors is a method for manufacturing a semiconductor device including a gate electrode, a channel formation region, and a source / drain region, wherein (A) after forming a gate insulating film on a surface of a semiconductor layer, polycrystalline or amorphous. Forming a quality silicon layer (polysilicon layer or amorphous silicon layer), and then introducing an impurity into at least the silicon layer in a region where the second transistor is to be formed;
(B) a step of sequentially stacking a high melting point metal material layer and an insulating material layer on the silicon layer, and then removing the insulating material layer and the high melting point metal material layer in a region where the first transistor is to be formed; C) a step of forming a gate electrode constituting the second transistor by patterning the insulating material layer, the refractory metal material layer, and the silicon layer, and simultaneously patterning the silicon layer; and (D) the second transistor. Forming source / drain regions constituting the second transistor by introducing impurities into a semiconductor layer in a region where a second transistor is to be formed, and (E) covering a region where a second transistor is to be formed with an insulating layer. Forming a sidewall on the side wall of the patterned silicon layer; and (F) forming a semiconductor layer and a silicon layer in a region where the first transistor is to be formed. Forming a source / drain region and a gate electrode constituting the first transistor by introducing an impurity into the transistor layer; (G) a portion of a semiconductor layer constituting a source / drain region of the first transistor; And forming a silicide layer on a surface of a silicon layer forming a gate electrode of the first transistor;
Characterized by comprising:

In the method for manufacturing a semiconductor device according to the second or third aspect of the present invention, the step (A)
Then, "to introduce an impurity into the silicon layer in the region where the second transistor is to be formed" at least "means depending on the type of the impurity to be introduced (more specifically, when introducing an n-type impurity). This means that impurities may be introduced not only into the silicon layer in the region where the second transistor is to be formed but also into the silicon layer in the region where the first transistor is to be formed.

The gate electrode of the first transistor manufactured by the method for manufacturing a semiconductor device according to the second or third aspect of the present invention is formed from below on a silicon layer into which an impurity is introduced, and on the silicon layer. Composed of two silicide layers. The gate electrode of the second transistor includes, from the bottom, a silicon layer into which impurities are introduced, and a refractory metal material layer, an insulating material layer, and an insulating layer formed thereon. In the present invention, the height of the gate electrode of the first transistor is lower than the height of the gate electrode of the second transistor. Specifically, the gate electrode of the first transistor and the gate electrode of the second transistor are different. The electrode has a different cross-sectional structure.

In the method of manufacturing the semiconductor device of the present invention or the semiconductor device according to the first to third aspects of the present invention (hereinafter, these may be collectively simply referred to as the present invention). May have a structure in which a first transistor forms a logic circuit, and a second transistor forms a dynamic random access memory (DRAM).

In the semiconductor device of the present invention, the first transistor may have a structure in which a silicide layer is formed in the source / drain region. The gate electrode of the first transistor has a two-layer structure of a polycrystalline or amorphous silicon layer (a polysilicon layer or an amorphous silicon layer) and a silicide layer formed on the silicon layer (the gate electrode). The height is the total thickness of the silicon layer and the silicide layer), and the gate electrode in the second transistor is at least a polycrystalline or amorphous silicon layer (polysilicon layer or amorphous silicon layer). A refractory metal material layer formed on the
Further, it is preferable that the insulating material layer has a three-layer structure (the height of the gate electrode is the total thickness of the silicon layer, the high melting point metal material layer, and the insulating material layer) formed on the high melting point metal material layer. . Note that a gate electrode in the second transistor includes a silicon layer, a high melting point metal material layer formed on the silicon layer, an insulating material layer formed on the high melting point metal material layer, the insulating material layer, and the gate. A four-layer structure of the insulating layer formed on the side wall of the electrode (the height of the gate electrode is the total thickness of the silicon layer, the refractory metal material layer, the insulating material layer, and the insulating layer) can also be employed.

In the present invention, a tungsten (W) layer or a tungsten silicide layer can be exemplified as the refractory metal material layer constituting the gate electrode. Further, in order to prevent a reaction between silicon atoms constituting the silicon layer and metal atoms constituting the high melting point metal material layer between the silicon layer and the high melting point metal material layer, for example, WN, Ti
It is preferable to form a reaction prevention layer made of various metal nitrides such as N, ZrN, and HfN.

The insulating material forming the insulating material layer is an insulating material having an etching selectivity with respect to the insulating material forming the interlayer insulating layer formed on the entire surface after forming the first transistor and the second transistor. Preferably, the material is a material. When the interlayer insulating layer is made of, for example, a silicon oxide-based material, the insulating material layer is preferably made of a silicon nitride (SiN) layer.

The material forming the sidewall or the insulating layer is preferably an insulating material having an etching selectivity between the insulating material forming the interlayer insulating layer and the semiconductor layer, such as silicon nitride (SiN) or nitride. Silicon (S
An example is a two-layer structure of an iN) layer and a silicon oxide (SiO ₂ ) layer.

The gate insulating film can be formed, for example, by oxidizing the surface of the semiconductor layer by a wet or dry thermal oxidation method. After the surface of the semiconductor layer is thermally oxidized, the surface is subjected to nitriding treatment, and silicon oxynitride (Si
ON) and two layers of silicon oxide (SiO ₂ ) or two layers of silicon nitride (SiN) and silicon oxide (SiO ₂ ).
It may be a gate insulating film composed of layers.

The material forming the cap layer is preferably made of a material having an etching selectivity between the material forming the sidewall and the semiconductor layer. For example,
TiN, BPSG, PSG, SOG, BSG, AsS
G, PbSG and SbSG can be mentioned.

The silicide layer is formed by forming a high-melting-point metal layer on the entire surface and then performing a heat treatment so that the metal atoms forming the high-melting-point metal layer and the atoms forming the semiconductor layer or the gate electrode (specifically, Si ) To form a silicide layer and then remove the unreacted refractory metal layer based on a salicide technique. Here, the refractory metal layer is made of, for example, cobalt (Co), nickel (Ni), platinum (Pt), titanium (Ti), or Ta.
(Tantalum), Mo (molybdenum), tungsten (W), and palladium (Pd).

In the present invention, as a semiconductor layer, a silicon semiconductor substrate, a substrate on which silicon or Si—Ge mixed crystal is epitaxially grown on spinel, a substrate on which sapphire is epitaxially grown with silicon or Si—Ge mixed crystal, insulation, A substrate obtained by melting and recrystallizing polycrystalline silicon on a film can be exemplified. As the silicon semiconductor substrate, an n-type silicon semiconductor substrate doped with an n-type impurity or a p-type silicon semiconductor substrate doped with a p-type impurity can be used.

Further, as a semiconductor layer, SOI (Semico)
nductor On Insulator) substrate can also be used. S
As a method of manufacturing an OI substrate, (1) After bonding a semiconductor substrate and a support substrate via an insulating layer, the semiconductor substrate is ground and polished from the back surface, so that a support made of the support substrate, an insulating layer, grinding,
A substrate bonding method for obtaining a semiconductor layer composed of a polished semiconductor substrate. (2) After an insulating layer is formed on the semiconductor substrate, hydrogen ions are ion-implanted into the semiconductor substrate to form a peeling layer inside the semiconductor substrate. The semiconductor substrate and the supporting substrate are attached to each other with an insulating layer interposed therebetween, and then the semiconductor substrate is separated (cleaved) from the separation layer by performing a heat treatment, and the remaining semiconductor substrate is ground and polished from the back surface to thereby form the supporting substrate. (3) Obtaining a semiconductor layer composed of a support, an insulating layer, and a semiconductor substrate after grinding and polishing. (3) Oxygen ions are implanted into the semiconductor substrate, and then heat treatment is performed. Forming an insulating layer inside a semiconductor substrate, a support formed of part of the semiconductor substrate below the insulating layer, and a semiconductor layer formed of part of the semiconductor substrate on the insulating layer, Re can each SIMOX (Separation b
y IMplanted OXygen) method (4) A single-crystal semiconductor layer is formed in a gas phase or a solid phase on an insulating layer formed on a semiconductor substrate corresponding to a support, whereby a support made of a semiconductor substrate and an insulating layer are formed. And (5) forming an insulating layer by partially making the surface of the semiconductor substrate porous by anodic oxidation, thereby forming a portion of the semiconductor substrate below the insulating layer. And a method of obtaining a semiconductor layer comprising a part of a semiconductor substrate on an insulating layer. Here, a semiconductor device having a semiconductor layer is formed. The insulating layer in the description of the SOI substrate is different from the insulating layer in the method for manufacturing a semiconductor device of the present invention.

When an SOI substrate is used, an element isolation region can be formed by the following method. (A) forming a pad oxide film and a silicon nitride film on a semiconductor layer and patterning the silicon nitride film and the pad oxide film to form a mask for forming an element isolation region; (B) forming a trench in a semiconductor layer by patterning the semiconductor layer, and then filling the trench with an insulating material, so-called STI (C) When preparing a substrate based on the above method (1) or (2), a trench is formed in a semiconductor substrate in advance, the inside of the trench is filled with an insulating layer, and then the entire surface is prepared. an interlayer film (e.g., SiO ₂ film, a film having a laminated structure of SiO ₂ film and polysilicon film) after forming the, with such a semiconductor substrate supported A substrate bonding method and an STI method, in which a substrate is bonded through the interlayer film, and a semiconductor substrate is ground and polished from the back surface to obtain a support composed of a support substrate, an insulating layer, and a semiconductor layer composed of a semiconductor substrate. (D) Mesa-type element isolation region forming method of forming an element isolation region by exposing the insulating layer by removing a semiconductor layer on the insulating layer

The semiconductor device of the present invention or the second device of the present invention
In the semiconductor device manufacturing method according to the third and third aspects, the height of the gate electrode in the first transistor is lower than the height of the gate electrode in the second transistor. Therefore, the difference between the maximum value and the minimum value of the aspect ratio determined by the distance (interval) between the gate electrodes and the height of the gate electrodes in the adjacent first transistors can be reduced, so that the first transistor is formed. The difference between the maximum value and the minimum value of the thickness of the silicide layer finally formed in the source / drain regions can be reduced.

In the method of manufacturing a semiconductor device according to the first to third aspects of the present invention, the gate electrode is formed by introducing impurities into the patterned and exposed silicon layer. The patterning of the silicon layer becomes difficult due to the difference in the etching rate depending on the type (n-type, p-type) of the impurity introduced into the silicon layer, and the problem that the impurity contained in the silicon layer diffuses. It is possible to avoid.

[0044]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings based on embodiments of the present invention (hereinafter, abbreviated as embodiments). (A) of each figure shows a manufacturing process of the p-channel type first transistor, and (B) of each figure shows
3A to 3E illustrate a manufacturing process of an n-channel second transistor.

Embodiment 1 Embodiment 1 relates to a semiconductor device of the present invention and a method of manufacturing a semiconductor device according to the first and second aspects of the present invention.

FIG. 12 is a schematic partial cross-sectional view of the semiconductor device according to the first embodiment.
A plurality of first transistors formed in a first region of
And a semiconductor device including a plurality of second transistors formed in a second region of the semiconductor substrate 10.
Note that a logic circuit is constituted by the first transistor,
, A dynamic random access memory (more specifically, a DRAM memory transistor) is formed. Here, the first transistor is an n-channel transistor and a p-channel transistor, and the second transistor is an n-channel transistor. That is, a plurality of n-channel first transistors and a plurality of p-channel second transistors which form a logic circuit are provided in the first region, and a DRAM is formed in the second region. A plurality of n-channel second transistors are provided.

Each of the first and second transistors has a gate electrode 20A, 20B and a channel forming region 23.
A, 23B and source / drain regions 22A, 22
B. Then, the height of the gate electrode 20A in the first transistor is lower than the height of the gate electrode 20B in the second transistor. The gate electrode 20A in the first transistor has a two-layer structure of a polycrystalline silicon layer (polysilicon layer 13) into which impurities are introduced, and a silicide layer 26 formed on the polysilicon layer 13. On the other hand, in the first embodiment, the gate electrode 20B of the second transistor is formed of a polycrystalline silicon layer (polysilicon layer 13) into which impurities are introduced and tungsten (W) formed on the polysilicon layer 13. It has a four-layer structure of a high melting point metal material layer 14, an insulating material layer 15 formed on the high melting point metal material layer 14, and an insulating layer 24 formed on the insulating material layer 15. The insulating layer 2
Reference numeral 4 covers the side wall of the gate electrode 20B. The height of the gate electrode 20A in the first transistor is the total thickness of the polysilicon layer 13 and the silicide layer 26. The height of the gate electrode 20B in the second transistor is the total thickness of the polysilicon layer 13, the refractory metal material layer 14, the insulating material layer 15, and the insulating layer 24. The source / drain region 22A of the first transistor has:
A silicide layer 26 is formed, and a gate electrode 20A is formed.
A sidewall 24A is formed on the side wall of the. In the figure, reference numeral 11 indicates an element isolation region, and reference numeral 12
A and 12B are gate insulating films.

Hereinafter, a method for manufacturing a semiconductor device according to the first embodiment will be described with reference to FIGS. 1 to 20 which are schematic partial cross-sectional views of a semiconductor substrate and the like.

[Step-100] First, after forming gate insulating films 12A and 12B on the surface of a semiconductor substrate 10 composed of a silicon semiconductor substrate as a semiconductor layer, a polysilicon layer 13 is formed. The impurity is introduced into the polysilicon layer 13 in the region where the transistor is to be formed.

Specifically, first, an element isolation region 11 is formed in a predetermined region of a semiconductor substrate 10 made of a p-type silicon semiconductor substrate. The structure of the element isolation region 11 may have a shallow trench structure as shown in FIG.
It may have a LOCOS structure or a combination of a shallow trench structure and a LOCOS structure. Thereafter, a p-type well is formed on the semiconductor substrate 10 in a region where the n-channel first transistor constituting the logic circuit is to be formed, and an n-type well is formed on the semiconductor substrate 10 in a region where the p-channel first transistor is to be formed. Form wells. Also, D
An n-type well is formed in the semiconductor substrate 10 in a region where an n-channel type second transistor constituting the RAM is to be formed, and a p-type well is formed in the n-type well (that is, a p-type well is formed).
Forming a twin-well structure). Semiconductor substrate 10 in a region where a first transistor constituting a logic circuit is to be formed
The impurity profile of the semiconductor substrate 10 in the region where the second transistor forming the DRAM is to be formed may be the same or different. The well can be formed by, for example, an ion implantation method. In order to form an n-type well, phosphorus (P) may be ion-implanted at an acceleration energy of about 500 keV. On the other hand, in order to form a p-type well, boron (B) may be ion-implanted at an acceleration energy of about 250 keV. Illustration of each well is omitted. In the punch-through stop ion implantation in the n-type well, phosphorus (P) may be implanted at an acceleration energy of about 300 keV. On the other hand, in the punch-through stop ion implantation in the p-type well, boron (B) may be implanted with an acceleration energy of about 100 keV. Further, in the ion implantation for adjusting the threshold voltage _Vth of the n-channel transistor, boron (B) may be implanted at an acceleration energy of about 10 keV. On the other hand, the threshold voltage V _th of the p-channel transistor
In ion implantation for adjustment, arsenic (As) is
Ion implantation may be performed at an acceleration energy of about 0 keV. The implantation dose may be on the order of 1 × 10 ¹² / cm ² .

Thereafter, the surface of the semiconductor substrate 10 is
For example, the gate insulating films 12A and 12B having a thickness of 2.5 nm are thermally
It is formed by an oxidation method. Should form the first transistor
Thickness of gate insulating film 12A in semiconductor substrate 10 in the region
And a semiconductor substrate in a region where a second transistor is to be formed.
The thickness of the gate insulating film 12B on the plate 10 is the same.
Or the former may be thinner than the latter
Is also good. Prevents penetration of boron into semiconductor substrate 10
For this purpose, silicon oxide (SiO 2) _Two) Or
The surface of the gate insulating film may be subjected to a nitriding treatment.
Next, impurities are not contained on the entire surface by the CVD method.
A polysilicon layer 13 having a thickness of about 0.1 μm is formed.

Next, an n-type impurity is introduced by ion implantation into the polysilicon layer 13 in the region where the second transistor is to be formed and the polysilicon layer 13 in the region where the n-channel type first transistor is to be formed. I do. For example, phosphorus (P) may be ion-implanted at an acceleration energy of 10 keV, and the implantation amount may be on the order of 1 × 10 ¹⁵ / cm ² (see FIG. 1). At this stage, no impurity is introduced into the polysilicon layer 13 in a region where the p-channel first transistor is to be formed.

[Step-110] After that, a high melting point metal material layer 14 and an insulating material layer 15 are sequentially laminated on the polysilicon layer 13, and then the insulating material layer 15 and the high The melting point metal material layer 14 is removed. Specifically, a reaction prevention layer (not shown) made of a tungsten nitride film is formed on the polysilicon layer 13, and a refractory metal material layer 14 made of tungsten, and an insulating material layer made of silicon nitride (SiN) are further formed. 15 are formed (see FIG. 2). The thickness of the reaction preventing layer is 5 nm, the thickness of the refractory metal material layer 14 made of tungsten is 50 nm, and the thickness of the insulating material layer 15 made of silicon nitride (SiN) is 0.15 μm. Since the polysilicon layer 13 does not contain boron, which is a p-type impurity, diffusion of boron from the polysilicon layer 13 does not occur.

Next, a resist layer (not shown) is formed on the insulating material layer 15 in a region where the second transistor is to be formed by lithography, and the resist layer is used as an etching mask to form the first transistor. Material layer 15 and high melting point metal material layer 14 in the region where
After removing the (reaction preventing layer in Embodiment 1) by dry etching or wet etching, the resist layer is removed (see FIG. 3).

[Step-120] Thereafter, a cap layer 16 made of titanium nitride (TiN) is formed on the entire surface by sputtering (see FIG. 4). The thickness of the cap layer 16 is, for example, 0.1 μm. Next, the cap layer 16 in a region where the second transistor is to be formed is removed (see FIG. 5). Specifically, a resist layer (not shown) is formed on the cap layer 16 in a region where the first transistor is to be formed based on a lithography method, and the second transistor is formed using the resist layer as an etching mask. After the cap layer 16 in the region to be removed is removed by dry etching or wet etching, the resist layer is removed.

[Step-130] Next, the insulating material layer 15,
The gate electrode 20B constituting the second transistor is formed by patterning the refractory metal material layer 14 and the silicon layer 13, and the cap layer 16 and the silicon layer 13 are also patterned (see FIG. 6). Patterning can be performed based on a known method such as a lithography method and an etching method. Since the polysilicon layer 13 in the region where the p-channel first transistor is to be formed does not contain a p-type impurity, a polysilicon layer containing an n-type impurity and a polysilicon layer containing a p-type impurity are not included. Problems caused by different etching rates of layers can be avoided.

By the above steps, the first step in the method of manufacturing a semiconductor device according to the first aspect of the present invention,
A gate insulating film 1 is formed on a surface of a semiconductor substrate 10 which is a semiconductor layer.
After the formation of 2A, the polysilicon layer 13 is formed, and then the cap layer 16 is formed on the polysilicon layer 13, and the step of patterning the cap layer 16 and the polysilicon layer 13 is completed.

After that, the side surface of the polysilicon layer 13 may be oxidized to form a silicon oxide (SiO ₂ ) film on the side surface. As a result, the thicknesses of the gate insulating films 12A and 12B near the lower end of the side surface of the polysilicon layer 13 are slightly increased, so that the electric field at the lower end of the sidewall of the finally formed gate electrode can be reduced. The refresh characteristics of the DRAM can be improved, and the occurrence of leakage current due to the thinning of the gate insulating film can be prevented.

[Step-140] Then, source / drain regions 22B constituting the second transistor are formed by introducing an n-type impurity into the semiconductor substrate 10 in a region where the second transistor is to be formed (FIG. 7).

More specifically, ion implantation is performed using the gate electrode 20B constituting the second transistor as an ion implantation mask. For example, phosphorus (P) may be ion-implanted at an acceleration energy of 20 keV. In addition, the injection amount is 1 ×
It may be on the order of 10 ¹³ / cm ² .

In addition, an n-channel type first transistor
For the semiconductor substrate 10 in the region where the data is to be formed, for example,
For example, arsenic (As) is produced at an acceleration energy of 5 keV,
1 × 10 injection volume¹⁴/ Cm^TwoInjection as an order of
To form a p-channel first transistor
For example, BF _Two
At an acceleration energy of 4 keV and an injection amount of 1 × 10
¹⁴/ Cm^TwoBy performing ion implantation as an order of
Thus, the LDD structure or the extension region 21A
Can be formed. Note that the first transistor
If the short channel effect is significant,
Ion implantation may be performed. In addition, half ion implantation
An increase caused by crystal defects formed in the conductive substrate 10
Redistribution of impurities in the semiconductor substrate 10 becomes apparent due to rapid diffusion.
If significant, after this step, the recovery
Heat treatment (RTA treatment) may be performed.

[Step-150] Next, the region where the second transistor is to be formed is covered with the insulating layer 24, and the patterned polysilicon layer 13 and the cap layer 1 are also formed.
The sidewalls 24A are formed on the side walls of the laminate composed of No. 6 (see FIG. 8). Alternatively, the sidewall 24A is formed on the side wall of the stacked body composed of the patterned polysilicon layer 13 and the cap layer 16. In particular,
By a CVD method, a silicon nitride (Si
N) film, a silicon oxide (SiO ₂ ) film having a thickness of 40 nm is deposited on the entire surface, and then a region where a second transistor is to be formed is covered with a resist layer (not shown) based on lithography, and etched back. The silicon oxide film and the silicon nitride film in the region where the first transistor is to be formed are etched back by the method. The removal amount of the silicon oxide film by etch back is 40 nm, and the removal amount of the silicon nitride film by etch back is 30 nm. The region where the second transistor is to be formed is covered with an insulating layer 24 composed of two layers, a silicon nitride film and a silicon oxide film. On the other hand, the patterned polysilicon layer 13 and the cap layer 1
On the side wall of the stacked body composed of 6, a sidewall 24 </ b> A composed of two insulating layers 24 of a silicon nitride film and a silicon oxide film is formed.

[Step-160] Thereafter, the cap layer 16
Is removed (see FIG. 9). Specifically, the cap layer 16 made of titanium nitride on the polysilicon layer 13 constituting the first transistor is formed by, for example, a wet etching method using a mixed solution of ammonia, hydrogen peroxide and pure water, Selectively remove. As a result, the polysilicon layer 13 constituting the gate electrode of the first transistor is exposed.

[Step-170] Next, the first transistor
Semiconductor substrate 10 and polysilicon in a region where a
By introducing impurities into the layer 13, the first transistor
Source / drain regions 22A and gates
The gate electrode 20A is formed (see FIG. 10). In particular,
The pattern in the region where the first transistor is to be formed
Polysilicon layer 13 and sidewall 24
Ion implantation is performed using A as an ion implantation mask. n
As for the channel-type first transistor, arsenic (A
s) is implanted with an acceleration energy of 40 keV,
1 × 10^Fifteen/ Cm^TwoThe order should be. one
On the other hand, for the p-channel type first transistor, B
F _TwoIs implanted at an acceleration energy of 20 keV,
1 × 10^Fifteen/ Cm^TwoThe order should be. Change
In addition, activation annealing of these ion-implanted impurities
I do. The activation annealing is performed, for example, by RTA.
1000 ° C, 10 seconds
You.

[Step-180] Thereafter, the first transistor
Semiconductor substrate forming source / drain region 22A of the star
Part of plate 10 and gate electrode of first transistor
The surface of the polysilicon layer 13 constituting 20A
The silicide layer 26 is formed on the basis of the id technology. There
Is a semiconductor substrate forming the source / drain region 22A.
Plate 10 and the gate electrode 20A.
Forming a silicide layer 26 on the surface of the silicon layer 13
You. Specifically, for example, it is made of cobalt (Co),
The refractory metal layer 25 having a thickness of about 10 nm is entirely formed by sputtering.
After forming a film on the surface (see FIG. 11), N _Two100% atmosphere
Is N_Two/ Ar atmosphere (atmospheric pressure), 550 ° C, 30
Heat treatment is performed based on the RTA method under the condition of seconds. By this
And the Co atoms, the semiconductor substrate 10 and the polysilicon layer 13
Reacts with the Si atoms that make up cobalt silicide
(CoSi_Two) Layer 26 is formed. Side wall 2
4A or a high melting point metal on the element isolation region 11 and the insulating layer 24
Layer 25 is unreacted and remains intact. Then, with sulfuric acid
Unreacted high melting point metal in mixed solution of hydrogen peroxide and pure water
Layer 25 is removed and again N 2_Two100% atmosphere or N_Two/ A
r atmosphere (atmospheric pressure) at 800 ° C for 30 seconds
Heat treatment is performed based on the RTA method (see FIG. 12). to this
Therefore, the resistance of the cobalt silicide layer 26 can be reduced.
Can be. Note that the source constituting the second transistor
/ Drain region 22B is covered with insulating layer 24
Then, a silicide layer is formed in the source / drain region 22B.
Is not formed.

The gate electrode 20A constituting the first transistor is composed of a polysilicon layer 13 doped with impurities and a silicide layer 26 formed thereon from below, from the bottom. The height of the gate electrode 20A constituting the first transistor is about 0.1 μm. On the other hand, the gate electrode 20B of the second transistor comprises, from below, a polysilicon layer 13 having a thickness of about 0.1 μm into which an impurity is introduced, and a refractory metal material layer having a thickness of about 0.05 μm formed thereon. 14, an insulating material layer 15 having a thickness of about 0.15 μm, and an insulating layer 24 having a thickness of about 0.07 μm. Therefore, the height of the gate electrode 20B constituting the second transistor is about 0.37 μm. As described above, since the height of the gate electrode 20A in the first transistor is lower than the height of the gate electrode 20B in the second transistor, the aspect ratio of the first transistor ((the height of the gate electrode / the height of the gate electrode) The difference between the maximum value and the minimum value of the interval can be reduced, and the difference between the maximum value and the minimum value of the thickness of the silicide layer 26 formed in the source / drain region forming the first transistor is reduced. Can be.

[Step-190] After that, an interlayer insulating layer, a contact plug, a DRAM capacitor, a wiring, and the like are formed.
Complete the DRAM embedded logic LSI. Specifically, for example, a first interlayer insulating layer 31 made of silicon oxide (SiO ₂ ) is formed on the entire surface by a CVD method, and the first interlayer insulating layer 31 is formed by a chemical mechanical polishing method (CMP method) or the like. 3
1 is performed. Next, a hard mask layer 32 made of polysilicon is formed on the entire surface by a CVD method.
Thereafter, an opening is formed in the hard mask layer 32 based on a lithography method and a dry etching method. Then
A polysilicon layer is formed on the hard mask layer 32 including the inside of the opening, and the polysilicon layer is etched back to form an opening diameter reducing mask 33 in the opening. FIG. 13 schematically shows the area of the DRAM in this state. In the region of the logic circuit, the interlayer insulating layer 31 and the hard mask layer 32 are formed, but the opening and the opening diameter reducing mask 33 are not formed. The diameter of the opening reduced by the opening diameter reducing mask 33 is set to about 80 nm. That is, the diameter of the bottom of the opening is about 80 nm. In some cases, a mask layer made of a resist material may be formed without forming the hard mask layer 32, and an opening may be formed in the first interlayer insulating layer 31 using the mask layer as an etching mask. .

Then, using the hard mask layer 32 and the opening diameter reducing mask 33 as an etching mask,
The opening 34 reaching the source / drain region 22B constituting the second transistor based on the dry etching method.
Is formed on the first insulating material layer 31. Since the insulating layer 24 is formed, the gate electrode 20B can be prevented from being exposed in the opening 34, and the occurrence of a short circuit between the contact plug to be formed next and the gate electrode 20B can be reliably prevented. . After that, the source / drain regions 2 constituting the second transistor exposed at the bottom of the opening 34
An impurity-containing region is formed by ion-implanting an n-type impurity into 2B (that is, contact compensation ion implantation is performed), and a contact resistance between the contact plug formed in the opening 34 and the source / drain region 22B is formed. Is preferably reduced.

Thereafter, a silicon layer made of polysilicon or amorphous silicon and containing impurities is deposited on the entire surface including the inside of the opening 34, and the silicon layer, the hard mask layer 32 and the opening are formed by an etch-back method or a CMP method. The diameter reducing mask 33 is removed, and the inside of the opening 34 is filled with a silicon layer containing an impurity as a conductive material, thereby completing a contact plug 35 (a contact plug for a bit line and a contact plug for a node).

Thereafter, a heat treatment at 800 to 850 ° C. is performed by the RTA method for activating the impurities in the impurity-containing region and the impurities in the contact plug 35.
Although this heat treatment is a process unnecessary for the manufacturing process of the first transistor included in the logic circuit, it is a short-time heat treatment such that the influence on the characteristics of the transistor can be ignored.

Next, on the first interlayer insulating layer 31 including the top surface of the contact plug 35, the contact plug 35 is made of silicon oxide (SiO ₂ ) having a thickness of about 20 nm in order to electrically separate the bit line from the contact plug 35. A first insulating film 36 is formed. This state is shown in FIG. Note that the first insulating film 36 is formed on the interlayer insulating layer 31 also in the region of the logic circuit.

Next, the contact plug 35 for the bit line is formed.
The bit line 37 is formed on the first insulating film 36 including the upper portion (see FIG. 16). Specifically, an opening is formed in the first insulating film 36 on the contact plug 35 for the bit line,
Next, a titanium (Ti) layer having a thickness of 10 to 20 nm, a TiN layer having a thickness of about 20 nm, and a tungsten layer having a thickness of about 100 nm are sequentially formed by a sputtering method.
The TiN layer and the titanium layer may be patterned. In the figure, the bit line 37 is represented by one layer. With such a bit line configuration, the resistance of the bit line 37 can be reduced, and the bit line equalizing speed can be improved.
High-speed access can be realized. When the bit line 37 is formed, a local wiring of the first transistor included in the logic circuit can be formed at the same time. Other examples of the bit line configuration include a stacked configuration of a tungsten layer / TiN layer and a stacked configuration of a tungsten layer / WN layer / polysilicon layer.

Thereafter, a second interlayer insulating layer 40 is formed on the entire surface, an opening is formed in the second interlayer insulating layer 40 above the contact plug 35 for the node, and the opening is buried with tungsten to form a node. The contact plug 41 is formed. Specifically, an opening having a diameter of about 100 nm is formed in the second interlayer insulating layer 40 by a super-resolution method or a combination of the above-described hard mask layer and the mask for reducing the diameter of the opening. After a titanium layer and a TiN layer are formed on the second interlayer insulating layer including by sputtering, a tungsten layer is formed by CVD over the entire surface including the inside of the opening.
Then, a tungsten layer on the second interlayer insulating layer 40, T
The node contact plug 41 can be obtained by selectively removing the iN layer and the titanium layer based on the etch-back method or the CMP method. In the drawing, the node contact plug 41 is represented by one layer.

Next, after a second insulating film 42 having a thickness of about 100 nm is formed on the second interlayer insulating layer 40 including the top surface of the node contact plug 41 (for the DRAM region, see FIG. 17). ), The source / drain region 22A of the first transistor that penetrates through the second insulating film 42, the second interlayer insulating layer 40, the first insulating film 36, and the first interlayer insulating layer 31, and forms a logic circuit. In addition, an opening 43 reaching the gate electrode 20A is provided (see FIG. 18). The gate electrode 2
The illustration of the opening reaching 0 A is omitted. Since the sidewalls 24A are formed, the occurrence of a short circuit between a contact plug to be formed next and the gate electrode 20A can be reliably prevented.

After that, a sintering process for introducing hydrogen into the source / drain regions 22A constituting the first transistor is performed. The sintering process can be a heat treatment in a hydrogen gas atmosphere at about 400 ° C.

When a capacitor constituting a DRAM is formed, a generally used nitride-based dielectric material requires a high-temperature process of about 700 to 800 ° C. As the capacitor, an MIM (Metal-Insulator-Metal) structure that can be formed by a low-temperature process of 600 ° C. or less can be applied. After that, a contact is made to the source / drain region of the first transistor constituting the logic circuit. When forming the plug, a heat treatment at about 650 ° C. is required to improve the characteristics of the barrier metal and the glue layer. However, when such a heat treatment at about 650 ° C. is performed, the characteristics of the capacitor having the MIM structure may be deteriorated. In addition, a metal oxide is generally used for a dielectric thin film constituting a capacitor having an MIM structure. However, such a dielectric thin film causes leakage due to oxygen vacancies and deteriorates its characteristics. It is not preferable to expose the dielectric thin film to the atmosphere. That is, the sintering process of introducing hydrogen into the source / drain regions of the first transistor included in the logic circuit after forming the MIM structure capacitor is a process that should be avoided as much as possible.

In the first embodiment, since the contact plug is formed in the source / drain region of the first transistor constituting the logic circuit before forming the capacitor, the above problem may occur. Absent.

Thereafter, an adhesion layer (not shown) made of TiN is formed on the second insulating film 42 including the inside of the opening 43 by a sputtering method, and is heated to about 650 ° C. for densification of the adhesion layer. Perform RTA processing. At this time, silicidation occurs in the connection boundary region between the node contact plug 41 made of tungsten and the node contact plug 35 made of silicon. As a result, good connection between the node contact plug 41 and the node contact plug 35 is obtained. Can be secured. Then, after forming a tungsten layer on the entire surface including the inside of the opening 43 by the CVD method,
The contact plug 44 can be obtained by selectively removing the tungsten layer and the TiN layer on the second insulating film 42 based on an etch-back method or a CMP method.
In the drawing, the contact plug 44 is represented by one layer.

Next, TiN / Al-Cu / TiN / Ti
The wiring 45 having a laminated structure (= 50/400/20/20 nm) is formed based on a sputtering method, a lithography method, and a dry etching method. Before the formation of the capacitor constituting the DRAM, the wiring 4
5, the wiring 45 and the contact plug 44 having high reliability can be easily obtained.
Note that the wiring 45 is represented by one layer. Thereafter, a third interlayer insulating layer 46 is formed on the entire surface (see FIG. 19). Since the wiring 45 is formed before the formation of the capacitor, the depth of the contact plug 44 does not become deeper to the left.

Next, a recess having a storage node shape is formed in third interlayer insulating layer 46 such that node contact plug 41 is exposed at the bottom thereof. Then, WN and T
Metals with excellent oxidation resistance, such as iN, or Ru or Ir
A thin film made of a metal or a metal oxide having an oxide such as an oxide is deposited on the third interlayer insulating layer 46 including the inside of the recess to a thickness of about 50 nm. Next, resist material or B
After the recess is filled with a material such as PSG or SOG that can be selectively removed from the third interlayer insulating layer 46, the thin film on the third interlayer insulating layer 46 is removed based on an etch-back method or a CMP method. By removing the material embedded in the recess, the storage node electrode 47 can be formed in the recess. Thereafter, a dielectric thin film 48 made of Ta ₂ O ₅ having a thickness of about 10 nm is formed on the third interlayer insulating layer 46 including the storage node electrode 47 in the concave portion.
The dielectric thin film 48 is irradiated with ultraviolet rays while being heated to 50 ° C., and then subjected to an annealing process in an ozone gas atmosphere for about 10 minutes. As a result, although the dielectric thin film 48 remains in an amorphous state, oxygen defects in the film are sufficiently eliminated, and residual carbon is also removed, so that a capacitor dielectric thin film having excellent film quality is obtained. After that, about 100n thickness
m TiN layer or tungsten layer is formed by a sputtering method.
The iN layer or the tungsten layer and the dielectric thin film 48 are patterned. Thus, a cell plate 49 made of a TiN layer or a tungsten layer can be obtained (see FIG. 20). There is no large step difference in the above capacitor forming process. The storage node electrode 47
Is provided for each second transistor, and the dielectric thin film 48 and the cell plate 49 are common to a plurality (or all) of the second transistors.

Thereafter, a fourth interlayer insulating layer is formed on the entire surface, an opening is formed in the fourth interlayer insulating layer above the cell plate 49 and the wiring 45, and the inside of the opening is filled with a conductive material to form a connection hole. To form After that, a wiring material layer is formed on the fourth interlayer insulating layer including on the connection hole, and the wiring material layer is patterned, whereby a second wiring can be formed. Since the capacitor structure is formed in the process between the formation of the wiring 45 and the second wiring, the depth of the contact plug for the second wiring is limited to the semiconductor device in which the conventional logic circuit and the DRAM are mounted. Can be made shallower than the depth of the contact plug.

(Embodiment 2) Embodiment 2 relates to a semiconductor device of the present invention and a method of manufacturing a semiconductor device according to the third aspect of the present invention.

FIG. 25 is a schematic partial cross-sectional view of the semiconductor device according to the second embodiment. The structure of the side wall 124A in the first transistor is the same as that of the semiconductor device described in the first embodiment. The semiconductor device has substantially the same structure except that the structure is slightly different from the structure of the sidewall 24A in the transistor, and thus a detailed description of the semiconductor device in the second embodiment is omitted.

A method of manufacturing a semiconductor device according to the second embodiment will be described below with reference to FIGS. 21 to 25 which are schematic partial cross-sectional views of a semiconductor substrate and the like. Is different from the method of manufacturing the semiconductor device of the first embodiment in that a cap layer is not formed.

[Step-200] First, as in [Step-100] of the first embodiment, after the gate insulating films 12A and 12B are formed on the surface of the semiconductor substrate 10 made of a silicon semiconductor substrate as a semiconductor layer, , Polysilicon layer 13
Is formed, and at least an impurity is introduced into the polysilicon layer 13 in a region where the second transistor is to be formed.

[Step-210] Then, in the same manner as in [Step-110] of the first embodiment, the refractory metal material layer 14 and the insulating material layer 15 are sequentially laminated on the polysilicon layer 13 and then the The insulating material layer 15 and the high melting point metal material layer 14 in the region where one transistor is to be formed are removed.

[Step-220] Then, the insulating material layer 15, the refractory metal material layer 14, and the silicon layer 13 are patterned in substantially the same manner as in [Step-130] of the first embodiment to form a second transistor. Is formed. At the same time, the polysilicon layer 13 is patterned (see FIG. 21). Patterning can be performed based on a known method such as a lithography method and an etching method. The polysilicon layer 13 in the region where the p-channel first transistor is to be formed has p-type conductivity.
Since no type impurity is contained, it is possible to avoid the occurrence of a problem caused by a difference in etching rate between the polysilicon layer containing the n-type impurity and the polysilicon layer containing the p-type impurity. Then, the polysilicon layer 1
3 may be oxidized to form a silicon oxide (SiO ₂ ) film on the side surface.

[Step-230] Then, in the same manner as in [Step-140] of the first embodiment, an n-type impurity is introduced into the semiconductor substrate 10 in the region where the second transistor is to be formed. Are formed (see FIG. 22). still,
In addition, an LDD structure or an extension region 21A is formed on the semiconductor substrate 10 in a region where the first transistor is to be formed.

[Step-240] Next, in substantially the same manner as in [Step-150] of the first embodiment, the region where the second transistor is to be formed is covered with the insulating layer 24, and is patterned. A sidewall 124A is formed on the side wall of the polysilicon layer 13 (see FIG. 23).

[Step-250] Next, as in [Step-170] of the first embodiment, the semiconductor substrate 10 and the polysilicon layer 1 in the region where the first transistor is to be formed are formed.
The source / drain region 22A and the gate electrode 20A that constitute the first transistor are formed by introducing impurities into the transistor 3 (see FIG. 24).

[Step-260] Then, similarly to [Step-180] of the first embodiment, the semiconductor substrate 10 forming the source / drain region 22A of the first transistor is formed.
And the gate electrode 20A of the first transistor
A silicide layer 26 is formed on the surface of the polysilicon layer 13 constituting the semiconductor layer based on the salicide technique (see FIG. 25).

The structure and height of the gate electrode 20A of the first transistor and the gate electrode 20B of the second transistor are the same as those of the gate electrode 20A and the second transistor of the first transistor in the first embodiment. The structure and height of the gate electrode 20B are the same.

[Step-270] After that, in the same manner as in [Step-190] of the first embodiment, an interlayer insulating layer, a contact plug, a DRAM capacitor, wiring, and the like are formed.
Complete the RAM embedded logic LSI.

Although the present invention has been described based on the embodiments of the present invention, the present invention is not limited to these embodiments. Structure of the semiconductor device described in the embodiment of the invention,
The materials, processing conditions, ion implantation conditions, and the like used in the manufacture of the semiconductor device are merely examples, and can be changed as appropriate. The second transistor is not limited to a DRAM. In some cases, the formation of the insulating material layer 15 may be omitted, and only the insulating layer 24 may be formed. When the sidewall 24A is formed, the insulating layer 24 in a region where the second transistor is to be formed may be removed.

[0095]

According to the method of manufacturing a semiconductor device of the present invention or the semiconductor device according to the second and third aspects of the present invention, the height of the gate electrode of the first transistor is reduced by the height of the second transistor. Since the height is lower than the height of the gate electrode, the difference between the maximum value and the minimum value of the aspect ratio determined by the distance (interval) between the gate electrodes in the adjacent first transistors and the height of the gate electrode can be reduced. As a result, the source /
The difference between the maximum value and the minimum value of the thickness of the silicide layer finally formed in the drain region can be reduced, and the parasitic resistance of the CMOS transistor forming the logic circuit can be reduced.

In the method for manufacturing a semiconductor device according to the first to third aspects of the present invention, the gate electrode is formed by introducing an impurity into the patterned and exposed silicon layer. It is possible to avoid the problem that the patterning of the silicon layer becomes difficult due to the difference in the etching rate depending on the type (n-type and p-type) of the impurity introduced into the silicon layer.

Furthermore, the heat treatment is applied to the boron contained in the silicon layer basically only once for activating the boron introduced into the silicon layer. Therefore, it is possible to avoid the problem that the impurity contained in the silicon layer is diffused into the high melting point metal material layer or the semiconductor layer, and the boron concentration in the silicon layer is reduced. As a result, it is possible to avoid a decrease in the current driving capability of the p-channel first transistor in the CMOS logic circuit.

A refractory metal layer is formed on the gate electrode (word line) of the second transistor forming the DRAM, and a silicide layer is formed on the gate electrode of the first transistor forming the logic circuit. Therefore, in each of the transistors, the resistance of the gate electrode can be reduced. Therefore, a large capacity DRAM and a logic circuit can be mixedly mounted on one chip.

In addition, since no silicide layer is formed in the source / drain regions forming the second transistor, it is possible to avoid a problem such as deterioration of DRAM memory cell characteristics.

Further, in the first transistor,
Since the sidewall is formed on the side wall of the gate electrode, even when the opening is shifted to the gate electrode side due to misalignment when forming the opening in the interlayer insulating layer in forming the contact plug to the source / drain region. In addition, the distance between the gate electrode and the contact plug is ensured, and the breakdown voltage between the gate electrode and the contact plug does not deteriorate. Also, in the second transistor, if an insulating layer is formed on the gate electrode, when forming an opening in the interlayer insulating layer in forming a contact plug in the source / drain region, the opening may be misaligned due to misalignment. Even if the shift is made, the distance between the gate electrode and the contact plug is ensured, so that the breakdown voltage between the gate electrode and the contact plug does not decrease.

Further, in the method for manufacturing a semiconductor device according to the second or third aspect of the present invention, the first transistor is formed in a state where the source / drain regions forming the second transistor are covered with the insulating layer. Since the semiconductor layer in the region where the transistor is to be formed is exposed, at this time, the semiconductor layer in the region where the second transistor is to be formed is dug by etching or is damaged by etching (so-called generation of suboxide in a semiconductor substrate or carbon dioxide). Hammering)
Does not occur, and the characteristics of the second transistor can be prevented from deteriorating.

As a result, it is possible to achieve good compatibility between a high-speed logic circuit manufacturing process including salicide technology and dual gate technology and a general-purpose DRAM manufacturing process. That is, by adding an additional DRAM process to a standard logic circuit process, a semiconductor device in which a logic circuit and a DRAM are mixed can be easily obtained. Further, a DRAM memory cell can be prepared as an IP library expected to be distributed in the future. Furthermore, since a semiconductor layer in a region where a silicide layer should not be formed can be easily obtained, a protection element and a high resistance element of an input / output circuit having high electrostatic breakdown strength can be formed at the same time.

[Brief description of the drawings]

FIG. 1 is a schematic partial cross-sectional view of a semiconductor substrate and the like for describing a method for manufacturing a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a schematic partial cross-sectional view of the semiconductor substrate and the like for describing the method for manufacturing the semiconductor device of the first embodiment of the invention, following FIG. 1;

FIG. 3 is a schematic partial cross-sectional view of the semiconductor substrate and the like for explaining the method for manufacturing the semiconductor device of the first embodiment of the invention, following FIG. 2;

FIG. 4 is a schematic partial cross-sectional view of the semiconductor substrate and the like for describing the method for manufacturing the semiconductor device of the first embodiment of the invention, following FIG. 3;

FIG. 5 is a schematic partial cross-sectional view of the semiconductor substrate and the like for explaining the method for manufacturing the semiconductor device of the first embodiment of the invention, following FIG. 4;

FIG. 6 is a schematic partial cross-sectional view of the semiconductor substrate and the like for explaining the method for manufacturing the semiconductor device of the first embodiment of the invention, following FIG. 5;

FIG. 7 is a schematic partial cross-sectional view of the semiconductor substrate and the like for describing the method for manufacturing the semiconductor device of the first embodiment of the invention, following FIG. 6;

FIG. 8 is a schematic partial cross-sectional view of the semiconductor substrate and the like for illustrating the method for manufacturing the semiconductor device of the first embodiment of the invention, following FIG. 7;

FIG. 9 is a schematic partial cross-sectional view of the semiconductor substrate and the like for illustrating the method for manufacturing the semiconductor device of the first embodiment of the invention, following FIG. 8;

FIG. 10 is a schematic partial cross-sectional view of the semiconductor substrate and the like for describing the method for manufacturing the semiconductor device of the first embodiment of the invention, following FIG. 9;

FIG. 11 is a schematic partial cross-sectional view of the semiconductor substrate and the like for describing the method for manufacturing the semiconductor device of the first embodiment of the invention, following FIG. 10;

FIG. 12 is a schematic partial cross-sectional view of the semiconductor substrate and the like for explaining the method for manufacturing the semiconductor device of the first embodiment of the invention, following FIG. 11;

FIG. 13 is a schematic partial cross-sectional view of the semiconductor substrate and the like for explaining the method for manufacturing the semiconductor device of the first embodiment of the invention, following FIG. 12;

FIG. 14 is a schematic partial cross-sectional view of the semiconductor substrate and the like for illustrating the method for manufacturing the semiconductor device of the first embodiment of the invention, following FIG. 13;

FIG. 15 is a schematic partial cross-sectional view of the semiconductor substrate and the like for describing the method for manufacturing the semiconductor device of the first embodiment of the invention, following FIG. 14;

FIG. 16 is a schematic partial cross-sectional view of the semiconductor substrate and the like for illustrating the method for manufacturing the semiconductor device of the first embodiment of the invention, following FIG. 15;

FIG. 17 is a schematic partial cross-sectional view of the semiconductor substrate and the like for illustrating the method for manufacturing the semiconductor device of the first embodiment of the invention, following FIG. 16;

FIG. 18 is a schematic partial cross-sectional view of the semiconductor substrate and the like for illustrating the method for manufacturing the semiconductor device of the first embodiment of the invention, following FIG. 17;

FIG. 19 is a schematic partial cross-sectional view of the semiconductor substrate and the like for describing the method for manufacturing the semiconductor device of the first embodiment of the invention, following FIG. 18;

20 is a schematic partial cross-sectional view of the semiconductor substrate and the like for describing the method for manufacturing the semiconductor device of the first embodiment of the invention, following FIG. 19;

FIG. 21 is a schematic partial cross-sectional view of a semiconductor substrate and the like for describing a method of manufacturing a semiconductor device according to a second embodiment of the present invention;

FIG. 22 is a schematic partial cross-sectional view of the semiconductor substrate and the like for illustrating the method for manufacturing the semiconductor device of the second embodiment of the invention, following FIG. 21;

FIG. 23 is a schematic partial cross-sectional view of the semiconductor substrate and the like for illustrating the method for manufacturing the semiconductor device of the second embodiment of the invention, following FIG. 22;

FIG. 24 is a schematic partial cross-sectional view of the semiconductor substrate and the like for illustrating the method for manufacturing the semiconductor device of the second embodiment of the invention, following FIG. 23;

FIG. 25 is a schematic partial cross-sectional view of the semiconductor substrate and the like for illustrating the method for manufacturing the semiconductor device of the second embodiment of the invention, following FIG. 24;

FIG. 26 is a schematic partial cross-sectional view of a semiconductor substrate and the like for describing a conventional method for manufacturing a semiconductor device.

FIG. 27 is a schematic partial cross-sectional view of a semiconductor substrate and the like for illustrating a conventional method for manufacturing a semiconductor device, following FIG. 26;

FIG. 28 is a schematic partial cross-sectional view of a semiconductor substrate or the like for illustrating a conventional method for manufacturing a semiconductor device, following FIG. 27;

FIG. 29 is a schematic partial cross-sectional view of a semiconductor substrate or the like for illustrating a conventional method for manufacturing a semiconductor device, following FIG. 28;

30 is a schematic partial cross-sectional view of a semiconductor substrate or the like for illustrating a conventional method for manufacturing a semiconductor device, following FIG. 29;

FIG. 31 is a schematic partial cross-sectional view of a semiconductor substrate or the like for describing a conventional method of manufacturing a semiconductor device, following FIG. 30;

FIG. 32 is a schematic partial cross-sectional view of a semiconductor substrate and the like for illustrating a conventional method for manufacturing a semiconductor device, following FIG. 31;

FIG. 33 is a schematic partial cross-sectional view of a semiconductor substrate and the like for illustrating a conventional method for manufacturing a semiconductor device, following FIG. 32;

[Explanation of symbols]

10: semiconductor substrate, 11: element isolation region, 12
A. 12B: gate insulating film, 13: polysilicon layer, 14: refractory metal material layer, 15: insulating material layer, 16: cap layer, 20A, 20B: gate electrode, 21A: Extension area, 22
A, 22B ... source / drain regions, 23A, 23
B: channel forming region, 24: insulating layer, 24
A, 124A: sidewall, 25: refractory metal layer, 26, 26 ': silicide layer

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 27/108 H01L 29/78 301G 21/8242 29/43 29/78 F term (Reference) 4M104 AA01 BB01 BB02 BB14 BB18 BB20 BB30 BB33 CC01 CC05 DD09 DD37 DD63 EE03 EE12 EE17 FF13 FF14 GG09 GG14 GG16 HH14 5F038 AC05 AC15 CD05 CD19 DF05 EZ01 EZ06 EZ20 5F040 DB03 DB09 DC01 EB03 EC02 EC07 EC05 EC05 EC05 EC05 EC05 AC03 AC10 BA16 BB00 BB06 BB07 BB08 BB09 BB10 BB11 BB13 BC18 BD04 BE03 BF06 BF11 BG12 BG13 DA25 DA27 DA30 5F083 AD63 AD70 GA02 GA06 HA02 HA07 JA06 JA32 JA35 JA39 JA53 KA05 MA06 MA19 ZA05 ZA08 ZA08

Claims (8)

[Claims] 1. A semiconductor device comprising a plurality of first transistors formed in a first region of a semiconductor layer and a plurality of second transistors formed in a second region of the semiconductor layer. Each of the first and second transistors includes a gate electrode, a channel formation region, and a source / drain region, and the height of the gate electrode in the first transistor is equal to the second height.
A semiconductor device, wherein the height is lower than the height of the gate electrode of the transistor. 2. A logic circuit is constituted by a first transistor, and a dynamic random access circuit is constituted by a second transistor.
2. The semiconductor device according to claim 1, wherein an access memory is configured. 3. The semiconductor device according to claim 1, wherein a silicide layer is formed in a source / drain region of the first transistor. 4. A gate electrode of the first transistor has a two-layer structure of a polycrystalline or amorphous silicon layer and a silicide layer formed on the silicon layer. Has a three-layer structure of at least a polycrystalline or amorphous silicon layer, a high melting point metal material layer formed on the silicon layer, and an insulating material layer formed on the high melting point metal material layer. The semiconductor device according to claim 1, wherein: 5. A semiconductor device comprising: a plurality of first transistors formed in a first region of a semiconductor layer; and a plurality of second transistors formed in a second region of the semiconductor layer. Each of the second transistors is a method for manufacturing a first transistor in a semiconductor device including a gate electrode, a channel formation region, and a source / drain region, wherein (A) forming a gate insulating film on a surface of a semiconductor layer Forming a polycrystalline or amorphous silicon layer, forming a cap layer on the silicon layer, and then patterning the cap layer and the silicon layer; and (B) forming the patterned silicon layer and (C) removing the cap layer; (D) removing impurities from the silicon layer and the semiconductor layer. Forming a gate electrode made of a patterned silicon layer and forming a source / drain region in the semiconductor layer, and (E) a portion of the semiconductor layer forming the source / drain region, And, on the surface of the silicon layer constituting the gate electrode,
A method of manufacturing a semiconductor device, comprising: forming a silicide layer. 6. A semiconductor device comprising: a plurality of first transistors formed in a first region of a semiconductor layer; and a plurality of second transistors formed in a second region of the semiconductor layer. Each of the second transistors is a method of manufacturing a semiconductor device including a gate electrode, a channel formation region, and a source / drain region. (A) After forming a gate insulating film on a surface of a semiconductor layer, Or a step of forming an amorphous silicon layer and then introducing an impurity into at least a silicon layer in a region where a second transistor is to be formed; and (B) forming a high melting point metal material layer and Removing the insulating material layer and the refractory metal material layer in a region where the first transistor is to be formed after the insulating material layers are sequentially stacked; and (C) forming a cap layer over the entire surface, and then removing the second transistor. (D) patterning the insulating material layer, the refractory metal material layer, and the silicon layer to form a gate electrode that constitutes the second transistor; and Patterning the cap layer and the silicon layer; and (E) forming source / drain regions constituting the second transistor by introducing impurities into a semiconductor layer in a region where the second transistor is to be formed. (F) a step of covering a region where a second transistor is to be formed with an insulating layer, and forming sidewalls on sidewalls of the stacked body including the patterned silicon layer and the cap layer; and (G) Removing the cap layer; and (H) introducing impurities into the semiconductor layer and the silicon layer in a region where the first transistor is to be formed. By the first
Forming a source / drain region and a gate electrode constituting the transistor of (a), (I) forming a portion of a semiconductor layer constituting a source / drain region of the first transistor, and constituting a gate electrode of the first transistor Forming a silicide layer on the surface of the silicon layer. 7. A semiconductor device comprising: a plurality of first transistors formed in a first region of a semiconductor layer; and a plurality of second transistors formed in a second region of the semiconductor layer. Each of the second transistors is a method of manufacturing a semiconductor device including a gate electrode, a channel formation region, and a source / drain region. (A) After forming a gate insulating film on a surface of a semiconductor layer, Or a step of forming an amorphous silicon layer and then introducing an impurity into at least a silicon layer in a region where a second transistor is to be formed; and (B) forming a high melting point metal material layer and Removing the insulating material layer and the refractory metal material layer in the region where the first transistor is to be formed after sequentially laminating the insulating material layers; and (C) insulating material layer, refractory metal material layer and silicon layer Forming a gate electrode constituting the second transistor by patterning the second transistor, and simultaneously patterning the silicon layer; and (D) introducing an impurity into the semiconductor layer in a region where the second transistor is to be formed. Forming a source / drain region constituting a second transistor, and (E) covering a region where the second transistor is to be formed with an insulating layer, and forming side surfaces on side walls of the patterned silicon layer. Forming a wall, and (F) introducing an impurity into a semiconductor layer and a silicon layer in a region where a first transistor is to be formed, thereby forming a first transistor.
(G) forming a source / drain region and a gate electrode of the first transistor; and (G) forming a portion of a semiconductor layer forming a source / drain region of the first transistor, and forming a gate electrode of the first transistor. Forming a silicide layer on the surface of the silicon layer. 8. A logic circuit is constituted by a first transistor, and a dynamic random access circuit is constituted by a second transistor.
8. The method for manufacturing a semiconductor device according to claim 5, wherein an access memory is configured.