KR100855862B1 - SRAM cell and method for manufacturing the same - Google Patents

Abstract

An SRAM cell and a method of fabricating the same may be simplified by forming a capacitor in a logic unit by using a local interconnection wire of an SRAM cell unit. The method of manufacturing such an SRAM cell includes a source / drain region and a gate electrode. A method of manufacturing an SRAM comprising a logic section including a transistor, and a cell section including first and second access transistors, first and second driving transistors, and first and second load transistors, the semiconductor substrate of the cell section. Contacting the first terminal of the first access, the first load and the first driving transistor and the gate electrode of the second load and the second driving transistor to electrically contact the second access, the second load and the second driving transistor. Local contact is made to electrically contact the first electrode, the first rod, and the gate electrode of the first driving transistor, and at the same time to contact the gate electrode of the logic unit. Forming a wiring; A contact hole to expose a predetermined portion of the first and second access transistors, the first and second load transistors, and the second ends of the first and second driving transistors, and the local connection wiring of the logic part may Forming a planar insulating film; The first and second access transistors, the first and second load transistors, and the second ends of the first and second driving transistors are electrically connected to each other through the contact hole. Forming a metal wire in the characterized in that it comprises.

Logic section, local interconnect wiring, SRAM

Description

SRAM cell and its manufacturing method {SRAM cell and method for manufacturing the same}

1 is an equivalent circuit diagram showing a typical SRAM cell

2 is a structural cross-sectional view of an SRAM cell according to the prior art.

3 is a structural cross-sectional view of an SRAM cell according to an embodiment of the present invention;

4A to 4G are cross-sectional views illustrating a method of manufacturing an SRAM cell according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

41 semiconductor substrate 42 element isolation film

43a: p well region 43b: n well region

44: gate insulating film

45a, 45b, 45c: first, second and third gate electrodes

47: insulating film side wall 49: metal silicide film

50: first flat insulating film 51: first contact hole

52: first barrier metal film 53: first tungsten plug

54: first metal wiring 55: second flat insulating film

56: second contact hole 57: the first barrier metal film                 

58: second tungsten plug 59: second metal wiring

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to an SRAM cell suitable for simplifying a process by forming a metal insulator metal (MIM) capacitor using a local interconnection wire in a logic part of a chip in which analog and digital signals are mixed. It relates to a manufacturing method.

Generally, a random random access memory (SRAM) cell is generally composed of a flip-flop circuit consisting of two access transistors, two drive transistors, and two load transistors. .

1 is an equivalent circuit diagram illustrating a general CMOS SRAM cell.

As shown in FIG. 1, the first and second access transistors Q1 and Q2, the first and second drive transistors Q3 and Q4, and the first and second load transistors Q5, Q6).

At this time, the SRAM cell is connected in parallel between the power supply terminal (Vcc) and the ground terminal (Vss), the first driving transistor (Q5) consisting of the PMOS transistor and the first driving transistor (Q3) consisting of the NMOS transistor is the first inverter ( an inverter, a second load transistor Q6 composed of a PMOS transistor and a second driving transistor Q4 composed of an NMOS transistor form a second inverter, and a first access transistor Q1 and a second access transistor. A source (or drain) thereof is connected to the output terminals of the first and second inverters Q2, respectively.

A first bit line BL and a second bit line / BL are connected to the drain (or source) of the first access transistor Q1 and the drain (or source) of the second access transistor Q2, respectively.

In addition, the first and second inverters are connected to the output terminal of the second inverter and the input terminal of the first inverter is connected to the output terminal of the first inverter in order to form a latch circuit. do.

Hereinafter, a conventional SRAM cell will be described with reference to the accompanying drawings.

1 is a cross-sectional view of a wiring portion to be in contact with a logic unit, a first or second access transistor, and a first or second load transistor.

In the conventional SRAM cell, as shown in FIG. 1, an element isolation film 12 is formed in a field region of a semiconductor substrate 11 defined as a field region and an active region, and n− is formed on the surface of the semiconductor substrate 11. The well region 13b and the p-well region 13a are formed, respectively.

Subsequently, first and second gate electrodes 15a and 15b are formed in predetermined regions of the active region through the gate insulating layer 14 on the semiconductor substrate 11, and the first and second gate electrodes ( The insulating film sidewalls 17 are formed on both side surfaces of the 15a and 15b.

In this case, a first or second access transistor is formed in the p-well region 13a, and a first or second load transistor is formed in the n-well region 13b.                         

Hereinafter, the first or second access transistor is referred to as a first gate electrode 15a and the first or second load transistor is referred to as a second gate electrode 15b.

Subsequently, a source / drain region 18 is formed in a surface of the semiconductor substrate 11 on both sides of the first and second gate electrodes 15a and 15b, and the first and second gate electrodes 15a and 15b and The metal silicide film 19 is formed on the surface of the semiconductor substrate 11 on which the source / drain regions 18 are formed.

The first planar insulating layer 20 is formed to have a first contact hole so that the surfaces of the source or drain region 18 and the second gate electrode 15b are partially exposed.

In this case, the first planar insulating layer 20 may be formed of boron phosphorus silicate glass (BPSG) or plasma enhanced-tetra ethyl ortho silicate (PE-TEOS).

Subsequently, a first tungsten plug 22 is formed in each of the first contact holes through the first barrier metal film 21, and the first tungsten plug 22 and the first flat insulating film 20 adjacent thereto are formed. Is formed on the first metal wiring 23.

The first metal wiring 23 is used as a local interconnection metal connecting the Vcc line and the Vss line and the impurity region of each transistor and the gate electrode.

A second planar insulating film 24 is formed on the entire surface, and a second contact hole is formed in the source region (or drain region) on one side of the first gate electrode 15a for connecting to the logic unit.

Subsequently, a second tungsten plug 26 is formed in the second contact hole through the second barrier metal layer 25, and the second tungsten plug 26 and the second flat insulating layer 24 adjacent thereto are formed. The second metal wiring 27 is formed on the dot).

A third planar insulating film 28 is formed on the entire surface including the second metal wiring 27, and a third contact hole is formed on the second metal wiring 27 to be connected to the logic unit.

Subsequently, a third tungsten plug 30 is formed in the third contact hole through the third barrier metal layer 29, and the third tungsten plug 30 and the third flat insulating layer 28 adjacent thereto are formed. The third metal wiring 31 is formed on the top.

Although not shown in the drawings, the capacitor of the logic part may be formed by depositing a semiconductor layer or a separate metal layer separately from the local interconnection wiring of the SRAM cell part (eg, separating the second metal wiring, the third flat insulating film, and the third metal wiring separately from each other. Vapor deposition).

As a result, a mask process needs to be added to the existing process, which causes a complicated process.

The present invention has been made to solve the above problems, and an object of the present invention is to use a local interconnect wiring of the SRAM cell unit, MIM (Metal Insulator Metal) in the logic portion of the chip mixed with analog and digital signals An object of the present invention is to provide an SRAM cell and a method of manufacturing the same, which can simplify a process by forming a capacitor.

In the SRAM cell of the present invention for achieving the above object, in the SRAM composed of a logic unit and a cell unit, first and second accesses each having a source / drain region and a gate electrode are provided on a semiconductor substrate of the cell unit. A transistor and first and second driving transistors and first and second load transistors; A transistor including a source / drain region and a gate electrode on the semiconductor substrate of the logic unit; Electrically contacting the first access, the first load and the first terminal of the first driving transistor and the gate electrode of the second load and the second driving transistor to electrically contact the second access, the second load and the second driving transistor; A local connection wiring electrically contacting the gate electrodes of the first stage, the first rod, and the first driving transistor, and simultaneously contacting the gate electrodes of the logic section; The contact hole is formed to expose a predetermined portion of the first and second access transistors, the first and second load transistors, and the second and first driving transistors, and is formed on the front surface including local connection wiring of the logic unit. A flat insulating film; The first and second access transistors, the first and second load transistors, and the second ends of the first and second driving transistors are electrically connected to each other through the contact hole. It characterized in that it comprises a metal wiring formed in.

The SRAM cell manufacturing method of the present invention having the above-described configuration includes a logic unit including a transistor including a source / drain region and a gate electrode, a first and a second access transistor, a first and a second driving transistor, and a first and a In the method of manufacturing an SRAM comprising a cell portion having a second load transistor, the first access, the first load, the first stage and the second load, the second driving transistor of the first access, the first load, the first driving transistor on the semiconductor substrate of the cell portion Electrically contact the gate electrode of the second electrode, the second load, the first end of the second driving transistor, the first rod and the gate electrode of the first driving transistor, and at the same time, the gate electrode of the logic part Forming a localized interconnect so as to be in contact therewith; A contact hole to expose a predetermined portion of the first and second access transistors, the first and second load transistors, and the second ends of the first and second driving transistors, and the local connection wiring of the logic part may Forming a planar insulating film; The first and second access transistors, the first and second load transistors, and the second ends of the first and second driving transistors are electrically connected to each other through the contact hole. Forming a metal wire in the characterized in that it comprises.

The local connection wiring is formed of a TiN / Ti film or a copper film.

The local connection wiring, the planar insulating film, and the metal wiring of the logic unit constitute a capacitor.

Hereinafter, an SRAM cell and a method of manufacturing the same according to a preferred embodiment of the present invention will be described with reference to the accompanying drawings.

In the full CMOS SRAM process using the logic part forming process instead of a single SRAM process, a local interconnection metal is used to reduce the cell area.

In the field of ESL (Embeded SRAM Logic), where the range of application is gradually increasing, not only the memory but also the logic part occupy a large area.In the case of a chip mixed with analog and digital signals, local interconnect wiring is applied to the logic part. Utilizing as capacitance helps to reduce chip area efficiently.                     

First, the configuration of an SRAM cell according to an embodiment of the present invention will be described.

3 is a structural cross-sectional view of an SRAM cell according to an embodiment of the present invention.

In the SRAM cell according to the exemplary embodiment of the present invention, as shown in FIG. 3, the device isolation layer 42 is formed in the field region of the semiconductor substrate 41 defined as the field region and the first and second active regions. The p-well region 43a and the n-well region 43b are formed in the surface of the semiconductor substrate 41, respectively.

The region where the p-well region 43a is formed is a first active region, and the region where the n-well region 43b is formed is a second active region.

The isolation layer 42 has a shallow trench isolation (STI) structure.

Subsequently, first and second gate electrodes 45a and 45b and a third gate electrode 45c of the logic unit are formed in a predetermined region of the active region of the semiconductor substrate 41 via the gate insulating layer 44. Insulating sidewalls 47 are formed on both side surfaces of the first, second, and third gate electrodes 45a, 45b, and 45c.

In this case, a first or second access transistor is formed in the p-well region 43a, and a first or second load transistor is formed in the n-well region 43b.

Therefore, the first gate electrode 45a means the first or second access transistor, and the second gate electrode 45b means the first or second load transistor.

The gate insulating layer 44 may have a thickness different from a region in which a PMOS transistor is formed and a region in which an NMOS transistor is formed, and a thin side has a thickness of about 29 μs and a thick side has a thickness of about 64 μm.

On the other hand, the first to third gate electrodes 45a, 45b, 45c are formed of a polysilicon film and have a thickness of about 2500 kPa.

Subsequently, an LDD structure source / drain region 48 is formed on a surface of the semiconductor substrate 41 on both sides of the first, second, and third gate electrodes 45a, 45b, and 45c. The metal silicide film 49 is formed on the surface of the semiconductor substrate 41 on which the third gate electrodes 45a, 45b, 45c and the source / drain regions 48 are formed.

The metal silicide film 49 is made of a high melting point metal film (for example, Co / Ti).

The first planar insulating layer 50 is formed to have a first contact hole so that the source or drain region 48 and the surfaces of the second and third gate electrodes 45b and 45c are partially exposed.

In this case, the first flat insulating layer 50 is formed of boron phosphorus silicate glass (BPSG).

The first planar insulating film 50 may be formed by stacking a nitride film, a boron phosphorus silica glass (BPSG) film, and a plasma enhanced-tetra ethyl ortho silicate film (PE-TEOS).

Subsequently, a first tungsten plug 53 is formed in each of the first contact holes of the logic unit and the SRAM cell unit via the first barrier metal layer 52, and the first tungsten of the logic unit and the SRAM cell unit is formed. A first metal fast wiring 54 is formed on the plug 53 and the first flat insulating film 50 adjacent thereto.

The first metal wiring 54 is used as a local interconnection metal connecting the Vcc line, the Vss line, and the impurity region and the gate electrode of each transistor.

The first interconnection 54, which is the local interconnection line, may be a metal having a low resistance, for example, a metal film or a copper film laminated with TiN / Ti, and has a thickness of about 200 GPa and about 100 GPa of TiN. to be.

On the other hand, L / S (Line / Space) of the first metal wiring 54 is 0.20 / 0.19㎛.

The first metal wiring 54 electrically contacts the first access, the first load, the first terminal of the first driving transistor, the gate electrode of the second load, and the second driving transistor of the SRAM cell unit, and The second access, the second load, the first terminal of the second driving transistor, the first rod, the gate electrode of the first driving transistor are electrically contacted, and at the same time, the first gate electrode 45a of the logic part is contacted.

A second planar insulating film 55 is formed on the entire surface, and a second contact hole is formed in a source region (or drain region) on one side of the first gate electrode 45a for connecting to the logic unit.

In this case, the second contact hole is formed to expose a predetermined portion of the first and second access transistors, the first and second load transistors, and the second ends of the first and second driving transistors.

In this case, the second flat insulating layer 55 may be formed of Plasma Enhanced-Tetra Ethyl Ortho Silicate (PE-TEOS) to have a thickness of about 1000 GPa.                     

Subsequently, a second tungsten plug 58 is formed in the second contact hole through the second barrier metal film 57, and the second tungsten plug 58 and the second flat insulating film 55 adjacent thereto are formed. The second metal wiring 59 is formed on the top.

 In this case, the first metal wiring 54, the second flat insulating film 55, and the second metal wiring 59 of the logic unit function as capacitors serving as capacitor lower electrodes, dielectric layers, and capacitor upper electrodes, respectively.

That is, the first metal wiring 54, which is a local interconnection wiring of the SRAM cell portion, was used together with the capacitor lower electrode of the logic portion.

Next, a manufacturing method of the SRAM cell according to the embodiment of the present invention having the above configuration will be described.

4A through 4G are cross-sectional views illustrating a method of manufacturing an SRAM cell according to an embodiment of the present invention.

4A to 4G, the left side represents a logic unit and the right side represents an SRAM cell unit.

In the method of manufacturing an SRAM cell according to an embodiment of the present invention, as shown in FIG. 4A, the device isolation layer 42 is formed in the field region of the semiconductor substrate 41 defined as the first and second active regions and the field region. do.

Here, the method of forming the device isolation layer 42 is as follows although not shown in the drawing.

That is, a pad oxide film and a pad nitride film are sequentially formed on the semiconductor substrate 41, a photoresist is applied on the pad nitride film, and the photoresist is patterned by an exposure and development process to define a field region and an active region.

Subsequently, the pad nitride film and the pad oxide film are selectively removed using the patterned photoresist as a mask, the photoresist is removed, and the field region of the semiconductor substrate is selectively selected using the selectively removed nitride film as a mask. To form a trench with a certain depth from the surface.

In order to compensate for damage of the semiconductor substrate 41 generated during the trench process, an oxide process is performed on the semiconductor substrate 41 to form an oxide film on the trench surface.

Subsequently, a gap-fill HDP oxide film is formed on the entire surface of the semiconductor substrate 41 including the trench, followed by an annealing process, and the front surface of the semiconductor substrate 41 using the pad oxide film as an end point. A chemical mechanical polishing (CMP) process is performed on the device to form a device isolation layer 42 inside the trench.

The pad oxide film is removed by performing a cleaning process on the semiconductor substrate 41.

Subsequently, as shown in FIG. 4B, n-type and p-type impurity ions are selectively implanted into the semiconductor substrate 41 to form an n-well region 43b and a p-well region in the surface of the semiconductor substrate 41. 43a are formed, respectively.

Herein, a method of forming the n-well region 43b and the p-well region 43a will be described in more detail.                     

First, an n-well is formed on the semiconductor substrate 41 by lithography, and phosphorus (P) is implanted into the exposed area by using a resist film (not shown) as a mask. The region 43b is formed.

In addition, a threshold voltage regulating assay As is injected into the n-well region 43b.

Subsequently, after removing the resist film, a region in which a p-well is to be formed is exposed by a lithography method, and boron B is implanted using a resist film (not shown) as a mask to form a p-well region 43a. do.

The boron B for threshold voltage control is injected into the p-well region 43a.

Next, an annealing process is performed on the semiconductor substrate 41 to activate the impurity ions implanted into the n-well region 43b and the p-well region 43a.

Thereafter, as shown in FIG. 4C, the gate insulating film 44 and the gate polysilicon film are sequentially formed on the entire surface of the semiconductor substrate 41.

Here, the gate insulating film 44 may be formed of a dual gate insulating film having a different thickness between the region where the NMOS transistor is to be formed and the region where the PMOS transistor is to be formed. The thin side is about 29 GPa, and the thick side is about 59 GPa. .

Subsequently, the polysilicon layer and the gate insulating layer 44 are selectively removed by a photo and etching process to form first, second, and third gate electrodes 45a, 45b, and 45c from the left side.

As shown in FIG. 4D, low concentration n-type and p-type impurity ions are selectively implanted into the semiconductor substrate 41 using the first to third gate electrodes 45a, 45b, and 45c as masks. Lightly doped drain (LDD) regions 46 are formed in the surfaces of the semiconductor substrate 41 on both sides of the first to third gate electrodes 45a, 45b, and 45c.

As shown in FIG. 4E, an insulating film is formed on the entire surface including the first to third gate electrodes 45a, 45b, and 45c, and then etched back to form the first to third gate electrodes 45a, 45b, and 45c. The insulating film sidewalls 47 are formed on both sides of the semiconductor film, and the high concentration n-type is formed on the entire surface of the semiconductor substrate 41 using the insulating film sidewalls 47 and the first to third gate electrodes 45a, 45b, and 45c as masks. P-type impurity ions are selectively implanted to form source / drain regions 48 in the surface of the semiconductor substrate 41.

Meanwhile, halo ions P or BF ₂ may be implanted into the semiconductor substrate 41 while giving a tilt angle of about 30 degrees.

In other words, as the size of logic devices is reduced, problems such as Hot Carrier Effect (HCE), Short Channel Effect (SCE), and Reverse SCE (Reverse SCE) are induced, resulting in deterioration of device performance and device performance. In order to inject a halo ion into the source / drain region 39 to give a tilt to increase the well concentration locally, the doping concentration can be locally increased only at the inner wall of the junction. The channel length can be made shorter without increasing.

In addition, the punch-through phenomenon is suppressed for the same channel length, thereby reducing the cost because the junction breakdown voltage is increased and the concentration is increased only at the locally required portion instead of increasing the overall concentration of the substrate. can do.

A high melting point metal film (eg, Co / Ti, etc.) is deposited on the entire surface of the semiconductor substrate 41 including the first to third gate electrodes 45a, 45b, and 45c, and a rapid thermal processing (RTP) process is performed. The metal silicide layer 49 is formed on the surface of the semiconductor substrate 41 on which the first to third gate electrodes 45a, 45b and 45c and the source / drain regions 48 are formed.

Co / Ti is formed to a thickness of 150/150 Å by the sputtering method.

The non-reacting high melting point metal film of the first to third gate electrodes 45a, 45b and 45c and the semiconductor substrate 41 is removed by wet etching.

The heat treatment process for forming the metal silicide film 49 is formed by performing a first RTP process at about 530 ° C. and 60 seconds, followed by a second RTP process at about 750 ° C. and 30 seconds, and forming H ₂ O. _A non-reacted high melting metal film is removed using a wet etchant mixed with ₂ and H ₂ SO ₄ .

A first planar insulating film 50 is formed on the entire surface of the semiconductor substrate 41 including the metal silicide film 49.

The first flat insulating layer 50 may be formed by stacking a nitride film, a BPSG film, and a PE-TEOS film in this order.

Subsequently, the first planar insulating layer 50 may be selectively removed to expose portions of the source or drain region 48 and the first and third gate electrodes 45a and 45c by a photo and etching process. 1 Contact hole 51 is formed.

Meanwhile, the first contact hole 51 may include a source / drain region and a second load of the first load transistor Q5, the first driving transistor Q3, and the first access transistor Q1 connected in parallel in FIG. 1. A predetermined portion of the gate electrode of the transistor Q6 and the second driving transistor Q4 is exposed.

In addition, the first contact hole 51 may include source / drain regions of the second load transistor Q6, the second driving transistor Q4, and the second access transistor Q2 connected in parallel, and the first load transistor Q5. ) And the surface of the gate electrode of the first driving transistor Q3 are exposed to a predetermined portion.

As shown in FIG. 4F, the first barrier metal film 52 and the first tungsten film are sequentially formed in the semiconductor substrate 41 including the first contact hole 51, and a CMP process is performed on the entire surface thereof. The first tungsten plug 53 is formed in the first contact hole 51.

The first barrier metal film 52 may be formed of a Ti / TiN film.

The first tungsten plug 53 is formed by forming a metal film made of a Ti / TiN film on the entire surface of the semiconductor substrate 41 including the first tungsten plug 53, and selectively removing the metal film through a photo and etching process. And a first metal wiring 54 which is a local interconnection wiring on the first interlayer insulating film 50 adjacent thereto.

In this case, the first metal wire 54 may be formed to have a thickness of 200 μs / 100 μm or may be formed of a copper film.

The L / S (Line / Space) of the first metal wire 54, which is the local interconnection wire, is 0.20 / 0.19 μm.

In this case, the first metal wiring 54 is also formed on the first tungsten plug 53 and the first flat insulating film 50 adjacent thereto.

A second planar insulating film 55 is formed by depositing a PE-TEOS film on the entire surface of the semiconductor substrate 41 including the first metal wiring 54 which is the local interconnection.

In this case, the second planar insulating layer 55 is used as a capacitor dielectric layer of the logic part later, and the capacitance value may be adjusted by adjusting the thickness by a CMP process.

The second planar insulating layer 55 and the first planar insulating layer 50 are selectively removed so that the surface of the source / drain region 48 where the first tungsten plug 53 is not formed is partially exposed to the second contact. The hole 56 is formed.

The second contact hole 56 is formed so that the source / drain regions of the first and second access transistors Q1 and Q2 and the first and second driving transistors Q3 and Q4 of FIG. 1 are partially exposed. .

As shown in FIG. 4G, a second barrier metal film 57 and a second tungsten film are sequentially formed in the semiconductor substrate 41 including the second contact hole 56, and a CMP process is performed on the entire surface thereof. The second tungsten plug 58 is formed in the second contact hole 56.

The second barrier metal film 57 is formed of a Ti / TiN film.

A metal film is deposited on the entire surface of the semiconductor substrate 41 including the second tungsten plug 58.

The metal layer is selectively removed by a photo and etching process to form a second metal interconnection 59.

The second metal wire 59 is used as a Vcc and Vss line.

In this case, the logic part, that is, the first metal wiring 54, the second flat insulating layer 55, and the second metal wiring 59 on the first gate electrode 45a form a capacitor.

The present invention is not limited to the above embodiments, and includes various forms that can be easily derived by those skilled in the art from the above embodiments.

As described above, the SRAM cell of the present invention and a method of manufacturing the same have the following effects.

First, since the local interconnection wire used in the SRAM cell part is used as the lower electrode when forming the capacitor of the logic part, the capacitor of the logic part can be formed without an additional mask process.

This can simplify the process and shorten the process time.

Second, there is no additional mask cost for forming capacitors in the logic section, which reduces production costs.

Claims (5)

In the SRAM consisting of a logic unit and a cell unit, First and second access transistors, first and second driving transistors, and first and second load transistors each having a source / drain region and a gate electrode on a semiconductor substrate of the cell unit; A transistor including a source / drain region and a gate electrode on the semiconductor substrate of the logic unit; Electrically contacting the first access, the first load and the first terminal of the first driving transistor and the gate electrode of the second load and the second driving transistor to electrically contact the second access, the second load and the second driving transistor; A local connection wiring electrically contacting the gate electrodes of the first stage, the first rod, and the first driving transistor, and simultaneously contacting the gate electrodes of the logic section; The contact hole is formed to expose a predetermined portion of the first and second access transistors, the first and second load transistors, and the second and first driving transistors, and is formed on the front surface including local connection wiring of the logic unit. Flat insulating film, The first and second access transistors, the first and second load transistors, and the second ends of the first and second driving transistors are electrically connected to each other through the contact hole. It is configured to include a metal wiring formed in, The local connection wiring, the planar insulating film, and the metal wiring of the logic unit constitute a capacitor. delete Fabrication of an SRAM comprising a logic section comprising a transistor comprising a source / drain region and a gate electrode, and a cell section including first and second access transistors and first and second driving transistors and first and second load transistors In the method, Contacting the semiconductor substrate of the cell portion with the first access, the first load, the first terminal of the first driving transistor and the gate electrode of the second load, the second driving transistor, and the second access, the second load, Electrically contacting a first end of the second driving transistor, a first rod, and a gate electrode of the first driving transistor, and simultaneously forming a local connection wiring to contact the gate electrode of the logic unit; A contact hole to expose a predetermined portion of the first and second access transistors, the first and second load transistors, and the second ends of the first and second driving transistors, and the local connection wiring of the logic part may Forming a planar insulating film; The first and second access transistors, the first and second load transistors, and the second ends of the first and second driving transistors are electrically connected to each other through the contact hole. Forming a metal wire in the SRAM cell. The method of claim 3, And said local connection wiring is formed of a TiN / Ti film or a copper film. The method of claim 3, And said local connection wiring, said planar insulating film and said metal wiring of said logic section are capacitors.

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