JPH1117027A - Semiconductor storage device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To implement miniaturization of memory cells by forming conductive films on a semiconductor substrate and by connecting side surfaces of plugs to side surfaces of the conductive films while passing the conductive films through the plugs that serve to connect interconnection layers located above the conductive films to semiconductor regions serving as storage nodes in a surface of the semiconductor substrate. SOLUTION: An insulating film is formed on the main surface of a semiconductor substrate, the insulating film serving to cover the main surface. A first polysilicon film 10 which is a conductive film for forming a capacitor is formed through the insulating film, and further a second polysilicon film 11 is formed through a thin insulating film. The connection between a first interconnection 12 and a predetermined region on the main surface of the semiconductor substrate is effected by a plug 15. The connection between the second interconnection and a predetermined region on the obverse surface of the semiconductor substrate is effected by a plug 16. Further, the formed by passing through the films 10 and 11, and the continuity of the films 10 and 11 with the plug 15 is established by means of contact between side surfaces of the films 10 and 11 with side surfaces of the plug 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a technique effective when applied to a semiconductor memory device requiring high soft error resistance.

[0002]

2. Description of the Related Art An SRAM is one of semiconductor memory devices.
(Static Radom Access Memory). As such a BiCMOS memory cell of the SRAM, a polysilicon PMOS load cell is generally used.

However, SRAMs are always required to have a high speed, and while the power supply voltage is being reduced in general semiconductor devices, a polycrystalline silicon PMOS load cell is required to operate at a high speed when the power supply voltage is reduced. It is difficult to operate.

For this reason, a 6-bulk MOS type cell which can operate at high speed even with a low power supply voltage is required. 6
For bulk MOS cells, see T.K. Hiromo
to other IEDM Technical Digest
1992, pages 39 to 42, "A 27 GHz D
available Polysilicon Bipolar
Transistor on Bonded SOI
with Embedded 58 μm ² CMOS
Memory cell for ECL-CMOS
SRAM Applications.

FIG. 1 is a circuit diagram of a 6-bulk MOS type cell, in which a memory cell is a driving NMOS Qnd,
Qnd ′, transfer NMOS Qnt, Qnt ′ and load P
MOSs Qp and Qp ', and Ns, N
s ′ is a storage node that stores information. The storage capacitors include storage capacitors Csg and Csg ′ with respect to the ground potential and a storage capacitor Cscom formed between storage nodes.

FIGS. 2 to 4 are a plan view and a vertical sectional view of a 6 bulk MOS type memory cell implemented by the present inventor, which show a borderless contact and a SAC (Self-A).
ligned Contact), SGI (Shallow Groove Isolatio)
n) The structure is applied for miniaturization.

FIG. 2 is a longitudinal sectional view of the memory cell, and FIGS. 3 and 4 are plan views. In FIGS. 3 and 4, the position of the section shown in FIG. One unit of the cell is indicated by a chain line.

First, as shown in FIG. 2, an n-type well layer 1 and a p-type well layer 2 provided on a main surface of a semiconductor substrate (not shown) via a separation layer (not shown) are formed. Each element formation region is separated by the SGI element isolation film 3, and the FETs Qp ', Qnd', Qnd ', Q
nt ′ source and drain regions 4 are provided, respectively.
A gate electrode 6 is provided via a gate insulating film 5 on the main surface of the semiconductor substrate between the source region 4 and the drain region 4 of each FET.

The source and drain regions 4 have an LDD structure composed of a low-concentration region 4a and a high-concentration region 4b, and 4c is a pocket region of the source and drain regions, and has a low-concentration region 4a and a high-concentration region. The conductive type is opposite to that of the region 4b. That is, n-type FETs Qnd and Qn
For d ′, Qnt and Qnt ′, the low-concentration region 4a and the high-concentration region 4b are n-type diffusion layers,
c is a p-type diffusion layer. For p-type FETs Qp and Qp ′, low-concentration region 4a and high-concentration region 4b are p-type diffusion layers, and pocket region 4c is an n-type diffusion layer.

The gate electrode 6 is a polycide film in which a polycrystalline silicon 6a and a tungsten silicide 6b are sequentially laminated. A cap 7 made of silicon nitride (Si ₃ N ₄ ) is formed on the upper surface, and a cap 7 is formed on the side surface. A sidewall 8 made of silicon nitride is formed. Gate electrode 6
Outside the element formation region, functions as a wiring for interconnecting word lines or gate electrodes.

On the main surface of the semiconductor substrate, silicon oxide (SiO 2)
₂ ) forming an interlayer insulating film 9 covering the main surface;
A first-layer metal wiring 12 is formed thereon. And
After forming an interlayer insulating film 13 made of silicon oxide on the entire surface and covering the metal wiring 12, a second-layer metal wiring 14 is formed.

The connection between the first-layer metal wiring 12 and a predetermined region of the main surface of the semiconductor substrate is performed by the plug 1 penetrating through the interlayer insulating film 9.
The connection between the metal wiring 14 of the second layer and the predetermined region of the main surface of the semiconductor substrate is made by connecting a plug 15 penetrating through the interlayer insulating film 9 and a plug 16 penetrating through the interlayer insulating film 13.
This is performed by connecting the metal wiring 12 of the layer as a landing pad.

FIG. 3 shows a MOSFET constituting a memory cell.
FIG. 4 is a plan view showing an arrangement of each of the F cells constituting a memory cell.
The drain region 4 serving as a node of the ETQnt, Qnd or the FET Qnt ′, Qnd ′ is formed continuously, and is connected to a plug 15 (hatched) connected to the first-layer metal wiring 12.

The source regions 4 of the FETs Qnd and Qnd 'are respectively drawn out by plugs 16 and connected to the ground wiring GND in the upper layer, and the drain regions 4 of the FETs Qnt and Qnt' are connected to the plug 15, the first metal wiring 12 and the plug, respectively. It is drawn out by the metal wirings 14c of the 16th and 2nd layers, and is connected to the bit line 17 of the metal wiring of the 3rd layer in the upper layer.

The gate electrodes 6 of the FETs Qnt and Qnt 'are formed integrally and extend as word lines. FETQ
The gate electrodes 6 of nd and Qp are also integrally formed,
The gate electrodes 6 of Qnd ′ and Qp ′ are also integrally formed, and each partially extends on the drain region 4 serving as the node, and is connected to the plug 15 at this portion.

The drain regions 4 of the FETs Qp and Qp 'are respectively drawn out by a plug 15 and connected to the first-layer metal wiring 12, which is electrically connected to the node by the metal wiring 12, and the source regions 4 of the FETs Qp and Qp' are respectively formed. It is pulled out by the plug 16 and connected to the power supply wiring 14a.

FIG. 4 is a plan view showing the arrangement of the metal wirings.
The metal wiring 12 of the layer is indicated by a broken line, and the metal wiring 17 of the third layer which is the upper layer is indicated by a two-dot chain line. The second layer metal wiring 14 forms a landing pad 14c, a ground wiring 14b, and a power supply wiring 14a for the bit line.

The feature of this memory cell is that the driving MO
SFETs Qnd, Qnd ′ and load MOSFETs Qp,
Storage nodes Ns, N to which the drains of Qp 'are connected
The opening to s' serves as a borderless contact with each SGI element isolation film.
5 and are connected by the first-layer metal wiring 12 which allows openings, and one or two of the four openings are formed.
This is opened over the gate electrode 6 of the other inverter.

The driving MOSFETs Qnd and Qnd '
Opening to the source of the MOSFET, load MOSFET Q
Contact opening and transfer M for the source of p, Qp '
The drain openings of the OSFETs Qnt and Qnt ′ are S
Borderless contact is provided for the GI element isolation film, and SAC is provided for the adjacent gate.
This SAC is performed by using a difference in etching selectivity with respect to each material, for example, a gate cap and a sidewall are made of silicon nitride and an insulating film is made of silicon oxide.

The third layer metal wiring is used, the first layer wiring 12 is used as a connection wiring of each element in the memory cell, the second layer wiring 14 is used as a power supply wiring 14a and a ground wiring 14b, and the third layer wiring is used. Are the bit line wiring, and the third layer wiring is the landing pad 14 formed by the second layer wiring.
c.

[0021]

However, for example, when an SRAM is used as a cache memory, strict soft error resistance is required. At present, in order to satisfy the required soft error resistance, STC (STacke
d Capacitor). However, it is not desirable that the mounting of the STC inhibits the miniaturization of the cell size.

In this regard, in the above-mentioned memory cell, the storage capacitors Csg and Csg ′ are only the drain junction capacitors, and the storage capacitor Cscom is 0. Also S
No TC is provided. Therefore, since the storage capacity is small, it is difficult to realize a soft error tolerance of a level of several hundreds of errors required for a cache SRAM or the like.

In addition, a margin is required between the contact hole for the storage node and the gate of the driving MOS transistor, and this margin hinders a reduction in cell size.

An object of the present invention is to provide a technique for SRAM memory cells that has excellent soft error resistance and can be miniaturized.

Another object of the present invention is to provide a technique capable of facilitating the manufacture of an SRAM memory cell.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0027]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

In a semiconductor memory device having an SRAM type memory cell for storing information in a storage node, a conductor film constituting a capacitor is formed on a main surface of a semiconductor substrate via an insulating film, and a wiring layer above the conductor film is formed. A plug connecting the layer and a semiconductor region serving as a storage node on the main surface of the semiconductor substrate penetrates the conductive film, and a side surface of the plug is connected to a side surface of the conductive film.

In addition, a capacitance is formed by a first wiring layer that forms the storage node and connects to a semiconductor region formed on the main surface of the semiconductor substrate, and a second wiring layer that is formed above the wiring layer. I do.

According to the above-mentioned means, since the capacitance is formed by the conductive film, the soft error resistance is improved.

Further, since a capacitance is formed by the first wiring layer and the second wiring layer, soft error resistance is improved.

Hereinafter, embodiments of the present invention will be described.

In all the drawings for describing the embodiments, those having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

[0034]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) A memory cell of a semiconductor memory device according to an embodiment of the present invention will be described with reference to FIGS.
FIG. 5 is a longitudinal sectional view of the memory cell, and FIGS. 6 to 8 are plan views showing the arrangement of MOSFETs of the memory cell. In FIGS. 6 to 8, the positions of the cross section shown in FIG. Each unit of the memory cell is indicated by a dashed line.

First, as shown in FIG. 5, an n-type well layer 1 and a p-type well layer 2 provided on a main surface of a semiconductor substrate (not shown) via a separation layer (not shown) are formed. Each element formation region is separated by the SGI element isolation film 3, and the FETs Qp ', Qnd', Qnd ', Q
nt ′ source and drain regions 4 are provided, respectively.
A gate electrode 6 is provided via a gate insulating film 5 on the main surface of the semiconductor substrate between the source region 4 and the drain region 4 of each FET.

The source region and the drain region 4 have an LDD structure including a low concentration region 4a and a high concentration region 4b, and 4c is a pocket region of the source region and the drain region. The conductive type is opposite to that of the region 4b. That is, n-type FETs Qnd and Qn
For d ′, Qnt and Qnt ′, the low-concentration region 4a and the high-concentration region 4b are n-type diffusion layers,
c is a p-type diffusion layer. For p-type FETs Qp and Qp ′, low-concentration region 4a and high-concentration region 4b are p-type diffusion layers, and pocket region 4c is an n-type diffusion layer.

The gate electrode 6 is a polycide film in which a polycrystalline silicon 6a and a tungsten silicide 6b are sequentially laminated. A cap 7 made of silicon nitride (Si ₃ N ₄ ) is provided on the upper surface, and a cap 7 is provided on the side surface. A sidewall 8 made of silicon nitride is formed. Gate electrode 6
Outside the element formation region, functions as a wiring for interconnecting word lines or gate electrodes.

On the main surface of the semiconductor substrate, silicon oxide (SiO 2)
₂ ), an insulating film 9a covering the main surface is formed, a first polycrystalline silicon film 10 is formed thereon,
Second polycrystalline silicon film 11 with thin insulating film 9b interposed
Is formed, and the polycrystalline silicon films 10 and 11 form S
Form TC.

Further, an insulating film 9c made of silicon oxide and covering the polycrystalline silicon film 11 is deposited on the entire main surface to form an interlayer insulating film 9 made of insulating films 9a, 9b and 9c.
On this, a first-layer metal wiring 12 made of titanium or titanium nitride is formed thin. Then, after a thin interlayer insulating film 13 made of silicon oxide covering the metal wiring 12 is formed on the entire surface, a second-layer metal wiring 14 is formed.

The connection between the metal wiring 12 of the first layer and a predetermined region of the main surface of the semiconductor substrate is performed by connecting the plug 1 through the interlayer insulating film 9.
The connection between the metal wiring 14 of the second layer and a predetermined region of the semiconductor substrate main surface is performed by a plug 16 penetrating through the interlayer insulating film 9 and the interlayer insulating film 13. Plug 1
Reference numerals 5 and 16 each have a structure in which tungsten is coated with titanium or titanium nitride serving as a barrier metal or a cap. The plug 15 is formed penetrating through the polycrystalline silicon films 10 and 11 constituting the STC. The contact between the side surfaces of the polycrystalline silicon films 10 and 11 and the side surface of the plug 15 causes the polycrystalline silicon films 10 and 11 to be connected to the plug 15. Are conducted.

After this, a third-layer metal wiring (to be described later) is further formed via an interlayer insulating film, and the third-layer metal wiring forms a bit line.

In the memory cell of this embodiment, the driving MO
SFETs Qnd, Qnd ′ and load MOSFETs Qp,
Storage nodes Ns, N to which the drains of Qp 'are connected
The plug 15 to s ′ is a borderless contact with each SGI element isolation film, and an opening for connecting the storage node and the driving MOSFET is formed by an error in mask alignment or the like as illustrated in the figure. Even if it moves to the right, the progress of etching is absorbed by the thickness of the SGI element isolation insulating film 3. The opening of the plug 15 is opened so that the silicon nitride film 7 on the gate electrodes 6 of Qnd and Qnd ′ also penetrates.

On the other hand, the opening of the plug 16 is opened to be SAC with respect to the adjacent gate electrode. SAC is advantageous for miniaturization because the alignment margin can be reduced.
In the SAC, the cap 7 and the sidewall 8 of the gate electrode 6 are made of, for example, silicon nitride, and the insulating film 9 is made of silicon oxide. By slowing down the progress, even if the opening covers the cap 7 or the sidewall 8, the exposure of the gate electrode 6 by etching is prevented, and the opening is formed by self-alignment.

A predetermined portion of the polycrystalline silicon films 10 and 11 is also removed by etching the opening of the plug 15, and the side surfaces thereof are exposed to the opening, and the polycrystalline silicon films 10 and 11 are connected to the plug 15 by this portion. , 1
It is not necessary to provide an opening and a plug to connect the storage node with the STC constituted by 1.

After the plugs 15 are formed, the drain regions 4 forming the nodes are connected by the first-layer metal wirings 12 that allow openings, and one or two of the four openings are formed.
This is opened over the gate electrode 6 of the other inverter.

Further, three-layer metal wirings 12, 14, 17
The first layer wiring 12 is a connection wiring for each element in the memory cell, the second layer wiring 14 is a power supply wiring 14a and a ground wiring 14b, the third layer wiring 17 is a bit line wiring, The third-layer wiring 17 is connected via a landing pad 14c formed by the second-layer wiring 14.

FIG. 6 shows a MOSFET constituting a memory cell.
FIG. 4 is a plan view showing an arrangement of each of the F cells constituting a memory cell.
The drain region 4 serving as a node of the ETQnt, Qnd or the FET Qnt ′, Qnd ′ is formed continuously, and is connected to a plug 15 (hatched) connected to the first-layer metal wiring 12.

The source regions 4 of the FETs Qnd and Qnd ′ are respectively drawn out by plugs 16 and connected to the ground wiring GND in the upper layer. The source regions 4 of the FETs Qnt and Qnt ′ are drawn out by the plug 16 and the bit lines in the upper layer. Connected to.

The gate electrodes 6 of the FETs Qnt and Qnt 'are formed integrally and extend as word lines. FETQ
The gate electrodes 6 of nd and Qp are also integrally formed, and the FET Q
The gate electrodes 6 of nd ′ and Qp ′ are also integrally formed, each partially extending on the drain region 4 serving as the node, and connected to the plug 15 at this portion.

The drain region 4 of each of the FETs Qp and Qp ′ is drawn out by a plug 15 and connected to the first-layer metal wiring 12, which is electrically connected to the node by the metal wiring 12, and the source regions 4 of the FETs Qp and Qp ′ are respectively formed. It is pulled out by the plug 16 and connected to the power supply wiring Vcc.

FIG. 7 is a plan view showing the arrangement of the STC.
The polycrystalline silicon film 10 and the polycrystalline silicon film 11 constituting the STC have a pattern symmetrical with each other with respect to the memory cell boundary, and a capacitance is formed in an overlapping portion by changing layers.

For the sake of explanation, the first-layer polycrystalline silicon film 10 is hatched to the lower right, and the second-layer polycrystalline silicon film 11 is hatched to the right. Therefore, S is set at a portion where the respective polycrystalline silicon films 10 and 11 overlap, that is, at a portion where oblique lines in the figure cross each other to form a mesh.
This means that TC is formed.

The first polycrystalline silicon film 10 has a plug 1
5, the drain regions 4 of the FETs Qp 'and Qnd'
And the second polycrystalline silicon film 11 is composed of FETs Qp and Qn.
d is connected to the drain region 4. Therefore, this STC is the capacitance Cs, com between the nodes shown in FIG. Further, the polycrystalline silicon films 10 and 11 also overlap with the polycrystalline silicon films 11 and 10 of another adjacent memory cell, and a capacitance is formed between the adjacent polycrystalline silicon films 11 and 10 of the other memory cell.

FIG. 8 is a plan view showing the arrangement of the metal wirings.
The metal wiring 12 of the layer is indicated by a broken line, and the metal wiring 17 of the third layer which is the upper layer is indicated by a two-dot chain line. The second layer metal wiring 14 forms a landing pad 14c, a ground wiring 14b, and a power supply wiring 14a for the bit line. Here, the storage capacitors Csg, Csg are located at the portions where the first-layer metal wiring 15 and the ground wiring 14b overlap.
g 'is formed, and the capacitance can be increased by forming the insulating film 9c thin.

Next, a method of manufacturing the memory cell shown in FIGS. 5 to 8 will be described with reference to FIGS. Each of FIGS. 9 to 17 shows a vertical cross-sectional view along the line aa in FIGS. 6 to 8 for each process, similarly to FIG.

First, steps up to a state where the MOSFET shown in FIG. 9 is formed will be described. An n-type well layer 1 and a p-type well layer 2 provided on the main surface of a semiconductor substrate (not shown) via an isolation layer (not shown)
To separate each element formation region. A gate insulating film 5 is formed in each element formation region by thermal oxidation.

Subsequently, a polycide film in which a polycrystalline silicon 6a and a tungsten silicide 6b are sequentially laminated is deposited, silicon nitride (Si ₃ N ₄ ) is further deposited on the entire surface, and patterning using photolithography is performed. 6 and a cap 7 for the gate electrode 6 are formed. The gate electrode 6 functions as a word line or a wiring connecting the gate electrodes to each other outside the element formation region.

Subsequently, by ion implantation using the gate electrode 6 as a mask, the lightly doped source region and drain region 4a of the n-type MOSFET, the p-type pocket region 4c of the n-type MOSFET, the lightly doped source region of the p-type MOSFET, The drain region 4a and the n-type pocket region 4c of the p-type MOSFET are formed. Further, silicon nitride is deposited on the entire surface and etched to form a side wall 8 covering the side surface of the gate electrode 6, and ion implantation is performed using the gate electrode 6 and the side wall 8 as a mask to form an n-type MOSF.
ET high concentration source region, drain region 4b and p-type M
A high concentration source region and a drain region 4b of the OSFET are formed. This state is shown in FIG.

Next, as shown in FIG. 10, after an insulating film 9a made of silicon oxide (SiO ₂ ) is deposited on the entire surface,
A first polycrystalline silicon film 10 is formed, and a thin insulating film 9 is formed.
A second-layer polycrystalline silicon film 11 is formed through the layer b, and an STC is formed by the polycrystalline silicon films 10 and 11.

Next, as shown in FIG. 11, an insulating film 9c made of silicon oxide is deposited on the entire surface and flattened.
An opening is formed by etching a predetermined region connected to the metal wiring 12 of the layer. In this etching, the opening for connecting the drain region 4 of the driving MOSFETs Qnd and Qnd ′ serving as storage nodes to the metal wiring 12 is moved to the left as shown in the figure due to a mask alignment error or the like. The borderless contact absorbs the progress of the etching by the thickness of the SGI element isolation insulating film 3.

Next, as shown in FIG.
The opening of the ET formation region is covered with the resist mask 18 and ions of arsenic (As) are implanted to lower the resistance of the contact region which is an opening for SGI.

Next, as shown in FIG.
The opening of the ET formation region is covered with a resist mask 19 and ion implantation of boron fluoride (BF ₂ ) or the like is performed to lower the resistance of the contact region which is an opening for SGI.

Next, as shown in FIG. 14, the opening is filled with a plug 15. The plug 15 has a structure in which tungsten is coated with titanium or titanium nitride serving as a barrier metal or a cap. By the plug 15, the side surfaces of the polycrystalline silicon films 10, 11 and the side surface of the plug 15 are connected.

Next, as shown in FIG. 15, a first-layer metal wiring 12 made of titanium or titanium nitride connected to the plug 15 is formed.

Next, as shown in FIG. 16, a thin interlayer insulating film 13 made of silicon oxide is deposited on the entire surface, and then the interlayer insulating film 9 in a predetermined region connected to the second-layer metal wiring is formed.
13 is provided with an opening by etching. In this etching, silicon nitride is etched at a high selectivity with a low etching rate of silicon nitride, and by utilizing the difference in the etch selectivity with respect to each material, the silicon nitride cap 7 and the side wall, which are difficult to progress, are etched. In FIG. 16, an opening for connecting the FET Qnd 'and the ground wiring 14b, an opening for connecting the source region 4 of the FET Qp' and the power supply wiring 14a, and a source region 4 of the FET Qnt 'are formed. An opening for connecting the bit line landing pad 14c to the bit line landing pad 14c is a SAC. At the same time, power supply wiring 14
a, ground wiring 14b, and landing pad 14c
Each has a borderless contact with the GI.

Next, as shown in FIG. 17, the opening is filled with a plug 15. The plug 15 has a structure in which tungsten is coated with titanium or titanium nitride serving as a barrier metal or a cap.

Thereafter, the power supply wiring 14c and the ground wiring 14b
Alternatively, the second-layer metal wiring 14 serving as the bit line landing pad 14a is formed, and the state shown in FIG. 5 is obtained. Although not shown, a third-layer metal wiring forming an interlayer insulating film and a bit line is further formed thereafter.

(Embodiment 2) A method of forming a thin silicon nitride film serving as a cap 7 at a predetermined portion of the gate electrode 6 in order to make a connection with the plug 15 will be described. FIGS. 18 to 23 show examples in which the size of the memory cell is reduced.

FIG. 18 is a plan view of the memory cell. The thickness of the cap 7 in the hatched portion of the gate electrode 6 in the figure is formed to be small.

FIGS. 19 to 23 are longitudinal sectional views showing a memory cell in each step. First, as shown in FIG. 19, a gate insulating film 5 is formed on the entire main surface of the semiconductor substrate by thermal oxidation.
Subsequently, a polycide film in which a polycrystalline silicon 6a and a tungsten silicide 6b are sequentially stacked is deposited, and silicon nitride 7a is deposited on the entire surface except for a region where the film thickness is reduced.

Next, as shown in FIG. 20, after further depositing silicon nitride 7b on the entire surface, as shown in FIG. 21, patterning using photolithography is performed, and gate electrode 6 and cap 7 of gate electrode 6 are formed. Is formed, the cap 7 at a predetermined portion can be formed thin.

With this configuration, the etching amount is set so that the cap 7 in the predetermined portion, which is formed thin, is removed but the cap 7 in the other portion is not removed during the etching for forming the opening in the interlayer insulating film 9. I do. Therefore, FIG.
8, a drain region 4 serving as a storage node as indicated by a broken line
Is directly connected to the plug 15 connected to the plug. Therefore, the gate electrode 6 is connected to the plug 15, and it is not necessary to separately provide a plug for connecting the gate electrode 6 and the storage node, and the memory cell size can be reduced.

Next, as shown in FIG. 22, an n-type MOSF is formed by ion implantation using the gate electrode 6 as a mask.
ET low concentration source region, drain region 4a and n-type M
OSFET p-type pocket region 4c, p-type MOSFET
Low concentration source region, drain region 4a and p-type MOS
An n-type pocket region 4c of the FET is formed. Further, silicon nitride is deposited on the entire surface and etched to form a gate electrode 6.
A sidewall 8 covering the side surface of the gate electrode 6 is formed.
Then, the high-concentration source and drain regions 4b of the n-type MOSFET and the high-concentration source and drain regions 4b of the p-type MOSFET are formed by ion implantation using the sidewalls 8 as a mask.

Next, as shown in FIG. 23, after an insulating film 9a made of silicon oxide (SiO ₂ ) is deposited on the entire surface,
A first polycrystalline silicon film 10 is formed, and a thin insulating film 9 is formed.
b, a second layer polycrystalline silicon film 11 is formed, an STC is formed by the polycrystalline silicon films 10 and 11, and an insulating film 9c made of silicon oxide is deposited on the entire surface and planarized. An opening is formed by etching a predetermined region connected to the metal wiring 12 of the eye.

In this etching, the opening for connecting to the drain region 4 of the FET Qnd ′ is SAC with respect to the cap 7 and the side wall 8 of the gate electrode 6 of the FET Qnd ′. The opening for connecting to the gate electrode 6 of the FET Qp 'is
It has become. For this reason, a margin for alignment in consideration of a mask alignment error or the like can be reduced, which is advantageous for miniaturization.

In this etching, since the thickness of the silicon nitride to be the cap 7 in the predetermined portion is set thin, the cap 7 in the predetermined portion is removed and the gate electrode 6 is partially exposed. Becomes

Thereafter, the opening is filled with a plug 15 to form a first-layer metal interconnection 12 made of titanium or titanium nitride to be connected to the plug 15, and an interlayer insulating film 13 made of silicon oxide is deposited thinly over the entire surface. After
An opening is formed in the interlayer insulating films 9 and 13 in a predetermined region connected to the metal wiring 14 of the layer, and an opening is provided. The opening is filled with a plug 15, and a power wiring 14a, a ground wiring 14b or a bit line landing pad 14c is formed.
The second layer metal wiring 14 is formed as shown in FIG. In FIG. 24, for comparison, the memory cells of the above-described embodiment are also shown below, and the corresponding reduced portions are indicated by broken lines.

(Embodiment 3) This embodiment is the same as the above-described embodiment up to the state where the interlayer insulating film 9 is formed, but thereafter, as shown in FIG. An opening for connecting to the region is provided, and this opening is filled with a plug 20 of polycrystalline silicon doped with phosphorus (P) to the capacity limit.

Next, as shown in FIG. 26, an opening for connecting to the p-type region is formed by etching, and ion implantation of boron fluoride (BF ₂ ) or the like is performed. In this implantation, ion implantation is also performed on the plug 20, but since the plug 20 is doped with phosphorus at a high concentration, the plug 20 does not change to a p-type.

Next, as shown in FIG. 27, the opening is filled with a plug 15.

Thereafter, a first-layer metal wiring 12 made of titanium or titanium nitride connected to the plugs 15 and 20 is formed, and a thin interlayer insulating film 13 made of silicon oxide is deposited on the entire surface. An opening is formed in the interlayer insulating films 9 and 13 in a predetermined region connected to the metal wiring, and the opening is buried with a plug 15 to form a power supply wiring 14a, a ground wiring 14b, or a bit line landing pad 14c. The metal wiring 14 of the eye is formed, and the state shown in FIG. 28 is obtained.

In the present embodiment, the number of masks can be reduced as compared with the above-described embodiment at the time of ion implantation for forming the diffusion layer in self-alignment with the opening. In this embodiment, the plug connected to the n-type region is made of polycrystalline silicon with a high impurity concentration, but the plug connected to the p-type region may be made of polycrystalline silicon with a high impurity concentration.

FIG. 29 shows an application example including a CMOS type peripheral circuit in the above-described memory cell, and FIG. 30 shows an application example including a BiCMOS type peripheral circuit. In FIG. 30, 2
1 is a p-type semiconductor substrate, 22 is a deep n-type isolation layer, and 23 is a p-type semiconductor substrate.
The type separation layer 24 is an n-type buried layer. In the case of a BiCMOS type, n serves as a collector of a bipolar transistor.
High concentration antimony (Sb), arsenic (A
Since s) is included, the lateral extension of the n-type buried layer 24 increases, so that the n-type well 2 is formed in a recessed region in the memory cell as shown in the figure.

Next, FIGS. 31 and 32 show modifications of the above-described embodiment for further increasing the storage capacity.

In the example shown in FIG. 31, the polycrystalline silicon film forming the STC is further multi-layered. In FIG. 31, the polycrystalline silicon film has four layers, and the even-numbered polycrystalline silicon film excluding the gate electrode 6 is formed. The films 10a and 10b are formed in the same pattern, and the odd-numbered polycrystalline silicon films 11a and 11b are formed in the same pattern.

Even-numbered polycrystalline silicon films 10a and 10b
Are connected to the same plug 15 on the side surface, and the odd-numbered polycrystalline silicon films 11a and 11b are connected to the other plugs 15 and 16 on the side surface.

With this structure, the polycrystalline silicon film 10
a-polycrystalline silicon film 11a, polycrystalline silicon film 11
a-polycrystalline silicon film 10b, polycrystalline silicon film 10
Capacitors are formed between the b-polycrystalline silicon film 11b, respectively, and the storage capacity can be increased.

It is conceivable that the stepped shape may become a problem by making the polycrystalline silicon film more multilayer. Therefore, in the example shown in FIG. 31, the insulating film 9a is flattened to form the polycrystalline silicon films 10a and 10b. , 11a, 11
b is formed flat.

In the example shown in FIG. 32, the element isolation between the drain regions 4 of the FETs Qp ′ and Qnd ′ serving as the memory cell storage nodes is formed as an element isolation film 25 by LOCOS, and the p-type well 1-n type well 2 of the memory cell is used. Other element isolation such as between the p-type well 1 and n-type well 2 of the memory cell and the FET of the peripheral circuit is performed by the trench type SGI element isolation film 3. In contrast to the trench type element isolation, the peripheral component of the diffusion capacitance is reduced. In this configuration, the element isolation between the drain regions 4 serving as the storage nodes is further improved by using the LOCOS element isolation film 25. It is possible to positively increase the storage capacity.

As described above, the invention made by the present inventor is:
Although a specific description has been given based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention.

[0091]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

(1) According to the present invention, there is an effect that a conductor film constituting a capacitor can be formed on a main surface of a semiconductor substrate via an insulating film.

(2) According to the present invention, since the side surface of the conductor film constituting the capacitor is connected to the side surface of the plug, there is an effect that the connection of the capacitor is facilitated.

(3) According to the present invention, there is an effect that a capacitance can be formed by a wiring layer.

(4) According to the present invention, the above effect (1)
According to (3), there is an effect that the soft error resistance is improved.

(5) According to the present invention, the above effect (1)
According to (2), there is an effect that the memory cell size is not increased when forming the storage capacitor.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an SRAM type memory cell.

FIG. 2 is a longitudinal sectional view showing a memory cell of a semiconductor memory device implemented conventionally.

FIG. 3 is a plan view showing a memory cell of a semiconductor memory device implemented conventionally.

FIG. 4 is a plan view showing a memory cell of a semiconductor memory device implemented conventionally.

FIG. 5 is a longitudinal sectional view showing a memory cell of the semiconductor memory device according to one embodiment of the present invention;

FIG. 6 is a plan view showing a memory cell of the semiconductor memory device according to one embodiment of the present invention;

FIG. 7 is a plan view showing a memory cell of the semiconductor memory device according to one embodiment of the present invention;

FIG. 8 is a plan view showing a memory cell of the semiconductor memory device according to one embodiment of the present invention;

FIG. 9 is a longitudinal sectional view showing a memory cell of a semiconductor memory device according to an embodiment of the present invention for each process.

FIG. 10 is a longitudinal sectional view showing a memory cell of a semiconductor memory device according to an embodiment of the present invention for each process.

FIG. 11 is a longitudinal sectional view showing, for each step, a memory cell of the semiconductor memory device according to the embodiment of the present invention;

FIG. 12 is a longitudinal sectional view showing a memory cell of a semiconductor memory device according to an embodiment of the present invention for each process.

FIG. 13 is a longitudinal sectional view showing a memory cell of a semiconductor memory device according to an embodiment of the present invention for each process.

FIG. 14 is a longitudinal sectional view showing a memory cell of a semiconductor memory device according to an embodiment of the present invention for each process.

FIG. 15 is a longitudinal sectional view showing a memory cell of a semiconductor memory device according to an embodiment of the present invention for each process;

FIG. 16 is a longitudinal sectional view showing a memory cell of a semiconductor memory device according to an embodiment of the present invention for each process;

FIG. 17 is a longitudinal sectional view showing, for each step, a memory cell of the semiconductor memory device according to the embodiment of the present invention;

FIG. 18 is a plan view showing a memory cell of a semiconductor memory device according to another embodiment of the present invention.

FIG. 19 is a longitudinal sectional view showing a memory cell of a semiconductor memory device according to another embodiment of the present invention for each process.

FIG. 20 is a longitudinal sectional view showing a memory cell of a semiconductor memory device according to another embodiment of the present invention for each process.

FIG. 21 is a longitudinal sectional view showing a memory cell of a semiconductor memory device according to another embodiment of the present invention for each step.

FIG. 22 is a longitudinal sectional view showing a memory cell of a semiconductor memory device according to another embodiment of the present invention for each process.

FIG. 23 is a longitudinal sectional view showing a memory cell of a semiconductor memory device according to another embodiment of the present invention for each process.

FIG. 24 is a longitudinal sectional view showing a memory cell of a semiconductor memory device according to another embodiment of the present invention for each process.

FIG. 25 is a longitudinal sectional view showing a memory cell of a semiconductor memory device according to another embodiment of the present invention for each process.

FIG. 26 is a longitudinal sectional view showing a memory cell of a semiconductor memory device according to another embodiment of the present invention for each process.

FIG. 27 is a longitudinal sectional view showing a memory cell of a semiconductor memory device according to another embodiment of the present invention for each process.

FIG. 28 is a vertical sectional view showing a memory cell of a semiconductor memory device according to another embodiment of the present invention for each process.

FIG. 29 is a longitudinal sectional view showing a memory cell and a CMOS type peripheral circuit of the semiconductor memory device according to the embodiment of the present invention;

FIG. 30 is a longitudinal sectional view showing a memory cell and a BiCMOS type peripheral circuit of the semiconductor memory device according to the embodiment of the present invention;

FIG. 31 is a longitudinal sectional view showing a modification of the memory cell of the semiconductor memory device according to the embodiment of the present invention;

FIG. 32 is a longitudinal sectional view showing a modified example of the memory cell of the semiconductor memory device according to the embodiment of the present invention;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... n-type well, 2 ... p-type well, 3 ... SGI element isolation film, 4 ... source region, drain region, 4a ... low concentration region, 4b ... high concentration region, 4c ... pocket region, 5 ... gate insulating film, 6 ... gate electrode, 6a ... polycrystalline silicon, 6
b: silicide, 7: cap, 7a, 7b: silicon nitride, 8: sidewall, 9: interlayer insulating film, 9a, 9
b, 9c: insulating film, 10, 11: polycrystalline silicon film, 1
2, 14, 17: metal wiring, 14a: power supply wiring, 14
b: ground wiring, 14c: landing pad, 15, 1
6, 20: plug, 18, 19: resist mask, 21
... semiconductor substrate, 22 ... n-type separation layer, 23 ... p-type separation layer,
24: n-type buried layer; 25: LOCOS element isolation film.

──────────────────────────────────────────────────の Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 27/092 27/10 491

Claims (15)

[Claims] In a semiconductor memory device having an SRAM type memory cell for storing information in a storage node, a conductor film constituting a capacitor is formed on a main surface of a semiconductor substrate via an insulating film, and a layer above the conductor film is formed. A plug that connects the wiring layer of the semiconductor substrate and a semiconductor region serving as a storage node on the main surface of the semiconductor substrate penetrates the conductive film, and a side surface of the plug is connected to a side surface of the conductive film. Storage device. 2. The semiconductor memory device according to claim 1, wherein the conductive film forms a capacitance between storage nodes of the same memory cell of the SRAM and between storage nodes of adjacent memory cells. 3. The semiconductor memory device according to claim 1, wherein a plurality of conductive films constituting said capacitor are provided. 4. The semiconductor memory device according to claim 1, wherein said conductive film is made of polycrystalline silicon, and said plug is made of metal. 5. The semiconductor device according to claim 1, wherein each of the conductor films constituting the capacitor has a pattern which is line-symmetric with respect to a memory cell boundary, and is formed by changing layers. The semiconductor memory device according to claim 1. 6. A semiconductor memory device having an SRAM type memory cell for storing information in a storage node, comprising: a first wiring layer forming the storage node and connecting to a semiconductor region formed on a main surface of a semiconductor substrate; A semiconductor memory device, wherein a capacitor is formed by a second wiring layer formed above a wiring layer. 7. An insulating film provided between said first wiring layer and said second wiring layer and said first wiring layer are formed thin,
7. The semiconductor device according to claim 6, wherein the second wiring layer and the semiconductor region of the semiconductor substrate are directly connected by a plug.
3. The semiconductor memory device according to claim 1. 8. The semiconductor memory device according to claim 6, wherein said upper wiring layer is at a ground potential. 9. The semiconductor memory device according to claim 1, wherein a semiconductor region forming a storage node of said memory cell is separated by a LOCOS element isolation film. . 10. The device according to claim 9, wherein device isolation between semiconductor regions forming storage nodes of said memory cells is performed by a LOCOS device isolation film, and another device isolation is performed by a trench type device isolation film. 13. The semiconductor memory device according to claim 1. 11. An SRAM for storing information in a storage node
Forming a FET constituting a memory cell on a main surface of a semiconductor substrate; forming an insulating film covering the FET on the main surface of the semiconductor substrate; Forming a conductive layer constituting a capacitor on the film; forming an insulating film covering the conductive layer; providing an opening that penetrates the insulating film and the conductive layer and exposes a semiconductor region of the FET. And a step of filling the opening with a conductor serving as a plug and connecting the conductor to a side surface of the conductor layer. 12. A cap covering the gate electrode of the FET and a material having different etching selectivity between the insulating film and the cap, wherein an etching rate of the cap is made lower than an etching rate of the insulating film. Item 1
2. The method for manufacturing a semiconductor memory device according to item 1. 13. The device according to claim 1, wherein the gate electrode connected to the storage node is partially extended to the opening, and a cap covering this portion is formed thinner than a cap covering another portion. 13. The method for manufacturing a semiconductor memory device according to item 12. 14. An impurity is implanted from the opening,
14. The method according to claim 11, wherein a diffusion layer is formed by self-alignment with the opening. 15. The method according to claim 15, wherein the implantation of the impurity from the opening is performed by n-type storage nodes using polycrystalline silicon containing an n-type impurity embedded in the opening, and the p-type storage nodes are implanted by ion implantation. The method for manufacturing a semiconductor memory device according to claim 14, wherein